X5001 CPU Supervisor Features DESCRIPTION • 200ms Power On Reset Delay • Low Vcc Detection and Reset Assertion —Five Standard Reset Threshold Voltages —Adjust Low Vcc Reset Threshold Voltage using special programming sequence —Reset Signal Valid to Vcc=1V • Selectable Nonvolatile Watchdog Timer —0.2, 0.6, 1.4 seconds —Off selection —Select settings through software • Long Battery Life With Low Power Consumption —<50µA Max Standby Current, Watchdog On —<1µA Max Standby Current, Watchdog Off • 2.7V to 5.5V Operation • SPI Mode 0 interface • Built-in Inadvertent Write Protection —Power-Up/Power-Down Protection Circuitry —Watchdog Change Latch • High Reliability • Available Packages —8-Lead TSSOP —8-Lead SOIC —8 Pin PDIP This device combines three popular functions, Power on Reset, Watchdog Timer, and Supply Voltage Supervision in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The Watchdog Timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET signal after a selectable time-out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The user’s system is protected from low voltage conditions by the device’s low Vcc detection circuitry. When Vcc falls below the minimum Vcc trip point, the system is reset. RESET is asserted until Vcc returns to proper operating levels and stabilizes. Five industry standard VTRIP thresholds are available, however, Xicor’s unique circuits allow the thresold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The device utilizes Xicor’s proprietary Direct WriteTM cell for the Watchdog TImer control bits and the VTRIP storage element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years. Block Diagram WATCHDOG TRANSITION DETECTOR SI SO WATCHDOG TIMER DATA REGISTER RESET & WATCHDOG TIMEBASE COMMAND SCK RESET DECODE & CONTROL CS/WDI LOGIC POWER ON/ LOW VOLTAGE RESET VCC + VTRIP GENERATION - 7036 FRM 01 Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending 7078 1.1 8/9/99 CM 1 Characteristics subject to change without notice X5001 PIN DESCRIPTION PIN (SOIC/PDIP) PIN TSSOP Name Function 1 1 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog timeout period results in RESET/RESET going active. 2 2 SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. 5 8 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. 9 SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or watchdog bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. 3 6 VPE VTRIP Program Enable. When VPE is LOW, the VTRIP point is fixed at the last valid programmed level. To readjust the VTRIP level, requires that the VPE pin be pulled to a high voltage (15-18V). 4 7 VSS Ground 8 14 VCC Supply Voltage 6 7 13 RESET 3-5,10-12 NC Reset Output. RESET is an active LOW, open drain output which goes active whenever Vcc falls below the minimum Vcc sense level. It will remain active until Vcc rises above the minimum Vcc sense level for 200ms. RESET goes active if the Watchdog Timer is enabled and CS/WDI remains either HIGH or LOW longer than the selectable Watchdog time-out period. A falling edge of CS/WDI will reset the Watchdog Timer. RESET goes active on power up at 1V and remains active for 200ms after the power supply stabilizes. No internal connections Figure 1. PIN CONFIGURATION 8 Lead TSSOP 8 Lead SOIC/PDIP 8 SCK VCC 2 7 SI CS/WDI SO 3 4 6 5 V SS VPE 2 CS/WDI 1 8 V CC SO VPE 2 7 RESET 6 SCK VSS 4 5 SI 3 X5001 1 X5001 RESET X5001 PRINCIPLES OF OPERATION To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the Vcc pin and tie the WPE pin to the programming voltage VP. Then a VTRIP programming command sequence is sent to the device over the SPI interface. This VTRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 01h (in order) and bringing CS HIGH. This initiates the VTRIP programming sequence. VP is brought LOW to end the operation. Power On Reset Application of power to the X5001 activates a Power On Reset Circuit. This circuit goes active at 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When Vcc exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET, allowing the processor to begin executing code. Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. Low voltage monitoring During operation, the X5001 monitors the VCC level and asserts RESET if supply voltage falls below a preset minimum VTRIP. The RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. It also remains active until Vcc returns and exceeds VTRIP for 200ms. To reset the VTRIP voltage, apply greater than 3V to the Vcc pin and tie the WPE pin to the programming voltage Vp. Then a VTRIP command sequence is sent to the device over the SPI interface. This VTRIP programming sequence consists of pulling CS LOW, then clocking in data 03h, 00h and 01h. This is followed by bringing CS HIGH then LOW and clocking in data 02h, 00h, and 03h (in order) and bringing CS HIGH. This initiates the VTRIP programming sequence. VP is brought LOW to end the operation. watchdog timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent a RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog timeout period. The state of two nonvolatile control bits in the Watchdog Register determine the watchdog timer period. Vcc Threshold Reset Procedure The X5001 is shipped with a standard Vcc threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5001 threshold may be adjusted. The procedure is described below, and requires the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. 3 X5001 Figure 2. Sample VTRIP Reset Circuit 4.7K VP 1 Adjust VTRIP Adj. 2 3 7 X5001 4 Run uC RESET 8 SCK SI 6 5 SO CS Figure 3. Set VTRIP Level Sequence (Vcc=desired VTRIP value. ) VPE = 15-18V VPE CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 SCK 16 BITS 16 BITS SI 03h 0001h 02h 0001h Figure 4. Reset VTRIP Level Sequence (Vcc > 3V. ) VPE = 15-18V VPE CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 SCK 16 BITS 16 BITS SI 03h 0001h 02h 4 0003h X5001 Figure 5. Vtrip Programming Sequence Vtrip Programming Execute Reset Vtrip Sequence Set Vcc = Vcc applied = Desired Vtrip New Vcc applied = Old Vcc applied + Error Execute Set Vtrip Sequence New Vcc applied = Old Vcc applied - Error Apply 5V to Vcc Execute Reset Vtrip Sequence Decrement Vcc (Vcc = Vcc - 50mV) NO RESET pin goes active? YES Error < 0 Measured Vtrip Desired Vtrip Error = 0 DONE 5 Error > 0 X5001 spi Interface Watchdog Change Latch The Watchdog Change Latch must be SET before a Write Watchdog Timer Operation is initiated. The Enable Watchdog Change (EWDC) instruction will set the latch and the Disable Watchdog Change (DWDC) instruction will reset the latch (See Figure 2.) This latch is automatically reset upon a power-up condition and after the completion of a valid nonvolatile write cycle. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device monitors the CS/WDI line and asserts RESET output if there is no activity within user selctable time-out period. The device also monitors the Vcc supply and asserts the RESET if Vcc falls below a preset minimum (VTRIP). The device contains an 8-bit Watchdog Timer Register to control the watchdog time-out period. The current settings are accessed via the SI and SO pins. Read Watchdog Timer Register Operation If there is not a nonvolatile write in progress, the Read Watchdog Timer instruction returns the setting of the watchdog timer control bits. The other bits are reserved and will return ’0’ when read. See Figure 3. All instructions (Table 1) and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. If a nonvolatile write is in progress, the Read Watchdog Timer Register Instruction returns a HIGH on SO. When the nonvolatile write cycle is completed, a seperate Read Watchdog Timer instruction should be used to determine the current status of the Watchdog control bits. Watchdog Timer Register 7 6 5 4 3 2 1 0 0 0 0 WD1 WD0 0 0 0 RESET Operation The RESET (X5001) output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the Watchdog timer has reached its programmable time-out limit. Watchdog Timer Control Bits The Watchdog Timer Control bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the Set Watchdog Timer (SWDT) instruction. Watchdog Control Bits WD1 WD0 Watchdog Time-out (Typical) 0 0 1.4 Seconds 0 1 600 Milliseconds 1 0 200 Milliseconds 1 1 Disabled The RESET output is an open drain output and requires a pull up resistor. Operational Notes The device powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. • SO pin is high impedance. • The Watchdog Change Latch is reset. • The RESET Signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: Write Watchdog Register Operation Changing the Watchdog Timer Register is a two step process. First, the change must be enabled with by setting the Watchdog Change Latch (see below). This instruction is followed by the Set Watchdog Timer (SWDT) instruction, which includes the data to be written (Figure 5). Data bits 3 and 4 contain the Watchdog settings and data bits 0, 1, 2, 5, 6 and 7 must be “0” . • A EWDC instruction must be issued to enable a change to the watchdog timeout setting. • CS must come HIGH at the proper clock count in order to implement the requested changes to the watchdog timeout setting. 6 X5001 Table 1. Instruction Set Definition Instruction Format Instruction Name and Operation 0000 0110 EWDC: Enable Watchdog Change Operation 0000 0100 DWDC: Disable Watchdog Change Operation 0000 0001 SWDT: Set Watchdog Timer control bits: Instruction followed by contents of register: 000(WD1) (WD0)000 See Watchdog Timer Settings and Figure 3. 0000 0101 RWDT: Read Watchdog Timer control bits Notes: Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first. 7038 FRM T03 Figure 1. Read Watchdog Timer setting CS 0 1 2 3 4 5 6 7 ... SCK RWDT INSTRUCTION ... SI W D 1 SO ... W D 0 Figure 2. Enable Watchdog Change/Disable Watchdog Change Sequence CS 0 1 2 3 4 5 SCK INSTRUCTION (1 BYTE) SI SO HIGH IMPEDANCE 7 6 7 X5001 Figure 3. Write Watchdog Timer Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK DATA BYTE INSTRUCTION 6 SI 5 HIGH IMPEDANCE SO 4 3 W D 1 W D 0 Figure 4. Read Nonvolatile Status (Option 1) (Used to determine end of Watchdog Timer store operation) CS 0 1 2 3 4 5 6 7 SCK RWDT INSTRUCTION SI NONVOLATILE WRITE IN PROGRESS SO SO HIGH During 1st bit while in the Nonvolatile write cycle Figure 5. Read Nonvolatile Status (Option 2) (Used to determine end of Watchdog Timer store operation) CS 0 1 2 3 4 5 6 7 SCK RWDT INSTRUCTION SI NONVOLATILE WRITE IN PROGRESS SO SO HIGH During Nonvolatile write cycle 8 X5001 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature under Bias ........................–65°C to +135°C Storage Temperature .............................–65°C to +150°C Voltage on any Pin with Respect to VSS....... –1.0V to +7V D.C. Output Current ....................................................5mA Lead Temperature (Soldering, 10 seconds)............ 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0°C +70°C Voltage Option Supply Voltage Limits 7036 FRM T07 –1.8 1.8V to 3.6V –2.7 or -2.7A 2.7V to 5.5V –4.5 or -4.5A 4.5V to 5.5V PT= Package, Temperature D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 VCC Write Current (Active) 5 mA SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open ICC2 VCC Read Current (Active) 0.4 mA SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open ISB1 VCC Standby Current WDT=OFF 1 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB2 VCC Standby Current WDT=ON 50 µA CS = VCC, VIN = VSS or VCC, VCC = 5.5V ISB3 VCC Standby Current WDT=ON 20 µA CS = VCC, VIN = VSS or VCC, VCC =3.6V ILI Input Leakage Current 0.1 10 µA VIN = VSS to VCC ILO Output Leakage Current 0.1 10 µA VOUT = VSS to VCC V Input LOW Voltage –0.5 VCCx0.3 VIH VOL1 Input HIGH Voltage VCCx0.7 VCC+0.5 V 0.4 V VCC > 3.3V, IOL = 2.1mA VOL2 Output LOW Voltage 0.4 V 2V < VCC < 3.3V, IOL = 1mA VOL3 Output LOW Voltage 0.4 V VOH1 Output HIGH Voltage VCC–0.8 V VCC ≤ 2V, IOL = 0.5mA VCC > 3.3V, IOH = –1.0mA VOH2 Output HIGH Voltage VCC–0.4 V 2V < VCC ≤ 3.3V, IOH = –0.4mA VOH3 Output HIGH Voltage VCC–0.2 V VOLRS Reset Output LOW Voltage VIL(1) (1) Output LOW Voltage 0.4 VCC ≤ 2V, IOH = –0.25mA IOL = 1mA V POWER-UP TIMING Symbol (2) tPUR (2) tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min. Max. Units 1 ms 5 ms Max. Units Conditions 8 pF VOUT = 0V 6 pF VIN = 0V CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol (2) COUT (2) CIN Notes: Test Output Capacitance (SO, RESET) Input Capacitance (SCK, SI, CS) (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 9 X5001 Figure 1. EQUIVALENT A.C. LOAD CIRCUIT 3V A.C. TEST CONDITIONS 5V Input Rise and Fall Times 3.3KΩ 1.64KΩ VCC x 0.1 to VCC x 0.9 Input Pulse Levels 10ns VCC x0.5 Input and Output Timing Level OUTPUT RESET 1.64KΩ 100pF 30pF A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing 1.8V–3.6V Symbol fSCK Clock Frequency tCYC Cycle Time 1000 500 ns tLEAD CS Lead Time 400 200 ns tLAG CS Lag Time 400 200 ns tWH Clock HIGH Time 400 200 ns tWL Clock LOW Time 400 200 ns tSU Data Setup Time 100 50 ns tH Data Hold Time 100 50 ns (3) Parameter 2.7V–5.5V Min. Max. Min. Max. Units 0 1 0 2 MHz tRI Input Rise Time 2 2 µs tFI(3) Input Fall Time 2 2 µs tCS CS Deselect Time tWC(4) Write Cycle Time 250 150 ns 10 10 ms Data Output Timing 1.8V–3.6V Symbol fSCK Clock Frequency tDIS Output Disable Time tV Output Valid from Clock Low tHO Output Hold Time tRO(3) Output Rise Time 300 150 ns tFO(3) Output Fall Time 300 150 ns Notes: Parameter 2.7V–5.5V Min. Max. Min. Max. Units 0 1 0 2 MHz 400 200 ns 400 200 ns 0 0 ns (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. 10 X5001 Figure 1. Data Output Timing CS t CYC tWH t LAG SCK tV SO SI tHO MSB OUT t WL tDIS MSB–1 OUT LSB OUT ADDR LSB IN Figure 2. Data Input Timing tCS CS tLEAD tLAG SCK tSU tH SI MSB IN SO HIGH IMPEDANCE tRI t FI LSB IN Figure 1. Symbol Table WAVEFORM 11 INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance X5001 Figure 1. Power-Up and Power-Down Timing VCC VTRIP V TRIP tPURST 0 Volts tPURST tF tRPD tR RESET (X5001) RESET Output Timing Symbol Min. Typ. Max. VTRIP Reset Trip Point Voltage, X5001PT-4.5A Reset Trip Point Voltage, X5001PT-4.5 Reset Trip Point Voltage, X5001PT-2.7A Reset Trip Point Voltage, X5001PT-2.7 Reset Trip Point Voltage, X5001PT-1.8 4.50 4.25 2.85 2.55 1.70 4.63 4.38 2.92 2.63 1.75 4.75 4.50 3.00 2.70 1.80 tPURST Power-up Reset Timeout 100 200 280 ms 500 ns (5) Parameter Units V tRPD VCC Detect to Reset/Output tF(5) VCC Fall Time 0.1 ns tR VCC Rise Time 0.1 ns VRVALID Reset Valid VCC 1 V (5) Notes: (5) This parameter is periodically sampled and not 100% tested. PT = Package, Temperature Figure 2. CS vs. RESET Timing CS t CST RESET t WDO tRST tWDO t RST RESET Output Timing Symbol Parameter Min. Typ. Max. Units tWDO Watchdog Timeout Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 1 200 600 1.4 300 800 2 ms ms sec tCST CS Pulse Width to Reset the Watchdog 400 tRST Reset Timeout 100 12 ns 200 300 ms X5001 VTRIP Programming Timing Diagram Vcc (VTRIP) VTRIP tTSU tTHD VP VPE tVPS tVPH tPCS CS tVPO tRP SCK SI 03h 0001h 02h 13 0001h or 0003h X5001 VTRIP Programming Parameters Parameter Description Min Max Units tVPS VTRIP Program Enable Voltage Setup time 1 µs tVPH VTRIP Program Enable Voltage Hold time 1 µs tPCS VTRIP Programming CS inactive time 1 µs tTSU VTRIP Setup time 1 µs tTHD VTRIP Hold (stable) time 10 ms tWC VTRIP Write Cycle Time tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0 us tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programmed Voltage Range 1.7 5.0 V -0.1 +0.4 V -25 +25 mV -25 +25 mV -25 +25 mV Vta1 Vta2 Vtr Vtv 10 Initial VTRIP Program Voltage accuracy (Vcc applied - VTRIP) (Programmed at 25oC.) Subsequent VTRIP Program Voltage accuracy [(Vcc applied - Vta1) - VTRIP. Programmed at 25oC.) VTRIP Program Voltage repeatability (Successive program operations. Programmed at 25oC.) VTRIP Program variation after programming (0-75oC). (Programmed at 25oC.) VTRIP Programming parameters are periodically sampled and are not 100% Tested. 14 ms X5001 Vcc Supply Current vs. Temperature (ISB) tWDO vs. Voltage/Temperature (WD1,0=1,1) 1.85 20 Watchdog Timer On (Vcc = 5V) 17 1.75 18 Reset (seconds) Isb (uA) 14 1.80 15 Watchdog Timer On (Vcc = 3V) 11 Watchdog Timer Off (Vcc = 3V, 5V) 0.55 0.35 –40C 1.65 –40°C 1.60 1.55 25°C 1.50 90°C 1.45 1.0 25C Temp (c) 1.70 1.40 1.7 90C VTRIP vs. Temperature (programmed at 25°C) 3.1 Voltage 4.5 tWDO vs. Voltage/Temperature (WD1,0=1,0) 0.85 5.025 Vtrip=5V 5.000 0.80 Reset (seconds) 4.975 Voltage 3.525 Vtrip=3.5V 3.500 3.475 2.525 25°C 0.70 90°C 0.65 0.60 1.7 2.475 0 25 Temperature 85 tPURST vs. Temperature 275 Reset (seconds) 270 265 260 255 250 245 240 25 Degrees °C 3.1 Voltage 4.5 tWDO vs. Voltage/Temperature (WD1,0 0=0,1) 280 Time (ms) 0.75 Vtrip=2.5V 2.500 235 –40 –40°C 0.30 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 25°C 90°C 1.7 90 –40°C 3.1 Voltage 15 4.5 X5001 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) PIN 1 INDEX PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7∞ 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) X 45∞ 0.050" TYPICAL 0.050" TYPICAL 0∞– 8∞ 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 16 0.030" TYPICAL 8 PLACES X5001 8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0∞– 8∞ Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 17 X5001 Ordering Information Vcc Range 4.5-5.5V 4.5-5.5V Vtrip Range 4.5.4.75 4.25.4.5 2.7-5.5V 2.85-3.0 2.7-5.5V 2.55-2.7 Package Operating Temperature Range PART NUMBER RESET (Active LOW) 8 pin PDIP 0oC - 70oC X5001P-4.5A 8L SOIC 0oC - 70oC X5001S8-4.5A 8L TSSOP 0oC - 70oC X5001V8-4.5A 8 pin PDIP 0oC - 70oC X5001P 8L SOIC 0oC - 70oC X5001S8 8L TSSOP 0oC - 70oC X5001V8 8L SOIC 0oC - 70oC X5001S8-2.7A 8L SOIC 0oC - 70oC X5001S8-2.7 0oC X5001V8-2.7 8L TSSOP 18 - 70oC X5001 Part Mark Information 8-Lead SOIC 8-Lead TSSOP X5001 YWW XX YWW XXXXX 501AG = 1.8 to 3.6V, 0 to +70°C, VTRIP=1.7-1.8V 501AH = 1.8 to 3.6V, -40 to +85°C, VTRIP=1.7-1.8V 501F = 2.7 to 5.5V, 0 to +70°C, VTRIP=2.55-2.7V 501G = 2.7 to 5.5V, -40 to +85°C, VTRIP=2.55-2.7V 501AN = 2.7 to 5.5V, 0 to +70°C, VTRIP=2.85-3.0V 501AP = 2.7 to 5.5V, -40 to +85°C, VTRIP=2.85-3.0V 501 = 4.5 to 5.5V, 0 to +70°C, VTRIP=4.25-4.5V 501I = 4.5 to 5.5V, -40 to +85°C, VTRIP=4.25-4.5V 501AL = 4.5 to 5.5V, 0 to +70°C, VTRIP=4.5-4.75V 501AM = 4.5 to 5.5V, -40 to +85°C, VTRIP=4.5-4.75V AG = 1.8 to 3.6V, 0 to +70°C, VTRIP=1.7-1.8V AH = 1.8 to 3.6V, -40 to +85°C, VTRIP=1.7-1.8V F = 2.7 to 5.5V, 0 to +70°C, VTRIP=2.55-2.7V G = 2.7 to 5.5V, -40 to +85°C, VTRIP=2.55-2.7V AN = 2.7 to 5.5V, 0 to +70°C, VTRIP=2.85-3.0V AP = 2.7 to 5.5V, -40 to +85°C, VTRIP=2.85-3.0V Blank = 4.5 to 5.5V, 0 to +70°C, VTRIP=4.25-4.5V I = 4.5 to 5.5V, -40 to +85°C, VTRIP=4.25-4.5V AL = 4.5 to 5.5V, 0 to +70°C, VTRIP=4.5-4.75V AM = 4.5 to 5.5V, -40 to +85°C, VTRIP=4.5-4.75V YWW = year/work week device is packaged. LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 19