ETC X84256V1425

MPS™ EEPROM
X84256
256K
µPort Saver EEPROM
FEATURES
DESCRIPTION
• 10MHz data transfer rate
• 30ns read access time
• Direct interface to microprocessors and microcontrollers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low power CMOS
—2.5V–3.6V
—Standby current less than 1µA
—Active current less than 3mA
• Byte or page write capable
—64-byte page write mode
• Typical nonvolatile write cycle time: 2ms
• High reliability
—1,000,000 endurance cycles
—Guaranteed data retention: 100 years
• Small packages options
—8-lead SOIC package
—14-lead TSSOP package
—8-lead XBGA package
The µPort Saver memories need no serial ports or
special hardware and connect to the processor memory bus. Replacing bytewide data memory, the µPort
Saver uses bytewide memory control functions, takes
a fraction of the board space and consumes much less
power. Replacing serial memories, the µPort Saver
provides all the serial benefits, such as low cost, low
power, low voltage, and small package size while
releasing I/Os for more important uses.
The µPort Saver memory outputs data within 30ns of
an active read signal. This is less than the read access
time of most hosts and provides “no-wait-state” operation. This prevents bottlenecks on the bus. With 10
MHz, the µPort Saver supplies data faster than
required by most host read cycle specifications. This
eliminates the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows
the µPort Saver to work well in 8-bit, 16 bit, 32-bit, and
64-bit systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Internal Block Diagram
MPS
System Connection
µP
µC
A15
WP
DSP
A0
D7
CE
ASIC
I/O
RISC
D0
Ports
Saved
P0/CS
P1/CLK
P2/DI
P3/DO
OE
OE
H.V. Generation
Timing & Control
Command
Decode
and
Control
Logic
X
DEC
EEPROM
Array
32K x 8
WE
WE
Y Decode
Data Register
REV 1.1 11/22/00
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Characteristics subject to change without notice.
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X84256
PIN CONFIGURATIONS
PIN DESCRIPTIONS
Drawings are to the same scale, actual package sizes
are shown in inches:
Chip Enable (CE)
8-Lead SOIC
CE
I/O
1
2
8
7
WP
VSS
3
4
6
5
VCC
NC
OE
WE
14-Lead TSSOP
CE
I/O
1
2
NC
3
X8401 11
4
10
5
9
6
NC
NC
WP
VSS
7
14
13
12
8
VCC
NC
NC
NC
NC
OE
WE
8-Lead XBGA
VCC
1
8
I/O
NC
2
7
CE
WE
3
6
VSS
OE
4
5
WP
Output Enable (OE)
The Output Enable input must be LOW to enable the
output buffer and to read data from the device on the I/O
line.
Write Enable (WE)
The Write Enable input must be LOW to write either
data or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to
or serially read from the device through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes
to the device are disabled. When WP is HIGH, all functions, including nonvolatile writes, operate normally. If a
nonvolatile write cycle is in progress, WP going LOW
will have no effect on the cycle already underway, but
will inhibit any additional nonvolatile write cycles.
DEVICE OPERATION
PIN NAMES
Pin
Description
I/O
Data Input/Output
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
WP
Write Protect Input
VCC
Supply Voltage
VSS
Ground
NC
No Connect
REV 1.1 11/22/00
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is deselected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
The X84256 serial EEPROM is designed to interface
directly with most microprocessor buses. Standard CE,
OE, and WE signals control the read and write operations, and a single l/O line is used to send and receive
data and commands serially.
Data Timing
Data input on the l/O line is latched on the rising edge
of either WE or CE, whichever occurs first. Data output
on the l/O line is active whenever both OE and CE are
LOW. Care should be taken to ensure that WE and OE
are never both LOW while CE is LOW.
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Characteristics subject to change without notice.
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X84256
Read Sequence
A read sequence consists of sending a 16-bit address,
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and
CE LOW, OE HIGH) to the part without a read cycle
between the write cycles. The address is sent serially,
most significant bit first, over the I/O line. Note that this
sequence is fully static, with no special timing restrictions, and the processor is free to perform other tasks
on the bus whenever the device CE pin is HIGH. Once
the 16 address bits are sent, a byte of data can be read
on the I/O line by issuing 8 separate read cycles (OE
and CE LOW, WE HIGH). At this point, writing a ‘1’ will
terminate the read sequence and enter the low power
standby state, otherwise the device will await further
reads in the sequential read mode.
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read.
The data stored in the memory at the next address can
be read sequentially by continuing to issue read
cycles. When the highest address in the array is
reached, the address counter rolls over to address
$0000 and reading may be continued indefinitely.
Reset Sequence
The reset sequence resets the device and sets an
internal write enable latch. A reset sequence can be
sent at any time by performing a read/write “0”/read
operation (see Figs. 1 and 2). This breaks the multiple
read or write cycle sequences that are normally used
to read from or write to the part. The reset sequence
can be used at any time to interrupt or end a sequential
read or page load. As soon as the write “0” cycle is
complete, the part is reset (unless a nonvolatile write
cycle is in progress). The second read cycle in this
sequence, and any further read cycles, will read a
HIGH on the l/O pin until a valid read sequence (which
includes the address) is issued. The reset sequence
must be issued at the beginning of both read and write
sequences to be sure the device initiates these operations properly.
REV 1.1 11/22/00
Write Sequence
A nonvolatile write sequence consists of sending a
reset sequence, a 16-bit address, up to 64-bytes of
data, and then a special “start nonvolatile write cycle”
command sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write
enable latch. The address is written serially by issuing
16 separate write cycles (WE and CE LOW, OE HIGH)
to the part without any read cycles between the writes.
The address is sent serially, most significant bit first, on
the l/O pin. Up to 64-bytes of data are written by issuing a multiple of 8 write cycles. Again, no read cycles
are allowed between writes.
The nonvolatile write cycle is initiated by issuing a special read/write “1”/read sequence. The first read cycle
ends the page load, then the write “1” followed by a
read starts the nonvolatile write cycle. The device recognizes 64-byte pages (e.g., beginning at addresses
XXXXXXXXX 000000 for X84256).
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
page, where data loading can continue. For this reason, sending more than 512 consecutive data bits will
result in overwriting previous data.
A nonvolatile write cycle will not start if a partial or
incomplete write sequence is issued. The internal write
enable latch is reset when the nonvolatile write cycle is
completed and after an invalid write to prevent inadvertent writes. Note that this sequence is fully static,
with no special timing restrictions. The processor is
free to perform other tasks on the bus whenever the
chip enable pin (CE) is HIGH.
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Characteristics subject to change without notice.
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X84256
Figure 1. Read Sequence
CE
OE
WE
"0"
I/O (IN)
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
I/O (OUT)
RESET
Load Address
Read Data
When Accessing: X84256 Array: A15 = 0
Figure 2. Write Sequence
CE
OE
WE
"0"
I/O (IN)
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
I/O (OUT)
RESET
Load Address
Load Data
When Accessing: X84256 Array: A15 = 0
Nonvolatile Write Status
The status of a nonvolatile write cycle can be determined at any time by simply reading the state of the l/O
pin on the device. This pin is read when OE and CE
are LOW and WE is HIGH. During a nonvolatile write
cycle the l/O pin is LOW. When the nonvolatile write
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START
Nonvolatile
Write
cycle is complete, the l/O pin goes HIGH. A reset
sequence can also be issued during a nonvolatile write
cycle with the same result: I/O is LOW as long as a
nonvolatile write cycle is in progress, and l/O is HIGH
when the nonvolatile write cycle is done.
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Characteristics subject to change without notice.
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X84256
Low Power Operation
The device enters an idle state, which draws minimal
current when:
Write Protection
A special “start nonvolatile write” command sequence is
required to start a nonvolatile write cycle (See Figure 2).
– an illegal sequence is entered. The following are the
more common illegal sequences:
SYMBOL TABLE
• Read/Write/Write—any time
WAVEFORM
• Read/Write ‘1’—When writing the address or writing
data.
• Write ‘1’—when reading data
• Read/Read/Write ‘1’—after data is written to
device, but before entering the NV write sequence.
• the device powers-up;
• a nonvolatile write operation completes.
While a sequential read is in progress, the device remains
in an active state. This state draws more current than
the idle state, but not as much as during a read itself.
To go back to the lowest power condition, an invalid
condition is created by writing a ‘1’ after the last bit of a
read operation.
REV 1.1 11/22/00
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INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
Will change
from LOW to
HIGH
May change
from HIGH to
LOW
Will change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
Characteristics subject to change without notice.
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X84256
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ....................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Terminal voltage with respect to VSS .......... –1V to +5V
DC output current................................................. 5mA
Lead temperature (soldering, 10 seconds).........300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indicated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X84256–2.5
2.5V to 3.6V
Industrial
–40°C
+85°C
–55°C
+125°C
†
Military
† Contact factory for availability.
D.C. OPERATING CHARACTERISTICS (VCC = 2.5V to 3.6V)
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
ICC1
Min.
Max.
Unit
VCC supply current (Read)
1
mA
OE = VIL, WE = VIH, I/O = Open, CE
clocking @ 10MHz
ICC2
VCC supply current (Write)
3
mA
ICC during nonvolatile write cycle all inputs
at CMOS levels
ISB1
VCC standby current
1
µA
CE = VCC, other inputs = VCC or VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
(1)
Input LOW voltage
–0.5
VCC x 0.3
V
(1)
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output LOW voltage
VOH
Output HIGH voltage
VlL
Note:
0.4
VCC – 0.4
Test Conditions
V
IOL = 1mA, VCC = 3V
V
IOH = –400µA, VCC = 3V
(1)VIL Min. and VIH Max. are for reference only and are not tested.
CAPACITANCE TA = +25°C, F = 1MHZ, VCC = 3V
Symbol
(2)
(2)
CI/O
CIN
Note:
Parameter
Max.
Unit
Test Conditions
Input/Output capacitance
8
pF
VI/O = 0V
Input capacitance
6
pF
VIN = 0V
(2) Periodically sampled, but not 100% tested.
REV 1.1 11/22/00
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Characteristics subject to change without notice.
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X84256
POWER-UP TIMING
Symbol
Max.
Unit
tPUR(3)
Power-up to Read operation
2
ms
(3)
Power-up to Write operation
5
ms
tPUW
Note:
Parameter
(3) Time delays required from the time the VCC is stable until the specific operation can be initiated. Periodically sampled, but not 100%
tested.
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUITS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
5ns
Input and Output timing levels
VCC x 0.5
3V
2.39KΩ
Output
4.58KΩ
30pF
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits–X84256
VCC = 2.5V–3.6V
Symbol
tRC
Read cycle time
tCE
CE access time
Min.
Max.
Unit
100
ns
30
ns
30
ns
tOE
OE access time
tOEL
OE pulse width
50
ns
tOEH
OE high recovery time
50
ns
tLOW
CE LOW time
50
ns
tHIGH
CE HIGH time
50
ns
(4)
CE LOW to output in low Z
0
ns
(4)
tLZ
CE HIGH to output in high Z
0
(4)
OE LOW to output in low Z
0
(4)
OE HIGH to output in high Z
0
Output hold from CE or OE HIGH
0
ns
tWES
WE HIGH setup time
25
ns
tWEH
WE HIGH hold time
25
ns
tHZ
tOLZ
tOHZ
tOH
Note:
Parameter
30
ns
ns
30
ns
(4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever
occurs first) to the time when I/O is no longer being driven into a 5pF load.
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Characteristics subject to change without notice.
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X84256
tRC
tLOW
tHIGH
tCE
CE
WE
tWES
tOEL
tOEH
tOE
OE
tWEH
tOHZ
I/O
HIGH Z
Data
tOLZ
tLZ
tOH
tHZ
Write Cycle Limits–X84256
VCC = 2.5V–3.6V
Symbol
(5)
tNVWC
Parameter
Min.
Nonvolatile write cycle time
Max.
Unit
5
ms
tWC
Write cycle time
100
ns
tWP
WE pulse width
35
ns
WE HIGH recovery time
65
ns
tCS
Write setup time
0
ns
tCH
Write hold time
0
ns
tCP
CE pulse width
35
ns
tCPH
CE HIGH recovery time
65
ns
tOES
OE HIGH setup time
25
ns
tOEH
tWPH
OE HIGH hold time
25
ns
(6)
Data setup time
20
ns
(6)
Data hold time
5
ns
tDS
tDH
(7)
WP HIGH setup
100
ns
(7)
WP HIGH hold
100
ns
tWPSU
tWPHD
Notes: (5) tNVWC is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write
cycle” sequence until the self-timed, internal nonvolatile write cycle is completed.
(6) Data is latched into the X84256 on the rising edge of CE or WE, whichever occurs first.
(7) Periodically sampled, but not 100% tested.
REV 1.1 11/22/00
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Characteristics subject to change without notice.
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X84256
CE Controlled Write Cycle
tCPH
tCP
CE
tOES
tOEH
OE
tCS
tCH
WE
WP
tWP
tWPSU
tWPH
tWPHD
tDS
I/O
tDH
HIGH Z
Data
tWC
WE Controlled Write Cycle
tCPH
tCP
CE
tOES
tCS
OE
WE
tCH
tOEH
tWPH
tWP
tWPHD
WP
tWPSU
tDS
I/O
tDH
HIGH Z
Data
tWC
REV 1.1 11/22/00
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Characteristics subject to change without notice.
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X84256
PACKAGING INFORMATION
8-Lead XBGA
Complete Part Number
X84256Z-2.5/B-2.5
X84256Z1-2.5/BI-2.5
Top Mark
XAAD
XACR
X84256: Bottom View
A1
VCC
1
8
I/O
NC
2
7
CE
WE
3
6
VSS
OE
4
5
WP
I/O
VCC
CE
NC
C
X84256: Top View
e
VSS
WE
WP
OE
E
E
D
D
A1
8-Lead XBGA
DWQ Symbol
Z
A
B
A
Contact Factory
Contact Factory
A1
Contact Factory
Contact Factory
C
Contact Factory
Contact Factory
D
Contact Factory
Contact Factory
E
Contact Factory
Contact Factory
e
Contact Factory
Contact Factory
F
Contact Factory
Contact Factory
NOTE: ALL DIMENSIONS IN µM
ALL DIMENSIONS ARE TYPICAL VALUES
REV 1.1 11/22/00
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Characteristics subject to change without notice.
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X84256
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050" Typical
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1 11/22/00
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Characteristics subject to change without notice.
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X84256
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.1 11/22/00
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Characteristics subject to change without notice.
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X84256
Ordering Information
X84256
X
X
–X
VCC Range
Blank = 2.5V to 3.6V, 10 MHz
Device
Temperature Range
25 = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Military = –55°C to +125°C (contact factory)
Packages
X84256
S8 = 8-Lead SOIC
V14 = 14-Lead TSSOP
Z = 8-Lead XBGA
B = 8-Lead XBGA
Part Mark Convention
14-Lead TSSOP
YWW
84256X
Blank = 2.5 to 3.6V, 0 to +70°C
I = 2.5 to 3.6V, -40 to +85°C
8-Lead XBGA
8-Lead SOIC
X84256 X
XX
Blank = 8-Lead SOIC
Blank = 2.5 to 3.6V, 0 to +70°C
I = 2.5 to 3.6V, -40 to +85°C
LIMITED WARRANTY
Complete Part Number
Top Mark
X84256Z–2.5
X84256ZI–2.5
X84256B–2.5
X84256BI–2.5
XABA
XABB
XABA
XABB
©Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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Characteristics subject to change without notice.
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