0 XC18V00 Series of In-System Programmable Configuration PROMs R DS026 (v3.5) June 14, 2002 0 0 Features • Product Specification • Dual configuration modes - Serial Slow/Fast configuration (up to 33 MHz) - Parallel (up to 264 Mb/s at 33 MHz) In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - Endurance of 20,000 program/erase cycles • 5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals - • 3.3V or 2.5V output capability • Available in PC20, SO20, PC44 and VQ44 packages • Design support using the Xilinx Alliance and Foundation series software packages. • JTAG command initiation of standard FPGA configuration Program/erase over full commercial/industrial voltage and temperature range • IEEE Std 1149.1 boundary-scan (JTAG) support • Simple interface to the FPGA • Cascadable for storing longer or multiple bitstreams • Low-power advanced CMOS FLASH process Description Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs (Figure 1). Initial devices in this 3.3V family are a 4-megabit, a 2-megabit, a 1-megabit, a 512-Kbit, and a 256-Kbit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA or CPLD configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. When the FPGA is in Master-SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave-Parallel or Slave-SelectMAP Mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA. After CE and OE are enabled, data is available on the PROMs DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. Neither Slave-Parallel nor SelectMAP utilize a Length Count, so a free-running oscillator can be used in the Slave-Parallel or SlaveSelecMAP modes. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable Serial PROM family. © 2001, 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. DS026 (v3.5) June 14, 2002 Product Specification www.xilinx.com 1-800-255-7778 1 R XC18V00 Series of In-System Programmable Configuration PROMs CLK CE TCK TMS TDI Control and JTAG Interface TDO OE/Reset Data Memory Address Data CEO Serial or Parallel Interface 7 D0 DATA (Serial or Parallel (Slave-Parallel/SelectMAP) Mode D[1:7] Slave-Parallel and SelectMAP Interface CF DS026_01_032702 Figure 1: XC18V00 Series Block Diagram Pinout and Pin Description Table 1: Pin Names and Descriptions Pin Name Boundary Scan Order Function Pin Description D0 4 DATA OUT 3 OUTPUT ENABLE 6 DATA OUT 5 OUTPUT ENABLE 2 DATA OUT 1 OUTPUT ENABLE 8 DATA OUT 7 OUTPUT ENABLE 24 DATA OUT 23 OUTPUT ENABLE 10 DATA OUT 9 OUTPUT ENABLE 17 DATA OUT 16 OUTPUT ENABLE 14 DATA OUT 13 OUTPUT ENABLE D1 D2 D3 D4 D5 D6 D7 2 44-pin VQFP 44-pin PLCC 20-pin SOIC and PLCC D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. 40 2 1 D0-D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in Slave-Parallel/SelectMap mode. 29 35 16 42 4 2 27 33 15 9 15 7(1) 25 31 14 14 20 9 19 25 12 www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs Table 1: Pin Names and Descriptions (Continued) Pin Name Boundary Scan Order Function Pin Description CLK 0 DATA IN OE/ RESET 20 DATA IN 19 DATA OUT 18 OUTPUT ENABLE CE 15 CF CEO 44-pin VQFP 44-pin PLCC 20-pin SOIC and PLCC Each rising edge on the CLK input increments the internal address counter if both CE is Low and OE/RESET is High. 43 5 3 When Low, this input holds the address counter reset and the DATA output is in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is NOT programmable. 13 19 8 DATA IN When CE is High, the device is put into low-power standby mode, the address counter is reset, and the DATA pins are put in a high-impedance state. The DATA output pin is in a high-impedance state, and the device is in low power standby mode. 15 21 10 22 DATA OUT 10 16 7(1) 21 OUTPUT ENABLE Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command. 12 DATA OUT 21 27 13 11 OUTPUT ENABLE Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. When OE/RESET goes Low, CEO stays High until the PROM is brought out of reset by bringing OE/RESET High. 6, 18, 28 & 41 3, 12, 24 & 34 11 GND GND is the ground connection. TMS MODE SELECT The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50K ohm resistive pull-up on it to provide a logic “1” to the device if the pin is not driven. 5 11 5 TCK CLOCK This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. 7 13 6 TDI DATA IN This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50K ohm resistive pull-up on it to provide a logic “1” to the system if the pin is not driven. 3 9 4 TDO DATA OUT This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50K ohm resistive pull-up on it to provide a logic “1” to the system if the pin is not driven. 31 37 17 DS026 (v3.5) June 14, 2002 Product Specification www.xilinx.com 1-800-255-7778 3 R XC18V00 Series of In-System Programmable Configuration PROMs Table 1: Pin Names and Descriptions (Continued) Pin Name Boundary Scan Order Pin Description 44-pin PLCC Positive 3.3V supply voltage for internal logic and input buffers. 17, 35 & 38 23, 41 & 44 18 & 20 Positive 3.3V or 2.5V supply voltage connected to the output voltage drivers. 8, 16, 26 & 36 14, 22, 32 & 42 19 No connects. 1, 2, 4, 11, 12, 20, 22, 23, 24, 30, 32, 33, 34, 37, 39, 44 1, 6, 7, 8, 10, 17, 18, 26, 28, 29, 30, 36, 38, 39, 40, 43 Function VCC VCCO NC 20-pin SOIC and PLCC 44-pin VQFP Notes: 1. By default, pin 7 is the D4 pin in the 20-pin packages. However, CF --> D4 programming option can be set to override the default and route the CF function to pin 7. Xilinx FPGAs and Compatible PROMs Table 2 provides a list of Xilinx FPGAs and compatible PROMs. Table 2: Xilinx FPGAs and Compatible PROMs Table 2: Xilinx FPGAs and Compatible PROMs 4 Device Configuration Bits XC18V00 Solution XC18V00 Solution XC2V1500 5,659,360 Device Configuration Bits XC18V04 + XC18V02 XC2VP2 1,305,440 XC18V02 XC2V2000 7,492,064 2 of XC18V04 XC2VP4 3,006,560 XC18V04 XC2V3000 10,494,432 3 of XC18V04 XC2VP7 4,485,472 XC18V04 + XC18V512 XC2V4000 15,660,000 4 of XC18V04 XC2V6000 21,849,568 5 of XC18V04 + XC18V02 XC2VP20 8,214,624 2 of XC18V04 XC2VP30 11,364,608 3 of XC18V04 XC2V8000 29,063,136 7 of XC18V04 XC2VP40 15,563,264 4 of XC18V04 XCV50 559,200 XC18V01 XC2VP50 19,021,472 5 of XC18V04 XCV100 781,216 XC18V01 XC2VP70 25,604,096 6 of XC18V04 + XC18V512 XCV150 1,040,096 XC18V01 XCV200 1,335,840 XC18V02 XC2VP100 33,645,312 8 of XC18V04 + XC18V256 XCV300 1,751,808 XC18V02 XCV400 2,546,048 XC18V04 XC2VP125 42,782,208 10 of XC18V04 + XC18V01 XCV600 3,607,968 XC18V04 XC2V40 360,160 XC18V512 XCV800 4,715,616 XC18V04 + XC18V512 XC2V80 635,360 XC18V01 XCV1000 6,127,744 XC2V250 1,697,248 XC18V02 XC18V04 + XC18V02 XC2V500 2,761,952 XC18V04 XCV50E 630,048 XC18V01 XC2V1000 4,082,656 XC18V04 XCV100E 863,840 XC18V01 XCV200E 1,442,106 XC18V02 www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs Table 2: Xilinx FPGAs and Compatible PROMs col as shown in Figure 2. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The Xilinx development system provides the programming data sequence using either Xilinx iMPACT software and a download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format and with automatic test equipment. Device Configuration Bits XC18V00 Solution XCV300E 1,875,648 XC18V02 XCV400E 2,693,440 XC18V04 XCV405E 3,430,400 XC18V04 XCV600E 3,961,632 XC18V04 XCV812E 6,519,648 2 of XC18V04 XCV1000E 6,587,520 2 of XC18V04 XCV1600E 8,308,992 2 of XC18V04 XCV2000E 10,159,648 3 of XC18V04 OE/RESET XCV2600E 12,922,336 4 of XC18V04 XCV3200E 16,283,712 4 of XC18V04 The ISP programming algorithm requires issuance of a reset that causes OE to go Low. XC2S15 197,696 XC18V256 External Programming XC2S30 336,768 XC18V512 XC2S50 559,200 XC18V01 XC2S100 781,216 XC18V01 XC2S150 1,040,096 XC18V01 Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130 or a third-party device programmer. This provides the added flexibility of using pre-programmed devices with an in-system programmable option for future enhancements and design changes. XC2S200 1,335,840 XC18V02 Reliability and Endurance XC2S50E 630,048 XC18V01 XC2S100E 863,840 XC18V01 XC2S150E 1,134,528 XC18V02 XC2S200E 1,442,016 XC18V02 Xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in-system program/erase cycles and a minimum data retention of 20 years. Each device meets all functional, performance, and data retention specifications within this endurance limit. XC2S300E 1,875,648 XC18V02 Configuration Bits XC18V04 4,194,304 XC18V02 2,097,152 XC18V01 1,048,576 XC18V512 524,288 XC18V256 262,144 The read security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. When set, it allows device erase. Erasing the entire device is the only way to reset the read security bit. Table 3: Data Security Options In-System Programming In-System Programmable PROMs can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG proto- DS026 (v3.5) June 14, 2002 Product Specification Design Security The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading via JTAG. Table 3 shows the security setting available. Capacity Devices All outputs are held in a high-impedance state or held at clamp levels during in-system programming. Default = Reset Set Read Allowed Program/Erase Allowed Verify Allowed Read Inhibited via JTAG Program/Erase Allowed Verify Inhibited www.xilinx.com 1-800-255-7778 5 R XC18V00 Series of In-System Programmable Configuration PROMs V CC GND (a) (b) DS026_02_011100 Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable IEEE 1149.1 Boundary-Scan (JTAG) The XC18V00 family is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the XC18V00 device. Table 4 lists the required and optional boundary-scan instructions supported in the XC18V00. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. Table 4: Boundary Scan Instructions Boundary-Scan Command Description Required Instructions BYPASS 11111111 Enables BYPASS SAMPLE/ PRELOAD 00000001 Enables boundary-scan SAMPLE/PRELOAD operation EXTEST 00000000 Enables boundary-scan EXTEST operation Optional Instructions CLAMP 11111010 Enables boundary-scan CLAMP operation HIGHZ 11111100 all outputs in high-impedance state simultaneously IDCODE 11111110 Enables shifting out 32-bit IDCODE USERCODE 11111101 Enables shifting out 32-bit USERCODE Instruction Register The Instruction Register (IR) for the XC18V00 is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI. The detailed composition of the instruction capture pattern is illustrated in Figure 3. Binary Code [7:0] XC18V00 Specific Instructions CONFIG 11101110 Initiates FPGA configuration by pulsing CF pin Low The ISP Status field, IR(4), contains logic “1” if the device is currently in ISP mode; otherwise, it contains logic “0”. The Security field, IR(3), contains logic “1” if the device has been programmed with the security option turned on; otherwise, it contains logic “0”. 6 www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification R TDI-> XC18V00 Series of In-System Programmable Configuration PROMs IR[7:5] IR[4] IR[3] IR[2] IR[1:0] 000 ISP Status Security 0 01 Table 5 lists the IDCODE register values for the XC18V00 devices. ->TDO Table 5: IDCODES Assigned to XC18V00 Devices ISP-PROM IDCODE 1. IR(1:0) = 01 is specified by IEEE Std. 1149.1 XC18V01 05024093h Figure 3: Instruction Register Values Loaded into IR as Part of an Instruction Scan Sequence XC18V02 05025093h XC18V04 05026093h XC18V256 05022093h XC18V512 05023093h Notes: Boundary Scan Register The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin on the XC18V00 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the High-Z enable state of the pin. For each input pin, the register stage controls and observes the input state of the pin. The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device’s programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XC18V00 device. If the device is blank or was not loaded during programming, the USERCODE register contains FFFFFFFFh. XC18V00 TAP Characteristics Identification Registers The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examination by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG. The IDCODE register has the following binary format: The XC18V00 family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the XC18V00 TAP are described as follows. TAP Timing vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where Figure 4 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations. v = the die version number f = the family code (50h for XC18V00 family) a = the ISP PROM product ID (26h for the XC18V04) c = the company code (49h for Xilinx) Note: The LSB of the IDCODE register is always read as logic “1” as defined by IEEE Std. 1149.1. DS026 (v3.5) June 14, 2002 Product Specification www.xilinx.com 1-800-255-7778 7 R XC18V00 Series of In-System Programmable Configuration PROMs TCKMIN 1,2 TCK TMSS TMSH TMS TDIS TDIH TDI TDOV TDO DS026_04_032702 Figure 4: Test Access Port Timing TAP AC Parameters Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4 Table 6: Test Access Port Timing Parameters Symbol Parameter Min Max Units TCKMIN1 TCK minimum clock period 100 - ns TCKMIN2 TCK minimum clock period, Bypass Mode 50 - ns TMSS TMS setup time 10 - ns TMSH TMS hold time 25 - ns TDIS TDI setup time 10 - ns TDIH TDI hold time 25 - ns TDOV TDO valid delay - 25 ns Connecting Configuration PROMs Connecting the FPGA device with the configuration PROM (see Figure 5 and Figure 6). • • • • The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) (in Master-Serial and Master-SelectMAP modes only). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. • • The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of all target FPGA devices, provided that DONE is not permanently grounded. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. Slave-Parallel/SelectMap mode is similar to slave serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements. Initiating FPGA Configuration The XC18V00 devices incorporate a pin named CF that is controllable through the JTAG CONFIG instruction. Executing the CONFIG instruction through JTAG pulses the CF low for 300-500 ns, which resets the FPGA and initiates configuration. The CF pin must be connected to the PROGRAM pin on the FPGA(s) to use this feature. 8 www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs The iMPACT software can also issue a JTAG CONFIG command to initiate FPGA configuration through the “Load FPGA” setting. the 20-pin packages do not have a dedicated CF pin. For 20-pin packages, the CF --> D4 setting can be used to route the CF pin function to pin 7 only if the parallel output mode is not used. Selecting Configuration Modes The XC18V00 accommodates serial and parallel methods of configuration. The configuration modes are selectable through a user control register in the XC18V00 device. This control register is accessible through JTAG, and is set using the “Parallel mode” setting on the Xilinx iMPACT software. Serial output is the default programming mode. Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. Xilinx PROMs are designed to accommodate the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is DS026 (v3.5) June 14, 2002 Product Specification provided by the rising edge of the temporary signal CCLK, which is generated by the FPGA during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line, a clock line, and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip pull-up resistor. Cascading Configuration PROMs For multiple FPGAs configured as a serial daisy-chain, or a single FPGA requiring larger configuration memories in a serial or SelectMAP configuration mode, cascaded PROMs provide additional memory (Figure 5). Multiple XC18V00 devices can be concatenated by using the CEO output to drive the CE input of the downstream device. The clock inputs and the data outputs of all XC18V00 devices in the chain are interconnected. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and drives its DATA line to a high-impedance state. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 7. After configuration is complete, address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low or CE goes High. www.xilinx.com 1-800-255-7778 9 R XC18V00 Series of In-System Programmable Configuration PROMs Vcc Vcco Vcc Vcco Vcc 4.7K Vcc MODE PINS* Vcc DOUT DIN DIN Vcc D0 Vcco TDI TMS 4 TDO Vcc First PROM Xilinx FPGA 4.7K Master Serial Slave Serial ** CLK CCLK CCLK TMS CE TMS CE DONE DONE TCK CEO TCK CEO TDI 2 3 TCK XC18V00 Cascaded PROM 1 Xilinx FPGA Vcco XC18V00 J1 D0 Vcc MODE PINS* CLK TDI OE/RESET OE/RESET CF CF TDO GND TDO GND INIT INIT PROGRAM PROGRAM TDI TDI TMS TMS TCK TCK TDO TDO Power Monitor Reset * For Mode pin connections, refer to appropriate FPGA data sheet. ** Virtex series Platform FPGAs are 300 ohms, all others are 3.3K. DS026_08_032702 Figure 5: Configuring Multiple Devices in Master/Slave Serial Mode Vcc Vcco Vcc Vcco Vcc 4.7K Vcc Vcc MODE PINS* **D[0:7] Vcc **D[0:7] Vcco J1 TDI TMS TCK TDO 1 2 3 4 **D[0:7] Vcc Xilinx Virtex-II FPGA Vcco XC18V00 XC18V00 Cascaded PROM First PROM Vcc 300 MODE PINS* **D[0:7] Xilinx Virtex-II FPGA 4.7K Master Serial/ SelectMAP Slave Serial/ SelectMAP CLK CCLK CCLK TMS CE TMS CE DONE DONE TCK CEO TCK CEO INIT INIT TDI GND CLK TDI OE/RESET OE/RESET CF CF TDO GND TDO PROGRAM PROGRAM TDI TDI TMS TMS TCK TDO TCK TDO Power Monitor Reset * For Mode pin connections, refer to appropriate FPGA data sheet. **Master/Slave Serial Mode does not require D[1:7]. DS026_08_032702 Figure 6: Configuring Multiple Virtex-II Devices with Identical Patterns in Master/Slave or Serial/SelectMAP Modes 10 www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs OPTIONAL Daisy-chained FPGAs with different configurations DOUT FPGA OPTIONAL Slave FPGAs with identical configurations Vcco Vcc VCC 4.7K Modes (1) VCC (2) ** VCC 4.7K VCC VCCO DATA First CLK PROM CEO CE DIN CCLK DONE INIT PROGRAM DATA CLK Cascaded PROM CE OE/RESET OE/RESET CF CF Power Monitor Reset (1) For Mode pin connections, refer to the appropriate FPGA data sheet. (2) Virtex, Virtex-E, Virtex-II, and Virtex-II Pro devices are 300 ohms; all others are 3.3K. Master Serial Mode I/O(1) I/O (1) Modes WRITE 1K VIRTEX Select MAP NC External Osc (4) CS VCC VCCO VCC VCCO VCC VCCO VCC VCCO 1K 3.3V VCC BUSY VCC 4.7K (2) XC18Vxx 4.7K CLK CCLK 8 PROGRAM D[0:7] CEO D[0:7] CE DONE OE/RESET INIT XC18Vxx CLK D[0:7] CE CF OE/RESET CEO CF Power Monitor Reset (1) CS and WRITE must be pulled down to be used as I/O. One option is shown. (2) Virtex, Virtex-E, Virtex-II, and Virtex-II Pro are 300 ohms, all others are 3.3K. (3) For Mode pin connections, refer to the appropriate FPGA data sheet. (4) External oscillator required for Virtex/Virtex-E SelectMAP or Virtex-II/Virtex-II Pro Slave-SelectMAP modes. Virtex/Virtex-E/Virtex-II/Virtex-II Pro SelectMAP Mode I/O(1) I/O (1) Modes WRITE Spartan-II, Spartan-IIE NC External Osc (4) CS BUSY 1K VCCO VCC VCCO 1K 3.3V VCC VCC 3.3K (2) CCLK PROGRAM D[0:7] VCC XC18Vxx 4.7K CLK 8 DONE INIT D[0:7] CE OE/RESET CF Power Monitor Reset (1) CS and WRITE must be pulled down to be used as I/O. One option is shown. (2) If Drive Done configuration option is not active for any of the FPGAs, pull up DONE with a 3.3-kΩ resistor. (3) For Mode pin connections, refer to the appropriate FPGA data sheet. (4) External oscillator required for Spartan-II/Spartan-IIE Slave-Parallel modes. Spartan-II/Spartan-IIE Slave-Parallel Mode DS026_05_032702 Figure 7: (a) Master Serial Mode (b) Virtex/Virtex-E/Virtex-II Pro SelectMAP Mode (c) Spartan-II/Spartan-IIE Slave-Parallel Mode (dotted lines indicate optional connection) DS026 (v3.5) June 14, 2002 Product Specification www.xilinx.com 1-800-255-7778 11 R XC18V00 Series of In-System Programmable Configuration PROMs 5V Tolerant I/Os 3.6V Recommended Operating Range 3.0V Recommended Volts The I/Os on each re-programmable PROM are fully 5V tolerant even through the core power supply is 3.3V. This allows 5V CMOS signals to connect directly to the PROM inputs without damage. In addition, the 3.3V VCC power supply can be applied before or after 5V signals are applied to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins, the core power supply (VCC), and the output power supply (VCCO) can have power applied in any order. This makes the PROM devices immune to power supply sequencing issues. VCC Rise Time 0V 0ms 1ms 50ms Time (ms) Reset Activation On power up, OE/RESET is held low until the XC18V00 is active (1 ms). OE/RESET is connected to an external resistor to pull OE/RESET HIGH releasing the FPGA INIT and allowing configuration to begin. To ensure data deliver does not begin until after VCC and VCCO reach their recommended operating ranges, an external power monitor with an open-drain reset output is a recommended connection to the XC18V00 OE/RESET pin (or FPGA PROGRAM pin). See Figure 8 and Figure 9. If the power drops below 2.0V, the PROM resets. OE/RESET polarity is not programmable. ds026_10_032702 Figure 8: VCC Power-Up Requirements Power Monitor Open-Drain XC18V00 VCC VCC XC18V00 OE/RESET RESET (or FPGA PROGRAM) ds026_11_032702 Figure 9: Power Monitor for Valid Power-Up Activation Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The address is reset. The output remains in a high-impedance state regardless of the state of the OE input. JTAG pins TMS, TDI and TDO can be in a high-impedance state or High. Customer Control Bits The XC18V00 PROMs have various control bits accessible by the customer. These can be set after the array has been programmed using “Skip User Array” in Xilinx iMPACT software. See Table 7. Table 7: Truth Table for PROM Control Inputs Control Inputs Outputs OE/RESET CE Internal Address DATA CEO ICC High Low If address < TC(1): increment If address > TC(1): don’t change Active High-Z High Low Active Reduced Low Low Held reset High-Z High Active High High Held reset High-Z High Standby Low High Held reset High-Z High Standby Notes: 1. TC = Terminal Count = highest address value. TC + 1 = address 0. 12 www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs Absolute Maximum Ratings(1,2) Symbol Description Value Units VCC Supply voltage relative to GND –0.5 to +4.0 V VIN Input voltage with respect to GND –0.5 to +5.5 V VTS Voltage applied to High-Z output –0.5 to +5.5 V TSTG Storage temperature (ambient) –65 to +150 pC TSOL Maximum soldering temperature (10s @ 1/16 in.) +260 pC Junction temperature +150 pC TJ Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can undershoot to –2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Recommended Operating Conditions Symbol Parameter VCCINT Internal voltage supply (TA = 0pC to +70pC) Internal voltage supply (TA = –40pC to +85pC) VCCO Min Max Units Commercial 3.0 3.6 V Industrial 3.0 3.6 V Supply voltage for output drivers for 3.3V operation 3.0 3.6 V Supply voltage for output drivers for 2.5V operation 2.3 2.7 V VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 2.0 5.5 V VO Output voltage 0 VCCO V VCC rise time from 0V to nominal voltage(1) 1 50 ms TVCC Notes: 1. At power up, the device requires the VCC power supply to monotonically rise from 0V to nominal voltage within the specified VCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. Quality and Reliability Characteristics Symbol Description Min Max Units 20 - Years TDR Data retention NPE Program/erase cycles (Endurance) 20,000 - Cycles VESD Electrostatic discharge (ESD) 2,000 - Volts DS026 (v3.5) June 14, 2002 Product Specification www.xilinx.com 1-800-255-7778 13 R XC18V00 Series of In-System Programmable Configuration PROMs DC Characteristics Over Operating Conditions Symbol VOH Test Conditions Min Max Units 2.4 - V 90% VCCO - V High-level output voltage for 3.3V outputs IOH = –4 mA High-level output voltage for 2.5V outputs IOH = –500 NA Low-level output voltage for 3.3V outputs IOL = 8 mA - 0.4 V Low-level output voltage for 2.5V outputs IOL = 500 NA - 0.4 V ICC Supply current, active mode 25 MHz - 25 mA ICCS Supply current, standby mode - 10 mA IILJ JTAG pins TMS, TDI, and TDO VCC = MAX VIN = GND –100 - NA IIL Input leakage current VCC = Max VIN = GND or VCC –10 10 NA IIH Input and output High-Z leakage current VCC = Max VIN = GND or VCC –10 10 NA Input and output capacitance VIN = GND f = 1.0 MHz - 10 pF VOL CIN and COUT 14 Parameter www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions for XC18V04 and XC18V02 CE TSCE THCE OE/RESET THC TLC THOE TCYC CLK TOE TCE TCAC TDF TOH DATA TOH DS026_06_012000 Symbol Description Min Max Units TOE OE/RESET to data delay - 10 ns TCE CE to data delay - 20 ns TCAC CLK to data delay - 20 ns TOH Data hold from CE, OE/RESET, or CLK 0 - ns TDF CE or OE/RESET to data float delay(2) - 25 ns Clock periods 50 - ns TLC CLK Low time(3) 10 - ns THC CLK High time(3) 10 - ns TSCE CE setup time to CLK (to guarantee proper counting)(3) 25 - ns THCE CE High time (to guarantee proper counting) 2 - Ns THOE OE/RESET hold time (guarantees counters are reset) 25 - ns TCYC Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 Ns, TCE = 2 Ns. 6. If THCE Low < 2 Ns, TOE = 2 Ns. DS026 (v3.5) June 14, 2002 Product Specification www.xilinx.com 1-800-255-7778 15 R XC18V00 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions for XC18V01, XC18V512, and XC18V256 CE TSCE THCE OE/RESET THC TLC THOE TCYC CLK TOE TCE TCAC TDF TOH DATA TOH DS026_06_012000 Symbol Description Min Max Units TOE OE/RESET to data delay - 10 ns TCE CE to data delay - 15 ns TCAC CLK to data delay - 15 ns TOH Data hold from CE, OE/RESET, or CLK 0 - ns - 25 ns 30 - ns 10 - ns 10 - ns 20 - ns TDF TCYC CE or OE/RESET to data float delay(2) Clock periods time(3) TLC CLK Low THC CLK High time(3) counting)(3) TSCE CE setup time to CLK (to guarantee proper THCE CE hold time to CLK (to guarantee proper counting) 2 - Ns THOE OE/RESET hold time (guarantees counters are reset) 20 - ns Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 Ns, TCE = 2 Ns. 16 www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions When Cascading for XC18V04 and XC18V02 OE/RESET CE CLK TCDF TOCE Last Bit DATA First Bit TOCK TOOE CEO DS026_07_020300 Symbol TCDF Description CLK to data float delay(2,3) delay(3) TOCK CLK to CEO TOCE CE to CEO delay(3) TOOE OE/RESET to CEO delay(3) Min Max Units - 25 ns - 20 ns - 20 ns - 20 ns Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. DS026 (v3.5) June 14, 2002 Product Specification www.xilinx.com 1-800-255-7778 17 R XC18V00 Series of In-System Programmable Configuration PROMs AC Characteristics Over Operating Conditions When Cascading for XC18V01, XC18V512, and XC18V256 OE/RESET CE CLK TCDF TOCE Last Bit DATA First Bit TOCK TOOE CEO DS026_07_020300 Symbol Description Min Max Units TCDF CLK to data float delay(2,3) - 25 ns TOCK CLK to CEO delay(3) - 20 ns TOCE CE to CEO delay(3) - 20 ns TOOE OE/RESET to CEO delay(3) - 20 ns Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 18 www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification R XC18V00 Series of In-System Programmable Configuration PROMs Ordering Information XC18V04 VQ44 C Device Number Operating Range/Processing XC18V04 XC18V02 XC18V01 XC18V512 XC18V256 Package Type VQ44 = 44-pin Plastic Quad Flat Package PC44 = 44-pin Plastic Chip Carrier(1) SO20 = 20-pin Small-Outline Package(2) PC20 = 20-pin Plastic Leaded Chip Carrier(2) C = Commercial (TA = 0p to +70pC) I = Industrial (TA = –40p to +85pC) Notes: 1. XC18V04 and XC18V02 only. 2. XC18V01, XC18V512, and XC18V256 only. Valid Ordering Combinations XC18V04VQ44C XC18V02VQ44C XC18V01VQ44C XC18V512VQ44C XC18V256VQ44C XC18V04PC44C XC18V02PC44C XC18V01PC20C XC18V512PC20C XC18V256PC20C XC18V01SO20C XC18V512SO20C XC18V256SO20C XC18V04VQ44I XC18V02VQ44I XC18V01VQ44I XC18V512VQ44I XC18V256VQ44I XC18V04PC44I XC18V02PC44I XC18V01PC20I XC18V512PC20I XC18V256PC20I XC18V01SO20I XC18V512SO20I XC18V256SO20I Marking Information 44-pin Package XC18V04 VQ44 I Device Number Operating Range/Processing XC18V04 XC18V02 XC18V01 XC18V512 XC18V256 Package Type VQ44 = 44-pin Plastic Quad Flat Package PC44 = 44-pin Plastic Leaded Chip Carrier(1) (blank) = Commercial (TA = 0p to +70pC) I = Industrial (TA = –40p to +85pC) Notes: 1. XC18V02 and XC18V04 Only. 20-pin Package(1) Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows: 18V01 S C Device Number Operating Range/Processing 18V01 18V512 18V256 Package Type S = 20-pin Small-Outline Package J = 20-pin Plastic Leaded Chip Carrier C = Commercial (TA = 0p to +70pC) I = Industrial (TA = –40p to +85pC) Notes: 1. XC18V01, XC18V512, and XC18V256 only. DS026 (v3.5) June 14, 2002 Product Specification www.xilinx.com 1-800-255-7778 19 R XC18V00 Series of In-System Programmable Configuration PROMs Revision History The following table shows the revision history for this document. 20 Date Version Revision 2/9/99 1.0 First publication of this early access specification 8/23/99 1.1 Edited text, changed marking, added CF and parallel load 9/1/99 1.2 Corrected JTAG order, Security and Endurance data. 9/16/99 1.3 Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF description, 256 Kbit and 128 Kbit devices. 01/20/00 2.0 Added Q44 Package, changed XC18xx to XC18Vxx 02/18/00 2.1 Updated JTAG configuration, AC and DC characteristics 04/04/00 2.2 Removed stand alone resistor on INIT pin in Figure 5. Added Virtex-E and EM parts to FPGA table. 06/29/00 2.3 Removed XC18V128 and updated format. Added AC characteristics for XC18V01, XC18V512, and XC18V256 densities. 11/13/00 2.4 Features: changed 264 MHz to 264 Mb/s at 33 MHz; AC Spec.: TSCE units to ns, THCE CE High time units to Ns. Removed Standby Mode statement: “The lower power standby modes available on some XC18V00 devices are set by the user in the programming software”. Changed 10,000 cycles endurance to 20,000 cycles. 01/15/01 2.5 Updated Figures 5 and 6, added 4.7 resistors. Identification registers: changes ISP PROM product ID from 06h to 26h. 04/04/01 2.6 Updated Figure 6, Virtex SelectMAP mode; added XC2V products to Compatible PROM table; changed Endurance from 10,000 cycles, 10 years to 20,000, 20 years; 04/30/01 2.7 Updated Figure 6: removed Virtex-E in Note 2, fixed SelectMAP mode connections. Under AC Characteristics Over Operating Conditions for XC18V04 and XC18V02, changed TSCE from 25 ms to 25 ns. 06/11/01 2.8 AC Characteristics Over Operating Conditions for XC18V01, XC18V512, and XC18V256 Changed Min values for TSCE from 20 ms to 20 ns and for THCE from 2 ms to 2 Ns. 09/28/01 2.9 Changed the boundary scan order for the CEO pin in Table 1, updated the configuration bits values in the table under Xilinx FPGAs and Compatible PROMs, and added information to the Recommended Operating Conditions table. 11/12/01 3.0 Updated for Spartan-IIE FPGA family. 12/06/01 3.1 Changed Figure 7(c). 02/27/02 3.2 Updated Table 2 and Figure 6 for the Virtex-II Pro family of devices. 03/15/02 3.3 Updated Xilinx software, added power monitor recommendation Figure 7, and added new Figure 6. 03/27/02 3.4 Made changes to pages 1-3, 5, 7-11, 13, 14, and 18. Added new Figure 8 and Figure 9. 06/14/02 3.5 Made additions and changes to Table 2. www.xilinx.com 1-800-255-7778 DS026 (v3.5) June 14, 2002 Product Specification