0 R DS092 (v1.0) January 3, 2002 XC2C64 CoolRunner-II CPLD 0 0 Advance Product Specification Features - • - • • • Optimized for 1.8V systems - Industry’s fastest low power CPLD - Static Icc of less than 100 microamps at all times - Densities from 32 to 512 macrocells Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V Available in multiple package options - 44-pin PLCC with 33 user I/O - 44-pin VQFP with 33 user I/O - 56-ball CP (0.05mm) BGA with 45 user I/O - 100-pin VQFP with 64 user I/O Advanced system features - Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt trigger input (per pin) - Unsurpassed low power management - FZP 100% CMOS product term generation - Flexible clocking modes · Optional DualEDGE triggered registers - Global signal options with macrocell control · Multiple global clocks with phase selection per macrocell · Multiple global output enables · Global set/reset - Abundant product term clocks, output enables and set/resets - Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - Advanced design security - Open-drain output option for Wired-OR and LED drive - Optional bus-hold or weak pullup on selected I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts - PLA architecture · Superior pinout retention · 100% product term routability across function block - Hot pluggable - Design entry/verification using Xilinx and industry standard CAE tools - Free software support for all densities using Xilinx WebPACK™ or WebFITTER™ tools Industry leading nonvolatile 0.18 micron CMOS process Guaranteed 1,000 program/erase cycles Guaranteed 20 year data retention Refer to the CoolRunner™-II family data sheet for architecture description. Description The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output control signals include slew rate control, bus hold and open drain. A Schmitt trigger input is available on a per input pin basis. In addition to combinatorial and registered outputs, the registers may be configured as fast inputs. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. These clocks are additionally used to set or preset individual macrocell registers on power up. Local clocks are generated in specific Function Blocks and only available to macrocell registers in that Function Block. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows performance where it is needed without raising the total power consumption of the entire device. The CoolRunner-II 64-macrocell CPLD is I/O compatible with standard LVTTL33 and LVCMOS18, 25, and 33 volts (see Table 1). This device is also 1.5 volt I/O compatible with the use of Schmitt inputs. © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS092 (v1.0) January 3, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 1 R XC2C64 CoolRunner-II CPLD Fast Zero Power Design Technology EIA/JESDSA standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt inputs. Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ Fast Zero Power™ (FZP), a design technique that makes use of CMOS technology in both the fabrication and design methodology. FZP design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high performance and low power operation. Table 1: I/O Standards for XC2C64 Output VCCIO Input VCCIO Input VREF Board Termination Voltage VT 3.3V 3.3V N/A N/A LVCMOS33 3.3 3.3 N/A N/A Supported I/O Standards LVCMOS25 2.5 2.5 N/A N/A The CoolRunner-II 64 macrocell features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose LVCMOS18 1.8 1.8 N/A N/A I/O Standard LVTTL 25 ICC (mA) 20 15 10 5 0 0 50 100 150 200 250 300 Frequency (MHz) DS092_07_121501 Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1) Frequency (MHz) Typical ICC (mA) 50 75 100 125 150 175 200 225 250 275 300 3.6 5.5 7.3 9.1 10.8 12.5 14.2 15.9 17.5 19.2 20.8 Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block). 2 www.xilinx.com 1-800-255-7778 DS092 (v1.0) January 3, 2002 Advance Product Specification R XC2C64 CoolRunner-II CPLD Absolute Maximum Ratings Symbol Description Value Units VCC Supply voltage relative to ground –0.5 to 2.0 V VCCIO Supply voltage for output drivers –0.5 to 4.0 V VIN Input voltage relative to ground(1) –0.5 to 4.0 V VTS Voltage applied to 3-state output(1) –0.5 to 4.0 V –65 to +150 °C VSTG Storage Temperature (ambient) TSOL Maximum Soldering temperature (10s @ 1/16in. = 1.5mm) + 60 °C Junction Temperature + 50 °C TJ Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Recommended Operating Conditions Symbol VCC VCCIO Parameter Min Max Units Commercial TA = 0°C to +70°C 1.7 1.9 V Industrial TA = –40°C to +85°C 1.7 1.9 V Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V 1.4 1.6 V Supply voltage for internal logic and input buffers Supply voltage for output drivers @ 1.5V operation(1) Notes: 1. Use input hysteresis for 1.5V LVCMOS. DC Electrical Characteristics (Over Recommended Operating Conditions) Symbol Parameter Test Conditions Min. Max. Units 100 µA ICCSB Standby current VCC = 1.9V, VCCIO = 3.6V ICC Dynamic current f = 1 MHz mA f = 50 MHz mA CJTAG JTAG input capacitance f = 1 MHz pF CCLK Global clock input capacitance f = 1 MHz pF CIO I/O capacitance f = 1 MHz pF DS092 (v1.0) January 3, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 3 R XC2C64 CoolRunner-II CPLD LVCMOS 3.3V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units 3.0 3.6 V VCCIO Input source voltage VIH High level input voltage 2 VCCIO + 0.3V V VIL Low level input voltage –0.3 0.8 V VOH High level output voltage IOH = –8 mA, VCCIO = 3V VCCIO – 0.4V - V IOH = –0.1 mA, VCCIO = 3V VCCIO – 0.2V - V IOL = 8 mA, VCCIO = 3V - 0.4 V IOL = 0.1 mA, VCCIO = 3V - 0.2 V VOL Low level output voltage IIL Input leakage current VIN = 0V or VCCIO to 3.9V –10 10 µA IIH I/O High-Z leakage VIN = 0V or VCCIO to 3.9V –10 10 µA CJTAG JTAG input capacitance f = 1 MHz pF CCLK Global clock input capacitance f = 1 MHz pF CIO I/O capacitance f = 1 MHz pF LVCMOS 2.5V DC Voltage Specifications Symbol Test Conditions Min. Max. Units VCCIO Input source voltage 2.3 2.7 V VIH High level input voltage 1.7 3.9 V VIL Low level input voltage –0.3 0.7 V VOH High level output voltage IOH = –8 mA, VCCIO = 3V VCCIO – 0.4V - V IOH = –0.1 mA, VCCIO = 3V VCCIO – 0.2V - V IOL = 8 mA, VCCIO = 3V - 0.4 V IOL = 0.1mA, VCCIO = 3V - 0.2 V VOL 4 Parameter Low level output voltage IIL Input leakage current VIN = 0V or VCCIO to 3.9V –10 10 µA IIH I/O High-Z leakage VIN = 0V or VCCIO to 3.9V –10 10 µA CJTAG JTAG input capacitance f = 1 MHz pF CCLK Global clock input capacitance f = 1 MHz pF CIO I/O capacitance f = 1 MHz pF www.xilinx.com 1-800-255-7778 DS092 (v1.0) January 3, 2002 Advance Product Specification R XC2C64 CoolRunner-II CPLD LVCMOS 1.8V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units 1.7 1.9 V VCCIO Input source voltage VIH High level input voltage 0.7 x VCCIO 3.9 V VIL Low level input voltage –0.3 0.2 x VCCIO V VOH High level output voltage IOH = –8 mA, VCCIO = 3V VCCIO -0.45 - V IOH = –0.1 mA, VCCIO = 3V VCCIO -0.2 - V IOL = 8 mA, VCCIO = 3V - 0.45 V IOL = 0.1 mA, VCCIO = 3V - 0.2 V VOL Low level output voltage IIL Input leakage current VIN = 0 or VCCIO to 3.9V –10 10 µA IIH I/O High-Z leakage VIN = 0 or VCCIO to 3.9V –10 10 µA CJTAG JTAG input capacitance f = 1 MHz pF CCLK Global clock input capacitance f = 1 MHz pF CIO I/O capacitance f = 1 MHz pF 1.5V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units 1.4 1.6 V VCCIO Input source voltage VIH High level input voltage 0.7 x VCCIO 3.9 V VIL Low level input voltage –0.3 0.3 V VOH High level output voltage VOL Low level output voltage IOH = –8 mA, VCCIO = 3V VCCIO – 0.45 V IOH = –0.1 mA, VCCIO = 3V VCCIO – 0.2 V IOL = 8 mA, VCCIO = 3V 0.4 V IOL = 0.1 mA, VCCIO = 3V 0.2 V IIL Input leakage current VIN = 0 or VCCIO to 3.9V –10 10 µA IIH I/O High-Z leakage VIN = 0 or VCCIO to 3.9V –10 10 µA CJTAG JTAG input capacitance f = 1 MHz pF CCLK Global clock input capacitance f = 1 MHz pF CIO I/O capacitance f = 1 MHz pF DS092 (v1.0) January 3, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 5 R XC2C64 CoolRunner-II CPLD AC Electrical Characteristics Over Recommended Operating Conditions -4 Symbol 6 Parameter -5 -7 Min. Max. Min. Max. Min. Max. Units TPD1 Propagation delay single p-term - 3.7 - 4.6 - 6.7 ns TPD2 Propagation delay OR array - 4.0 - 5.0 - 7.5 ns TSU1 Setup time fast 1.6 - 1.9 - 2.3 - ns TSU2 Setup time 2.0 - 2.4 - 3.3 - ns TH1 Fast input register hold time 0 - 0 - 0 - ns TH2 P-term hold time 0 - 0 - 0 - ns TCO Clock to output - 3.0 - 3.9 - 6.0 ns TTOGGLE Internal toggle rate - 416 - 250 - 168 MHz FSYSTEM Maximum system frequency - 270 - 213 - 141 MHz FEXT Maximum external frequency - 200 - 159 - 108 MHz TPSU1 Fast input register p-term clock setup time 1.0 - 1.2 - 1.5 - ns TPSU2 P-term clock setup time 1.4 - 1.7 - 2.5 - ns TPH1 Fast input register p-term clock hold time 0.4 - 0.6 - 0.7 - ns TPH2 P-term clock hold 0.3 - 0.5 - 0.5 - ns TPCO P-term clock to output - 3.6 - 4.6 - 6.8 ns TOE/TOD Global OE to output enable/disable - 3.9 - 4.9 - 7.0 ns TPOE/TPOD P-term OE to output enable/disable - 4.3 - 5.3 - 7.3 ns TMOE/TMOD Macrocell driven OE to output enable/disable - 4.9 - 6.3 - 9.2 ns TPAO P-term set/reset to output valid - 5.4 - 6.4 - 9.1 ns TAO Global set/reset to output valid - 5.5 - 6.5 - 9.3 ns TSUEC1 Fast input register clock enable setup time 1.6 - 1.9 - 2.3 - ns TSUEC2 Register clock enable setup time 2.0 - 2.4 - 3.3 - ns THEC1 Fast input register clock enable hold time 0 - 0 - 0 - ns THEC2 Register clock enable hold time 0 - 0 - 0 - ns TCW Global clock pulse width High or Low 1.2 - 2.0 - 3.0 - ns TPCW P-term pulse width High or Low 4.0 - 5.0 - 7.5 - ns TCONFIG Configuration time us www.xilinx.com 1-800-255-7778 DS092 (v1.0) January 3, 2002 Advance Product Specification R XC2C64 CoolRunner-II CPLD Internal Timing Parameters -4 Parameter(1) Symbol -5 -7 Min. Max. Min. Max. Min. Max. Units Buffer Delays TIN Input buffer delay - 1.3 - 1.7 - 2.4 ns TFIN Fast data register input delay - 1.6 - 2.1 - 3.0 ns TGCK Global Clock buffer delay - 1.2 - 1.6 - 2.5 ns TGSR Global set/reset buffer delay - 1.9 - 2.4 - 3.5 ns TGTS Global 3-state buffer delay - 1.4 - 1.9 - 3.0 ns TOUT Output buffer delay - 1.6 - 1.9 - 2.8 ns TEN Output buffer enable/disable delay - 2.5 - 3.0 - 4.0 ns TCT Control term delay - 0.5 - 0.6 - 0.9 ns TLOGI1 Single P-term delay adder - 0.4 - 0.5 - 0.8 ns TLOGI2 Multiple P-term delay adder - 0.3 - 0.4 - 0.8 ns P-term Delays Macrocell Delay TPDI Input to output valid - 0.4 - 0.5 - 0.7 ns TSUI Setup before clock 1.2 - 1.4 - 1.8 - ns THI Hold after clock 0 - 0 - 0 - ns TECSU Enable clock setup time 1.2 - 1.4 - 1.8 - ns TECHO Enable clock hold time 0 - 0 - 0 - ns TCOI Clock to output valid - 0.2 - 0.4 - 0.7 ns TAOI Set/reset to output valid - 2.0 - 2.2 - 3.0 ns TCDBL Clock doubler delay - 0 - 0 - 0 ns Feedback Delays TF Feedback delay - 1.6 - 2.0 - 3.0 ns TOEM Macrocell to global OE delay - 1.0 - 1.3 - 2.0 ns I/O Standard Time Adder Delays 1.5V CMOS TIN15 Standard input adder ns THYS15 Hysteresis input adder ns TOUT15 Output adder ns TSLEW15 Output slew rate adder ns I/O Standard Time Adder Delays 1.8V CMOS TIN18 Standard input adder - 0 - 0 - 0 ns THYS18 Hysteresis input adder - 2.0 - 3.0 - 4.0 ns TOUT18 Output adder - 0 - 0 - 0 ns TSLEW Output slew rate adder - 2.0 - 3.0 - 4.0 ns DS092 (v1.0) January 3, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 7 R XC2C64 CoolRunner-II CPLD Internal Timing Parameters (Continued) -4 Parameter(1) Symbol -5 -7 Min. Max. Min. Max. Min. Max. Units I/O Standard Time Adder Delays 2.5V CMOS TIN25 Standard input adder - 0.5 - 0.8 - 1.0 ns THYS25 Hysteresis input adder - 1.5 - 2.5 - 3.0 ns TOUT25 Output adder - 1.5 - 2.5 - 3.0 ns TSLEW25 Output slew rate adder - 2.0 - 3.0 - 4.0 ns I/O Standard Time Adder Delays 3.3V CMOS/TTL TIN33 Standard input adder - 0.7 - 1.0 - 2.0 ns THYS33 Hysteresis input adder - 1.0 - 2.0 - 3.0 ns TOUT33 Output adder - 1.0 - 2.0 - 3.0 ns TSLEW33 Output slew rate adder - 2.0 - 3.0 - 4.0 ns Notes: 1. 1.5 ns input pin signal rise/fall. Switching Characteristics VCC = 1.8V, 25oC 6.0 TPD_PAL (ns) 5.8 5.6 4.4 4.2 4.0 1 2 4 8 12 16 Number of Outputs Switching DS092_09_121501 8 www.xilinx.com 1-800-255-7778 DS092 (v1.0) January 3, 2002 Advance Product Specification R XC2C64 CoolRunner-II CPLD Pin Descriptions (Continued) Pin Descriptions VQ100 Function Block Macrocell PC44 VQ44 CP56 VQ100 F1 13 3 1 35 29 C4 91 37 E3 12 3 2 34 28 A4 90 42 36 E1 11 3 3 33 27 C5 89 4 - - - 10 3 4 - - A7 81 1 5 - - - 9 3 5 - - C8 79 1 6 - - - 8 3 6 29 23 A8 78 1 7 - - D3 7 3 7 - - A9 77 1 8 - - - 6 3 8 - - - 76 1(GTS1) 9 40 34 D1 4 3 9 - - A5 74 1(GTS0) 10 39 33 C1 3 3 10 28 22 A10 72 1(GTS3) 11 38 32 A3 2 3 11 27 21 B10 71 1(GTS2) 12 37 31 A2 1 3 12 26 20 C10 70 1(GRS) 13 36 30 B1 99 3 13 - - D8 68 1 14 - - A1 97 3 14 25 19 E8 67 1 15 - - C3 94 3 15 24 18 D10 64 1 16 - - A4 92 3 16 - - - 61 2 1 1 39 G1 14 4 1 11 5 K6 35 2 2 2 40 F3 15 4 2 12 6 H5 36 2 3 - - - 16 4 3 - - - 37 2 4 - - - 17 4 4 - - - 39 2 5 3 41 H1 18 4 5 - - H7 40 2 6 4 42 G3 19 4 6 - - - 41 2(GCK0) 7 5 43 J1 22 4 7 14 8 H8 42 2(GCK1) 8 6 44 K1 23 4 8 - - - 43 2 9 - - K4 24 4 9 - - - 49 2(GCK2) 10 7 1 K2 27 4 10 - - K8 50 2 11 - - - 28 4 11 18 12 H10 52 2 12 8 2 K3 29 4 12 - - - 53 2 13 9 3 H3 30 4 13 19 13 G10 55 2 14 - - K5 32 4 14 20 14 - 56 2 15 - - - 33 4 15 22 16 F10 58 2 16 - - - 34 4 16 - - E10 60 Function Block Macrocell PC44 VQ44 CP56 1 1 44 38 1 2 43 1 3 1 Note: GTS = global output enable, GRS = global reset/set, GCK = global clock x DS092 (v1.0) January 3, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 9 R XC2C64 CoolRunner-II CPLD XC2C64 Global, JTAG, Power/Ground and No Connect Pins Pin Type PC44 VQ44 CP56 VQ100 TCK 17 11 K10 48 TDI 15 9 J10 45 TDO 30 24 A6 83 TMS 16 10 K9 47 VAUX (JTAG supply voltage) 41 35 D3 5 Power internal (VCC) 21 15 G8 26,57 13, 32 7,26 H6, C6 38, 51,88, 98 10,23,31 4,17,25 H4, F8, C7 21,31,62,69,84,100 Power external I/O (VCCIO) Ground No connects 20,25,44,46,54,59,63,65,66,73,75, 80,82,85,86,87,93,95,96 Total user I/O 33 33 45 64 Ordering Information Commercial (C) Pin/Ball Spacing θJA (C/Watt) θJC (C/Watt) Package Type I/O Industrial (I) XC2C64-4PC44C 1.27mm 53.1 28.7 Plastic Leaded Chip Carrier 33 C XC2C64-5PC44C 1.27mm 53.1 28.7 Plastic Leaded Chip Carrier 33 C XC2C64-7PC44C 1.27mm 53.1 28.7 Plastic Leaded Chip Carrier 33 C XC2C64-4VQ44C 0.8mm 46.6 8.2 Very Thin Quad Flat Pack 33 C XC2C64-5VQ44C 0.8mm 46.6 8.2 Very Thin Quad Flat Pack 33 C XC2C64-7VQ44C 0.8mm 46.6 8.2 Very Thin Quad Flat Pack 33 C XC2C64-4CP56C 0.5mm 65.0 15.0 Chip Scale Package 45 C XC2C64-5CP56C 0.5mm 65.0 15.0 Chip Scale Package 45 C XC2C64-7CP56C 0.5mm 65.0 15.0 Chip Scale Package 45 C XC2C64-4VQ100C 0.5mm 53.2 14.6 Very Thin Quad Flat Pack 64 C XC2C64-5VQ100C 0.5mm 53.2 14.6 Very Thin Quad Flat Pack 64 C XC2C64-7VQ100C 0.8mm 53.2 14.6 Very Thin Quad Flat Pack 64 C XC2C64-5PC44I 1.27mm 53.1 28.7 Plastic Leaded Chip Carrier 33 I XC2C64-7PC44I 1.27mm 53.1 28.7 Plastic Leaded Chip Carrier 33 I XC2C64-5VQ44I 0.8mm 46.6 8.2 Very Thin Quad Flat Pack 33 I XC2C64-7VQ44I 0.8mm 46.6 8.2 Very Thin Quad Flat Pack 33 I XC2C64-5CP56I 0.5mm 65.0 15.0 Chip Scale Package 45 I XC2C64-7CP56I 0.5mm 65.0 15.0 Chip Scale Package 45 I XC2C64-5VQ100I 0.5mm 53.2 14.6 Very Thin Quad Flat Pack 64 I XC2C64-7VQ100I 0.5mm 53.2 14.6 Very Thin Quad Flat Pack 64 I Part Number 10 www.xilinx.com 1-800-255-7778 DS092 (v1.0) January 3, 2002 Advance Product Specification R PQ44 Top View 44 43 42 41 40 39 38 37 36 35 34 I/O VCCIO Gnd TDO I/O I/O I/O I/O I/O I/O GND I/O(2) I/O I/O GND I/O I/O VCCIO I/O TDI TMS TCK 1 2 3 4 5 6 7 8 9 10 11 VQ44 Top View 33 32 31 30 29 28 27 26 25 24 23 I/O(1) I/O(1) I/O(1) I/O(3) I/O I/O I/O VCCIO GND TDO I/O 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O VCCIO I/O TDI TMS TCK I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O(2) I/O(2) I/O(2) I/O I/O GND I/O I/O(2) I/O(2) I/O I/O I/O I/O I/O I/O I/O VAUX I/O(1) I/O I/O I/O VAUX I/O(1) I/O(1) I/O(1) I/O(1) I/O(3) I/O I/O XC2C64 CoolRunner-II CPLD (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset Figure 2: PQ44 Package 3 4 5 6 7 8 I/O(2) I/O(2) I/O I/O I/O I/O I/O I/O J I/O(2) H I/O I/O G I/O I/O F I/O I/O E I/O D TMS 10 2 K 9 1 Figure 3: VQ44 Package TCK TDI GND I/O VCCIO I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O(1) VAUX I/O I/O C I/O(1) I/O I/O I/O B I/O(3) A I/O CP56 Bottom View I/O I/O VCCIO GND I/O I/O(1) I/O I/O I/O TDO I/O I/O I/O I/O (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset Figure 4: CP56 Package DS092 (v1.0) January 3, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 11 R 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND I/O(3) VCCIO I/O NC NC I/O NC I/O I/O I/O I/O VCCIO NC NC NC GND TDO NC I/O NC I/O I/O I/O I/O XC2C64 CoolRunner-II CPLD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VQ100 Top View 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC I/O NC I/O I/O I/O GND I/O I/O NC NC I/O NC GND I/O I/O NC I/O Vcc I/O I/O NC I/O I/O VCCIO VCC I/O(2) I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O NC TDI NC TMS TCK I/O I/O 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O(1) I/O(1) I/O(1) I/O(1) VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND I/O(2) I/O(2) I/O NC (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset Figure 5: VQ100 Package Revision History The following table shows the revision history for this document. 12 Date Version 01/03/02 0.1 Revision Initial Xilinx release. www.xilinx.com 1-800-255-7778 DS092 (v1.0) January 3, 2002 Advance Product Specification