SEMTECH XE8802MI035LF

XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
XE8802 Sensing Machine
Data Acquisition SoC with 16+10 bit ZoomingADC™
Embedded RISC controller and LCD driver
General Description
The XE8802 includes a high resolution acquisition
path with the 16+10 bits ZoomingADC™ and an
LCD driver for up to 120 segments. The LCD lines
can be used as additional I/Os.
Key product Features
•
•
•
The embedded core of the XE8802 is an ultra
low-power low-voltage microcontroller unit (MCU)
with a strict 1 instruction per clock processing and
branch speed, allowing for a sustained 4MIPS at
1200µA under 2.4 to 5.5 V.
The XE8802 is available with on chip ROM or
Multiple-Time-Programmable (MTP) program
memory.
Applications
•
•
•
•
•
•
Portable, battery operated instruments
Medical portable instrument
Remote control
HVAC control
Metering
Sports watches, wrist instruments
Rev 1 January 2006
•
•
•
•
•
•
•
Low-power, high resolution ZoomingADC
•
16-bits sigma-delta type ADC
•
0.5 to 1000 gain with offset cancellation
•
up to 13 inputs multiplexer, 8 dedicated inputs
4 low power comparators
Low-voltage low-power controller operation
•
•
•
•
2 or 4 MIPS max, 2.4 to 5.5 V operation
300µA per 1MIPS over full voltage range
7MIPS or 1.2V operation in ROM
Hardware MULT
up to 22kByte (8 kInstruction) MTP
1032Byte RAM data memory
RC and crystal oscillators
5 reset, 22 interrupt, 8 event sources
36 I/O lines, hardware UART and SPI
120 segments LCD driver,
can be used as 32 extra I/O lines
100 years MTP Flash retention at 55°C
Ordering Information
Product
Temperature range
Memory type
Package
XE8802MI000
-40°C to 85 °C
MTP
die
XE8802MI035LF
-40°C to 85 °C
MTP
LQFP100
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XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
TABLE OF CONTENTS
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Chapter 15
Chapter 16
Chapter 17
Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
Chapter 23
© Semtech 2006
XE8802 Overview
XE8802 Performance
XE8802 CPU
XE8802 Memory
Low power modes
Reset generator
Clock generation
Interrupt handler
Event handler
Low power RAM
Port A
Port B
Port D
Universal Asynchronous Receiver/Transmitter (UART)
Universal Synchronous Receiver/Transmitter (USRT)
Serial Peripheral Interface (SPI)
Acquisition chain
Voltage multiplier
LCD driver
Counters/PWM
The Voltage Level Detector
Low Power Comparators
XE8802 Dimensions
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XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
1. General overview
1.1
Top schematic
1-2
1.2
1.2.1
1.2.2
Pin map
LQFP-100
LQFP-80
1-4
1-4
1-6
1.3
Bare die
1-8
1.4
Pin assignment
1-9
© Semtech 2006
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1-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
1.1 Top schematic
The top-level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the
Coolrisc816 CPU core. This core includes an 8x8 multiplier and 16 internal registers.
The bus controller generates all control signals for access to all data registers other than the CPU internal
registers.
The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained
in its control registers. Possible reset sources are the power-on-reset (POR), the external pin NRESET, the
watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. Different low
power modes are implemented.
The clock generation and power management block sets up the clock signals and generates internal supplies for
different blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal
oscillator (XTAL) or an external clock source (given on the XIN pin).
The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8
low power data registers. If power consumption is important for the application, the variables that need to be
accessed frequently should be stored in these registers rather than in the RAM.
The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows
masking of the interrupt sources and it flags which interrupt source is active.
Events are generally used to restart the processor after a HALT period without jumping to a specified address, i.e.
the program execution resumes with the instruction following the HALT instruction. The EVN handler routes the
event signals of the different peripherals to the EVN inputs of the CPU core. It allows masking of the interrupt
sources and it flags which interrupt source is active.
The Port B is an 8-bit parallel IO port with analog capabilities. The URST, UART, PWM and CMPD block also
make use of this port.
The instruction memory is a 22-bit wide flash or ROM memory depending on the circuit version. In case of the
ROM version, the VPP and NFASTREAD pins are not used. ROM versions have 8k instruction memory. Flash
versions have 8k or 4k instruction memories depending on the selected operation speed.
The data memory on this product is a 1024 byte SRAM.
The Acquisition Chain is a high-resolution acquisition path with the 16+10 bits ZoomingADC™. The VMULT
(voltage multiplier) powers a part of the Acquisition Chain.
The SPI is a serial interface with a master or slave configuration capability. When unused, the 4 SPI pads can be
used as 4-bit wide general-purpose I/O port.
The port A is an 8 bit parallel input port. It can also generate interrupts, events or a reset. It can be used to input
external clocks for the timer/counter/PWM block.
The Port D1 and the Port D2 are two general-purpose 8 bit parallel I/O ports.
The LCD driver can support a direct drive display (up to 32 segments), or multiplex 1/2, 1/3, 1/4 displays (up to 120
segments). The driver contains an on chip low-power voltage generation device VGEN. The LCD lines can be used
as additional I/O pins.
The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to
simplify the software implementation of a synchronous serial link.
© Semtech 2006
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1-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
NFASTREAD
DATA
MEMORY
INSTRUCTION MEMORY
VPP
CPU
COOLRISC816
VBAT
VSS
8 X 8 MULTIPLIER
B
U
S
C
O
N
T
R
O
L
L
E
R
address
control
PORT A
PA(7:0)
datain
dataout
PORT D1
PD1(7:0)
16 CPU REGISTERS
NRESET
RESET BLOCK
WD
XIN
XOUT
VREG
TEST
reset
control
PORT D2
POR
PD2(7:0)
CLOCK
GENERATION/
POWER
MANAGEMENT
RC
XTAL
VREG
clocks
LCD_IO(31:0)
LCD Driver
VGEN
test
control
LCD_COM(1:0)
TEST CONTROLLER
VGEN_Vx(4:0)
8 DATA REGISTERS
PORT B
COUNTERS
TIMERS
PWM
ACQUISITION CHAIN
VMULT
(ZoomingADC)
VLD
PB(7:0)
VMULT
AC_R(3:0)
AC_A(7:0)
CMPD
PB(7:6)
UART
PB(1:0) PA(3:0)
evn
PB(7:4)
EVN HANDLING
USRT
PB(5:4)
irq
IRQ HANDLING
SPI
SPI(3:0)
Figure 1-1. Block schematic of the XE8802 circuit.
The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of the
asynchronous serial link.
© Semtech 2006
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1-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
The counters/timers/PWM can take their clocks from internal or external sources (on Port A) and can generate
interrupts or events. The PWM is output on Port B.
The VLD (voltage level detector) detects the battery end of life with respect to a programmable threshold.
The CMPD contains a 4-channel comparator. It is intended to monitor analog or digital signals with very low power
consumption.
1.2 Pin map
The 02 can be delivered in different packages. The pin maps for the different packages are given below.
PA(2)
PD1(2)
PA(3)
PD1(3)
PA(4)
PD1(4)
30
PA(5)
PD1(5)
PA(6)
PD1(6)
PA(7)
PD1(7)
PB(0)
40
LCD_VR2
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
SPI(0)
SPI(1)
SPI(2)
SPI(3)
50
VPP
1.2.1 LQFP-100
VMULT
LCD_IO(0)
VREG
LCD_IO(1)
VBAT
LCD_IO(2)
XOUT
VSS
LCD_IO(3)
20
LCD_VR1
XIN
LCD_IO(4)
AC_R(2)
LCD_IO(5)
AC_R(3)
AC_R(0)
LCD_IO(6)
LCD_IO(7)
AC_R(1)
60
LCD_IO(8)
AC_A(7)
LCD_IO(9)
AC_A(6)
LCD_IO(10)
AC_A(5)
LCD_IO(11)
AC_A(4)
AC_A(3)
LCD_IO(12)
LCD_IO(13)
10
AC_A(2)
LCD_IO(14)
AC_A(1)
LCD_IO(15)
AC_A(0)
TEST
LCD_IO(16)
LCD_IO(17)
NRESET
70
LCD_IO(18)
PD2(7)
LCD_IO(19)
PD2(6)
LCD_IO(20)
PD2(5)
PD2(4)
LCD_IO(21)
PD2(1)
PA(1)
PD2(0)
PD1(1)
PA(0)
PD1(0)
NFASTREAD
VSS
VGEN_V3
VGEN_VB
PD2(3)
PD2(2)
1
90
VGEN_V2
VGEN_V1
VGEN_VA
LCD_COM(0)
LCD_COM(1)
LCD_IO(31)
LCD_IO(30)
LCD_IO(29)
LCD_IO(28)
LCD_IO(27)
LCD_IO(26)
LCD_IO(25)
LCD_IO(24)
LCD_IO(23)
80
LCD_IO(22)
Figure 1-2. LQFP-100 pin map
Package pin
1
2
name
PD2(3)
PD2(4)
Package pin
51
52
name
LCD_VR2
LCD_IO(0)
© Semtech 2006
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1-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PD2(5)
PD2(6)
PD2(7)
NRESET
TEST
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
AC_R(1)
AC_R(0)
AC_R(3)
AC_R(2)
XIN
VSS
XOUT
VBAT
VREG
VMULT
PA(2)
PD1(2)
PA(3)
PD1(3)
PA(4)
PD1(4)
PA(5)
PD1(5)
PA(6)
PD1(6)
PA(7)
PD1(7)
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
SPI(0)
SPI(1)
SPI(2)
SPI(3)
VPP
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
LCD_IO(1)
LCD_IO(2)
LCD_IO(3)
LCD_VR1
LCD_IO(4)
LCD_IO(5)
LCD_IO(6)
LCD_IO(7)
LCD_IO(8)
LCD_IO(9)
LCD_IO(10)
LCD_IO(11)
LCD_IO(12)
LCD_IO(13)
LCD_IO(14)
LCD_IO(15)
LCD_IO(16)
LCD_IO(17)
LCD_IO(18)
LCD_IO(19)
LCD_IO(20)
LCD_IO(21)
LCD_IO(22)
LCD_IO(23)
LCD_IO(24)
LCD_IO(25)
LCD_IO(26)
LCD_IO(27)
LCD_IO(28)
LCD_IO(29)
LCD_IO(30)
LCD_IO(31)
LCD_COM(1)
LCD_COM(0)
VGEN_VA
VGEN_V1
VGEN_V2
VGEN_V3
VGEN_VB
VSS
NFASTREAD
PD1(0)
PA(0)
PD1(1)
PA(1)
PD2(0)
PD2(1)
PD2(2)
Table 1-1. Bonding plan of the LQFP-100 package (LQFP 100L 14x14mm thick 1.6 mm)
© Semtech 2006
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1-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
1.2.2 LQFP-80
Package pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
name
NRESET
TEST
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
AC_R(1)
AC_R(0)
AC_R(3)
AC_R(2)
XIN
VSS
XOUT
VBAT
VREG
VMULT
PA(2)/ PD1(2)
PA(3)/ PD1(3)
PA(4)/ PD1(4)
PA(5)/ PD1(5)
PA(6)/ PD1(6)
PA(7)
PD1(7)
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
SPI(0)
SPI(1)
SPI(2)
SPI(3)
VPP
Package pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
name
LCD_VR1
LCD_IO(4)
LCD_IO(5)
LCD_IO(6)
LCD_IO(7)
LCD_IO(8)
LCD_IO(9)
LCD_IO(10)
LCD_IO(11)
LCD_IO(12)
LCD_IO(13)
LCD_IO(14)
LCD_IO(15)
LCD_IO(16)
LCD_IO(17)
LCD_IO(18)
LCD_IO(19)
LCD_IO(20)
LCD_IO(21)
LCD_IO(22)
LCD_IO(23)
LCD_IO(24)
LCD_IO(25)
LCD_IO(26)
LCD_IO(27)
LCD_IO(28)
LCD_IO(29)
LCD_IO(30)
LCD_IO(31)
LCD_COM(1)
LCD_COM(0)
VGEN_VA
VGEN_V1
VGEN_V2
VGEN_V3
VGEN_VB
VSS
NFASTREAD
PA(0)/PD1(0)
PA(1)/ PD1(1)
Table 1-2. Bonding plan of the LQFP-80 package (LQFP 80L 14x14mm thick 1.6 mm)
© Semtech 2006
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1-6
PD1(2)/PA(2)
PD1(3)/PA(3)
PD1(4)/PA(4)
PD1(5)/PA(5)
PD1(6)/PA(6)
PA(7)
PD1(7)
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
SPI(0)
SPI(1)
SPI(2)
SPI(3)
30
LCD_VR1
40
VPP
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
20
VMULT
LCD_IO(4)
VREG
LCD_IO(5)
VBAT
LCD_IO(6)
XOUT
LCD_IO(7)
VSS
LCD_IO(8)
XIN
LCD_IO(9)
AC_R(2)
LCD_IO(10)
AC_R(3)
LCD_IO(11)
AC_R(0)
LCD_IO(12)
AC_R(1)
50
LCD_IO(13)
10
AC_A(7)
LCD_IO(14)
AC_A(6)
LCD_IO(15)
AC_A(5)
LCD_IO(16)
AC_A(4)
LCD_IO(17)
AC_A(3)
LCD_IO(18)
AC_A(2)
LCD_IO(19)
AC_A(1)
LCD_IO(20)
AC_A(0)
TEST
LCD_IO(21)
PD1(1)/PA(1)
PD1(0)/PA(0)
NFASTREAD
VSS
VGEN_VB
VGEN_V3
VGEN_V2
VGEN_V1
VGEN_VA
LCD_COM(0)
LCD_IO(31)
LCD_COM(1)
LCD_IO(30)
LCD_IO(29)
LCD_IO(28)
LCD_IO(27)
LCD_IO(26)
LCD_IO(25)
LCD_IO(24)
NRESET
80
1
70
60
LCD_IO(23)
LCD_IO(22)
Figure 1-3. LQFP- 80 pin map
© Semtech 2006
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1-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
(2600, 5315)
(2716, 5315)
(2882, 5315)
(3050, 5315)
(3217, 5315)
(3385, 5315)
(3553, 5315)
(3720, 5315)
(3888, 5315)
(4055, 5315)
(4223, 5315)
LCD_COM(1)
VSS
LCD_IO(31)
LCD_IO(30)
LCD_IO(29)
LCD_IO(28)
LCD_IO(27)
LCD_IO(26)
LCD_IO(25)
LCD_IO(24)
LCD_IO(23)
LCD_COM(0) (2432, 5315)
PD2(2)
PD2(1)
PD2(0)
VSS
PA(1)
PD1(1)
PA(0)
PD1(0)
VBAT
NFASTREAD
VSS
VGEN_VB
VGEN_V3
VGEN_V2
VGEN_V1
VGEN_VA
( 450, 5315)
( 565, 5315)
( 680, 5315)
( 795, 5315)
( 910, 5315)
(1025, 5315)
(1140, 5315)
(1255, 5315)
(1370, 5315)
(1485, 5315)
(1600, 5315)
(1761, 5315)
(1876, 5315)
(1991, 5315)
(2106, 5315)
(2221, 5315)
1.3 Bare die
VGEN_V3
(4634, 4911)
LCD_IO(22) (4634, 4795)
PD2(3)
PD2(4)
PD2(5)
PD2(6)
PD2(7)
VSS
NRESET
TEST
LCD_IO(21) (4634, 4628)
LCD_IO(20) (4634, 4460)
LCD_IO(19) (4634, 4292)
LCD_IO(18) (4634, 4124)
LCD_IO(17) (4634, 3957)
LCD_IO(16) (4634, 3789)
XEMICS
(48, 4673)
(48, 4558)
(48, 4443)
(48, 4328)
(48, 4213)
(48, 4098)
(48, 3983)
(48, 3868)
LCD_IO(15) (4634, 3622)
LCD_IO(14) (4634, 3454)
VSS
(4634, 3288)
LCD_IO(13) (4634, 3171)
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
VBAT
AC_R(1)
AC_R(0)
AC_R(3)
AC_R(2)
XIN
VSS
XOUT
VBAT
VREG
VMULT
LCD_IO(12) (4634, 3004)
LCD_IO(11) (4634, 2826)
LCD_IO(10) (4634, 2659)
LCD_IO(9)
(4634, 2376)
LCD_IO(8)
(4634, 2209)
LCD_IO(7)
(4634, 2041)
LCD_IO(6)
(4634, 1873)
LCD_IO(5)
(4634, 1706)
VBAT
5530µm
PA(2)
PD1(2)
PA(3)
PD1(3)
PA(4)
PD1(4)
VSS
PA(5)
PD1(5)
PA(6)
PD1(6)
PA(7)
PD1(7)
VBAT
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
VSS
PB(7)
SPI(0)
SPI(1)
SPI(2)
SPI(3)
VPP
(4231, 48)
4580µm
( 450, 48)
( 588, 48)
( 726, 48)
( 864, 48)
(1002, 48)
(1140, 48)
(1278,48)
(1416, 48)
(1554, 48)
(1692, 48)
(1830, 48)
(1968, 48)
(2106, 48)
(2249, 48)
(2382, 48)
(2520, 48)
(2658, 48)
(2796, 48)
(2934, 48)
(3049, 48)
(3164, 48)
(3279, 48)
(3394, 48)
(3512, 48)
(3627, 48)
(3742, 48)
(3857, 48)
(48, 3016)
(48, 2874)
(48, 2732)
(48, 2590)
(48, 2448)
(48, 2306)
(48, 2164)
(48, 2022)
(48, 1880)
(48, 1738)
(48, 1596)
(48, 1454)
(48, 1312)
(48, 1170)
(48, 1026)
(48, 882)
(48, 738)
(48, 594)
(48, 450)
LCD_IO(4)
(4634, 1538)
LCD_VR1
LCD_IO(3)
(4634, 1372)
(4634, 1249)
LCD_IO(2)
(4634, 966)
LCD_IO(1)
(4634, 799)
LCD_IO(0)
(4634, 631)
LCD_VR2
(4634, 465)
Figure 1-4. Bare die dimensions and pin locations.
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1-8
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
1.4 Pin assignment
The table below gives a short description of the different pin assignments.
Pin
Assignment
VBAT
VSS
VREG
VPP
NFASTREAD
NRESET
TEST
XIN/XOUT
PA(7:0)
PB(7:0)
PD1(7:0)
PD2(7:0)
SPI(3:0)
LCD_IO(29:0)
LCD_IO(31:30)
LCD_COM(1:0)
LCD_VR1/LCD_VR2
VGEN_Vx
AC_A(7:0)
AC_R(3:0)
VMULT
Positive power supply
Negative power supply
Connection for the mandatory external capacitor of the voltage regulator
High voltage supply for flash memory programming (NC in ROM versions)
Selects the maximal operation speed and the flash memory size (NC in ROM versions)
Resets the circuit when the voltage is low
Sets the pin to flash programming mode
Quartz crystal connections, also used for flash memory programming
Parallel input port A pins
Parallel I/O port B pins
Parallel I/O port D1 pins
Parallel I/O port D2 pins
Serial SPI port or general purpose I/O port pins
LCD segment driver or general purpose I/O port pins
LCD segment driver or LCD back plane driver or general purpose I/O port pins
LCD back plane driver pins
LCD supply voltage
LCD driver voltage generation pins
Acquisition chain input pins
Acquisition chain reference pins
Connection for external capacitor of the voltage multiplier
Table 1-3. Pin assignment
Table 1-4 gives a more detailed pin map for the different pins in the different packages. It also indicates the
possible I/O configuration of these pins. The indications in blue bold are the configuration at start-up. Please note
that in the LQFP-80 package several functions are routed to the same package pins. These pins are indicated in
red italic.
PD2(3)
PD2(4)
PD2(5)
PD2(6)
PD2(7)
NRESET
TEST
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
AC_R(1)
POWER
LCD
SNAP
PD
X
X
X
X
X
PU
X
X
X
X
X
X
X
OD
AO
AI
third
first
second
I/O configuration
DO
1
2
3
4
5
6
7
8
9
10
11
Function
DI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
lqfp-80
lqfp-100
Pin
number
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
© Semtech 2006
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1-9
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
12
13
14
15
16
17
18
19
20
21
21
22
22
23
23
24
24
25
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
AC_R(0)
AC_R(3)
AC_R(2)
XIN
VSS
XOUT
VBAT
VREG
VMULT
PA(2)
PD1(2)
PA(3)
PD1(3)
PA(4)
PD1(4)
PA(5)
PD1(5)
PA(6)
PD1(6)
PA(7)
PD1(7)
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
SPI(0)
SPI(1)
SPI(2)
SPI(3)
VPP
LCD_VR2
LCD_IO(0)
LCD_IO(1)
LCD_IO(2)
LCD_IO(3)
LCD_VR1
LCD_IO(4)
LCD_IO(5)
LCD_IO(6)
LCD_IO(7)
LCD_IO(8)
LCD_IO(9)
LCD_IO(10)
LCD_IO(11)
LCD_IO(12)
LCD_IO(13)
LCD_IO(14)
X
X
X
X
X
X
X
X
X
X
X
CNTC
CNTD
PWM0
PWM1
USRT_S0
USRT_S1
UART_Tx
UART_Rx
CMPD(0)
CMPD(1)
CMPD(2)
CMPD(3)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
© Semtech 2006
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1-10
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
79
80
80
LCD_IO(15)
LCD_IO(16)
LCD_IO(17)
LCD_IO(18)
LCD_IO(19)
LCD_IO(20)
LCD_IO(21)
LCD_IO(22)
LCD_IO(23)
LCD_IO(24)
LCD_IO(25)
LCD_IO(26)
LCD_IO(27)
LCD_IO(28)
LCD_IO(29)
LCD_IO(30)
LCD_IO(31)
LCD_COM(1)
LCD_COM(0)
VGEN_VA
VGEN_V1
VGEN_V2
VGEN_V3
VGEN_VB
VSS
NFASTREAD
PD1(0)
PA(0)
PD1(1)
PA(1)
PD2(0)
PD2(1)
PD2(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CNTA
CNTB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Pin map table legend:
blue bold: configuration at start up
AI: analog input
AO: analog output
DI: digital input
DO: digital output
OD: nMOS open drain output
PU: pull-up resistor
PD: pull-down resistor
SNAP: snap-to-rail function (see peripheral description for detailed description)
POWER: power supply
Table 1-4. Pin description table
© Semtech 2006
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1-11
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
2 XE8802 Performance
2.1
Absolute maximum ratings
2-2
2.2
Operating range
2-2
2.3
Current consumption
2-3
2.4
2.4.1
2.4.2
2.4.3
Operating speed
Flash circuit version
ROM circuit version with regulator on
ROM circuit version with regulator off
2-5
2-5
2-6
2-7
2.5
Simplified supply selection criteria
2-8
© Semtech 2006
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2-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
2.1
Absolute maximum ratings
Table 2-1. Absolute maximal ratings
Voltage applied to VBAT with respect to VSS
Voltage applied to VPP with respect to VSS
Voltage applied to all pins except VPP and VBAT
Storage temperature (ROM device or unprogrammed
flash device)
Storage temperature (programmed flash device)
Min.
Max.
Note
-0.3
VBAT-0.3
VSS-0.3
-55
6.0
12
VBAT+0.3
150
V
V
V
°C
-40
85
°C
Stresses beyond the absolute maximal ratings may cause permanent damage to the device. Functional operation
at the absolute maximal ratings is not implied. Exposure to conditions beyond the absolute maximal ratings may
affect the reliability of the device.
2.2
Operating range
Table 2-2. Operating range for the flash device
Voltage applied to VBAT with respect to VSS
Voltage applied to VBAT with respect to VSS during
the flash programming
Voltage applied to VPP with respect to VSS
Voltage applied to all pins except VPP and VBAT
Operating temperature range
Capacitor on VREG (flash version)
Capacitor on VMULT
1.
2.
3.
Min.
Max.
Note
2.4
4.5
5.5
5.5
V
V
1
VBAT
VSS
-40
0.8
1.0
11.5
VBAT
85
1.2
3.0
V
V
°C
µF
nF
2
3
During the programming of the device the temperature must be between 10°C and 40°C.
The capacitor on VREG is mandatory.
The capacitor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The
multiplier has to be enabled if VBAT<3.0V.
Table 2-3. Operating range for the ROM device
Min.
Voltage applied to VBAT
with respect to VSS
Acquisition
chain off
Acquisition
chain on
VREG bypassed
VREG on
VMULT on
VMULT off
Voltage applied to all pins except VPP and VBAT
Operating temperature range
Capacitor on VREG
Capacitor on VMULT
1.
2.
3.
Max.
Note
1.2
5.5
V
1.5
2.4
3.0
5.5
5.5
5.5
V
V
V
VSS
-40
0.1
1.0
VBAT
125
1.2
3.0
V
°C
µF
nF
2
1
3
The capacitor may be omitted when VREG is connected to VBAT.
The voltage reference for the LCD drivers starts operating at 1.5 V.
The capacitor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The
multiplier has to be enabled if VBAT<3.0V.
© Semtech 2006
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2-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
All specifications in this document are valid for the complete operating range unless otherwise specified.
Table 2-4. Operating range of the Flash memory
Min.
Retention time at 85°C
Retention time at 55°C
Number of programming cycles
1.
2.
2.3
10
100
10
Max.
Note
years
years
1
1
2
Valid only if programmed using a programming tool that is qualified
Circuits can be programmed more than 10 times but in that case, the retention time is no longer
guaranteed.
Current consumption
The tables below give the current consumption for the circuit in different configurations. The figures are indicative
only and may change as a function of the actual software implemented in the circuit.
Table 2-5 gives the current consumption for the flash version of the circuit. The peripherals are disabled. The
parallel ports are configured in input with pull up. Their pins are not connected externally.
Table 2-5. Typical current consumption of the XE8802M version (8k instructions flash memory)
Operation mode
CPU
RC
Xtal
Consumption
High speed CPU
1 MIPS
1 MHz
Off
Low speed CPU
.1 MIPS
100 kHz
Off
Low power CPU
32 kIPS
Off
32 kHz
HALT
Off
32 kHz
200 µA
320 µA
410 µA
310 µA
21 µA
33 µA
42 µA
7.5 µA
11.0 µA
14.5 µA
1.9 µA
2.4V <>5.5V, 27°C
HALT
Ready
32kHz
2.3 µA
2.4V <>5.5V, 27°C
HALT
1 MHz
Off
35 µA
2.4V <>5.5V, 27°C
15 µA
2 µA
2.4V <>5.5V, 27°C
2.4V <>5.5V, 27°C
Low power time
keeping
Fast
wake-up
time keeping
Immediate wakeup time keeping
VLD static current
CMPD
static
current
1.
2.
3.
4.
comments
Note
2.4V<>5.5V, 27°C
1
2
3
4
1
2
3
1
2
3
2.4V <>5.5V, 27°C
2.4V <>5.5V, 27°C
Software without data access
100% low power RAM access
100% RAM access
typical software
© Semtech 2006
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2-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Table 2-6. Current consumption of the XE8802R version (8k instructions ROM memory)
Operation mode
CPU
RC
Xtal
Consumption
High speed CPU
Max. Speed CPU
Low speed CPU
Low power CPU
Low voltage CPU
Low power time
keeping
1 MIPS
4 MIPS
.1 MIPS
32 kIPS
32 kIPS
HALT
1 MHz
4 MHz
100 kHz
Off
Off
Off
Off
Off
Off
32 kHz
32 kHz
32 kHz
200
800
21
7
1
1.3
comments
Note
2.4V<>5.5V, 27°C
2.4V<>5.5V, 27°C
2.4V <>5.5V, 27°C
2.4V <>5.5V, 27°C
1.2V, 27°C
2.4V <>5.5V, 27°C
1
1
1
1
1
1. Software using MOVE instruction using internal CPU registers and peripheral registers
Hints for low power operation:
1. Use the low power RAM instead of the RAM for all parameters that are accessed frequently. The average
current consumption for the low power RAM is about 40 times lower than for the RAM.
2. Rather than using the circuit at low speed, it is better to use the circuit at higher speed and switch off the blocks
when not needed.
3. The power consumption of the program memory is an important part of the overall power consumption. In case
you intend to use a ROM version and power consumption is too high, please ask us to provide you with a
circuit version with smaller ROM size.
© Semtech 2006
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2-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
2.4
Operating speed
2.4.1
Flash circuit version
The speed of the flash devices is not highly dependent upon the supply voltage. However, by limiting the
temperature range, the speed can be increased. The minimal guaranteed speed as a function of the supply voltage
and maximal temperature operating temperature is given in Figure2-2.
VBAT
2.4 - 5.5 V
VREG
1uF
VSS
Figure 2-1. Supply configuration for flash circuit operation.
NFASTREAD=1 85°C
NFASTREAD=0 85°C
NFASTREAD=1 45°C
NFASTREAD=0 45°C
7
speed (MIPS)
6
5
4
3
2
1
0
2
3
4
supply voltage VBAT (V)
5
Figure 2-2. Guaranteed speed as a function of the supply voltage and maximal temperature.
The maximal speed of the device depends on the setting of the NFASTREAD pin. If NFASTREAD=1, the full 8k
instructions of the memory are available and the speed is limited to 2-3MIPS. If NFASTREAD=0, only 4k
instructions are available but the speed is doubled.
Important Note
The circuit has to be programmed for the correct option of the NFASTREAD pin. If not, the execution of the
software may not be correct.
© Semtech 2006
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2-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
2.4.2
ROM circuit version with regulator on
For the ROM version, two possible operating modes exist: with and without voltage regulator. Using the voltage
regulator, low power consumption will be obtained even with supply voltages above 2.4V. Without the voltage
regulator (i.e. VREG short-circuited to VBAT), a higher speed can be obtained.
VBAT
2.4 - 5.5 V
VREG
100nF
VSS
Figure 2-3. Supply configuration for ROM circuit operation using the internal regulator.
85°C
45°C
125°C
speed (MIPS)
8
6
4
2
0
2
2.5
3
3.5
4
4.5
5
5.5
supply voltage VBAT (V)
Figure 2-4. Guaranteed speed as a function of supply voltage and for different maximal temperatures using the
voltage regulator.
© Semtech 2006
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2-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
2.4.3
ROM circuit version with regulator off
VBAT
VREG
1.2 – 3.3 V
VSS
Figure 2-5. Supply configuration for ROM circuit operation by-passing the internal regulator.
85°C
45°C
1.5
2
125°C
speed (MIPS)
8
6
4
2
0
1
2.5
3
3.5
supply voltage VBAT (V)
Figure 2-6. Guaranteed speed as a function of supply voltage and for two temperature ranges when VREG=VBAT.
Important Note
Note that the acquisition chain will not operate if VBAT is below 2.4V. The internal reference voltage for the LCD
will not operate below 1.5V. If the internal reference is not used, the LCD voltage generator and the LCD driver will
operate down to 1.2V. The operation range of the different blocks is summarized in Figure 2-7.
© Semtech 2006
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2-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
2.5
•
•
•
•
•
•
•
Simplified supply selection criteria
MTP devices always require the capacitor on VREG and VREG cannot be shorted to VBAT on MTP devices.
ROM devices can operate 1.5 V to 5.5 V with lowest current requirement with the capacitor on VREG, and
VREG not shorted to VBAT.
ROM devices can operate 1.2 V to 3.3 V at highest speed with VREG shorted to VBAT.
If operation is always above 3.0 V, the capacitor on VMULT is not needed and VMULT can be always off.
If the acquisition chain is used between 2.4 V and 3.0 V, then the capacitor on VMULT must be present and
VMULT must be set on during operation below 3.0 V.
The acquisition chain does not operate below 2.4 V.
The internal reference voltage for the LCD does not operate below 1.5 V.
acquisition chain
VMULT off
acquisition chain
VMULT on
MTP
Vgen internal reference
ROM (VBAT≠VREG)
CPU
parallel and serial ports
LCD driver and Vgen (no int. ref.)
RC and crystal oscillator
VLD
Comparators
Counters and PWM
ROM (VBAT=VREG)
0
1.2 1.5
2.4
3.0
5.5
VBAT (V)
Figure 2-7. Operating voltage range of the different circuit blocks. MTP devices do not operate below 2.4V. ROM
devices can operate in different voltage ranges if VREG and VBAT are short circuited or not.
© Semtech 2006
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2-8
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
3. CPU
3.1
3.2
3.3
CPU description
CPU internal registers
CPU instruction short reference
3-2
3-2
3-4
© Semtech 2006
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3-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
3.1
CPU description
The CPU of the XE8000 series is a low power RISC core. It has 16 internal registers for efficient implementation of
the C compiler. Its instruction set is made up of 35 generic instructions, all coded on 22 bits, with 8 addressing
modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. The
circuit therefore runs on 1 MIPS on a 1MHz clock.
The CPU hardware and software description is given in the document “Coolrisc816 Hardware and Software
Reference Manual”. A short summary is given in the following paragraphs.
The
good
code
efficiency
of
the
CPU
core
makes
it
possible
to
compute
a
polynomial
like
Z = ( A0 + A1 ⋅ Y ) ⋅ X + B0 + B1 ⋅ Y in less than 300 clock cycles (software code generated by the XEMICS Ccompiler, all numbers are signed integers on 16 bits).
3.2
CPU internal registers
As shown in Figure 3-1, the CPU has 16 internal 8-bit registers. Some of these registers can be concatenated to a
16-bit word for use in some instructions. The function of these registers is defined in Table 3-1. The status register
stat (Table 3-2) is used to manage the different interrupt and event levels. An interrupt or an event can both be
used to wake up after a HALT instruction. The difference is that an interrupt jumps to a special interrupt function
whereas an event continues the software execution with the instruction following the HALT instruction.
The program counter (PC) is a 16 bit register that indicates the address of the instruction that has to be executed.
The stack (STn) is used to memorise the return address when executing subroutines or interrupt routines.
ST4
ST3
ST1
ST2
r0
r1
Data memory
r2
data bus
22bit
CPU
CPU internal registers
Instruction
memory
instruction bus
PC
program counter stack
r3
i0h
i0l
i1h
i1l
i2h
i2l
i3h
i3l
iph
ipl
stat
a
Figure 3-1. CPU internal registers
© Semtech 2006
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3-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Register name
r0
r1
r2
r3
i0h
i0l
i1h
i1l
i2h
i2l
i3h
i3l
iph
ipl
stat
a
Register function
general purpose
general purpose
general purpose
data memory offset
MSB of the data memory index i0
LBS of the data memory index i0
MSB of the data memory index i1
LBS of the data memory index i1
MSB of the data memory index i2
LBS of the data memory index i2
MSB of the data memory index i3
LBS of the data memory index i3
MSB of the program memory index ip
LBS of the program memory index ip
status register
accumulator
Table 3-1. CPU internal register definition
bit
7
6
5
4
name
IE2
IE1
GIE
IN2
3
IN1
2
IN0
1
EV1
0
EV0
function
enables (when 1) the interrupt request of level 2
enables (when 1) the interrupt request of level 1
enables (when 1) all interrupt request levels
interrupt request of level 2. The interrupts labelled “low” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
interrupt request of level 1. The interrupts labelled “mid” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
interrupt request of level 0. The interrupts labelled “hig” in the interrupt handler are
routed to this interrupt level. This bit has to be cleared when the interrupt is served.
event request of level 1. The events labelled “low” in the event handler are routed to
this event level. This bit has to be cleared when the event is served.
event request of level 1. The events labelled “hig” in the event handler are routed to
this event level. This bit has to be cleared when the event is served.
Table 3-2. Status register description
The CPU also has a number of flags that can be used for conditional jumps. These flags are defined in Table 3-3.
symbol
Z
C
V
name
zero
carry
overflow
function
Z=1 when the accumulator a content is zero
This flag is used in shift or arithmetic operations.
For a shift operation, it has the value of the bit that was shifted out (LSB for shift
right, MSB for shift left).
For an arithmetic operation with unsigned numbers:
it is 1 at occurrence of an overflow during an addition (or equivalent).
it is 0 at occurrence of an underflow during a subtraction (or equivalent).
This flag is used in shift or arithmetic operations.
For arithmetic or shift operations with signed numbers, it is 1 if an overflow or
underflow occurs.
Table 3-3. Flag description
© Semtech 2006
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3-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
3.3
CPU instruction short reference
Table 3-4 shows a short description of the different instructions available on the Coolrisc816. The notation cc in the
conditional jump instruction refers to the condition description as given in Table 3-6. The notation reg, reg1, reg2,
reg3 refers to one of the CPU internal registers of Table 3-1. The notation eaddr and DM(eaddr) refer to one of the
extended address modes as defined in Table 3-5. The notation DM(xxx) refers to the data memory location with
address xxx.
Instruction
Modification
Operation
Jump addr[15:0]
Jump ip
Jcc addr[15:0]
Jcc ip
Call addr[15:0]
Call ip
Calls addr[15:0]
Calls ip
-,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -
PC := addr[15:0]
PC := ip
if cc is true then PC := addr[15:0]
if cc is true then PC := ip
STn+1 := STn (n>1); ST1 := PC+1; PC := addr[15:0]
STn+1 := STn (n>1); ST1 := PC+1; PC := ip
ip := PC+1; PC := addr[15:0]
ip := PC+1; PC := ip
Ret
Rets
Reti
Push
Pop
-,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -
PC := ST1; STn := STn+1 (n>1)
PC := ip
PC := ST1; STn := STn+1 (n>1); GIE :=1
PC := PC+1; STn+1 := STn (n>1); ST1 := ip
PC := PC+1; ip := ST1; STn := STn+1 (n>1)
Move reg,#data[7:0]
Move reg1, reg2
Move reg, eaddr
Move eaddr, reg
Move addr[7:0],#data[7:0]
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-,-, -,-,-, -
a := data[7:0]; reg := data[7:0]
a := reg2; reg1 := reg2
a := DM(eaddr); reg := DM(eaddr)
DM(eaddr) := reg
DM(addr[7:0]) := data[7:0]
Cmvd reg1, reg2
Cmvd reg, eaddr
Cmvs reg1, reg2
Cmvs reg, eaddr
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
a := reg2; if C=0 then reg1 := a;
a := DM(eaddr); if C=0 then reg := a
a := reg2; if C=1 then reg1 := a;
a := DM(eaddr); if C=1 then reg := a
Shl reg1, reg2
Shl reg
Shl reg, eaddr
Shlc reg1, reg2
Shlc reg
Shlc reg, eaddr
Shr reg1, reg2
Shr reg
Shr reg, eaddr
Shrc reg1, reg2
Shrc reg
Shrc reg, eaddr
Shra reg1, reg2
Shra reg
Shra reg, eaddr
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg2<<1; a[0] := 0; C := reg2[7]; reg1 := a
a := reg<<1; a[0] := 0; C := reg[7]; reg := a
a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7]; reg := a
a := reg2<<1; a[0] := C; C := reg2[7]; reg1 := a
a := reg<<1; a[0] := C; C := reg[7]; reg := a
a := DM(eaddr)<<1; a[0] := C; C := DM(eaddr)[7]; reg := a
a := reg2>>1; a[7] := 0; C := reg2[0]; reg1 :=a
a := reg>>1; a[7] := 0; C := reg[0]; reg := a
a := DM(eaddr)>>1; a[7] := 0; C := DM(eaddr)[0]; reg := a
a := reg2>>1; a[7] := C; C := reg2[0]; reg1 := a
a := reg>>1; a[7] := C; C := reg[0]; reg := a
a := DM(eaddr)>>1; a[7] := C; C := DM(eaddr)[0]; reg := a
a := reg2>>1; a[7] := reg2[7]; C := reg2[0]; reg1 := a
a := reg>>1; a[7] := reg[7]; C := reg[0]; reg := a
a := DM(eaddr)>>1; a[7] := DM(eaddr)[7]; C := DM(eaddr)[0]; reg := a
Cpl1 reg1, reg2
Cpl1 reg
Cpl1 reg, eaddr
Cpl2 reg1, reg2
Cpl2 reg
Cpl2 reg, eaddr
Cpl2c reg1, reg2
Cpl2c reg
Cpl2c reg, eaddr
-,-, Z, a
-,-, Z, a
-,-, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := NOT(reg2); reg1 := a
a := NOT(reg); reg := a
a := NOT(DM(eaddr)); reg := a
a := NOT(reg2)+1; if a=0 then C:=1 else C := 0; reg1 := a
a := NOT(reg)+1; if a=0 then C:=1 else C := 0; reg := a
a := NOT(DM(eaddr))+1; if a=0 then C:=1 else C := 0; reg := a
a := NOT(reg2)+C; if a=0 and C=1 then C:=1 else C := 0; reg1 := a
a := NOT(reg)+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
a := NOT(DM(eaddr))+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
Inc reg1, reg2
Inc reg
Inc reg, eaddr
Incc reg1, reg2
Incc reg
Incc reg, eaddr
Dec reg1, reg2
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg2+1; if a=0 then C := 1 else C := 0; reg1 := a
a := reg+1; if a=0 then C := 1 else C := 0; reg := a
a := DM(eaadr)+1; if a=0 then C := 1 else C := 0; reg := a
a := reg2+C; if a=0 and C=1 then C := 1 else C := 0; reg1 := a
a := reg+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
a := DM(eaadr)+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
a := reg2-1; if a=hFF then C := 0 else C := 1; reg1 := a
© Semtech 2006
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3-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Dec reg
Dec reg, eaddr
Decc reg1, reg2
Decc reg
Decc reg, eaddr
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg-1; if a=hFF then C := 0 else C := 1; reg := a
a := DM(eaddr)-1; if a=hFF then C := 0 else C := 1; reg := a
a := reg2-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg1 := a
a := reg-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
a := DM(eaddr)-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a
And reg,#data[7:0]
And reg1, reg2, reg3
And reg1, reg2
And reg, eaddr
Or reg,#data[7:0]
Or reg1, reg2, reg3
Or reg1, reg2
Or reg, eaddr
Xor reg,#data[7:0]
Xor reg1, reg2, reg3
Xor reg1, reg2
Xor reg, eaddr
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
a := reg and data[7:0]; reg := a
a := reg2 and reg3; reg1 := a
a := reg1 and reg2; reg1 := a
a := reg and DM(eaddr); reg := a
a := reg or data[7:0]; reg := a
a := reg2 or reg3; reg1 := a
a := reg1 or reg2; reg1 := a
a := reg or DM(eaddr); reg := a
a := reg xor data[7:0]; reg := a
a := reg2 xor reg3; reg1 := a
a := reg1 xor reg2; reg1 := a
a := reg or DM(eaddr); reg := a
Add reg,#data[7:0]
Add reg1, reg2, reg3
Add reg1, reg2
Add reg, eaddr
Addc reg,#data[7:0]
Addc reg1, reg2, reg3
Addc reg1, reg2
Addc reg, eaddr
Subd reg,#data[7:0]
Subd reg1, reg2, reg3
Subd reg1, reg2
Subd reg, eaddr
Subdc reg,#data[7:0]
Subdc reg1, reg2, reg3
Subdc reg1, reg2
Subdc reg, eaddr
Subs reg,#data[7:0]
Subs reg1, reg2, reg3
Subs reg1, reg2
Subs reg, eaddr
Subsc reg,#data[7:0]
Subsc reg1, reg2, reg3
Subsc reg1, reg2
Subsc reg, eaddr
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg+data[7:0]; if overflow then C:=1 else C := 0; reg := a
a := reg2+reg3; if overflow then C:=1 else C := 0; reg1 := a
a := reg1+reg2; if overflow then C:=1 else C := 0; reg1 := a
a := reg+DM(eaddr); if overflow then C:=1 else C := 0; reg := a
a := reg+data[7:0]+C; if overflow then C:=1 else C := 0; reg := a
a := reg2+reg3+C; if overflow then C:=1 else C := 0; reg1 := a
a := reg1+reg2+C; if overflow then C:=1 else C := 0; reg1 := a
a := reg+DM(eaddr)+C; if overflow then C:=1 else C := 0; reg := a
a := data[7:0]-reg; if underflow then C := 0 else C := 1; reg := a
a := reg2-reg3; if underflow then C := 0 else C := 1; reg1 := a
a := reg2-reg1; if underflow then C := 0 else C := 1; reg1 := a
a := DM(eaddr)-reg; if underflow then C := 0 else C := 1; reg := a
a := data[7:0]-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
a := reg2-reg3-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := reg2-reg1-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := DM(eaddr)-reg-(1-C); if underflow then C := 0 else C := 1; reg := a
a := reg-data[7:0]; if underflow then C := 0 else C := 1; reg := a
a := reg3-reg2; if underflow then C := 0 else C := 1; reg1 := a
a := reg1-reg2; if underflow then C := 0 else C := 1; reg1 := a
a := reg-DM(eaddr); if underflow then C := 0 else C := 1; reg := a
a := reg-data[7:0]-(1-C); if underflow then C := 0 else C := 1; reg := a
a := reg3-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := reg1-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a
a := reg-DM(eaddr)-(1-C); if underflow then C := 0 else C := 1; reg := a
Mul reg,#data[7:0]
Mul reg1, reg2, reg3
Mul reg1, reg2
Mul reg, eaddr
Mula reg,#data[7:0]
Mula reg1, reg2, reg3
Mula reg1, reg2
Mula reg, eaddr
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8]
a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8]
a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8]
a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8]
Mshl reg,#shift[2:0]
Mshr reg,#shift[2:0]
Mshra reg,#shift[2:0]
u, u, u, a
u, u, u, a
u, u, u, a*
a := (reg*2 )[7:0]; reg := (reg*2 )[15:8]
(8-shift
(8-shift
a := (reg*2
)[7:0]; reg := (reg*2
)[15:8]
(8-shift
(8-shift
a := (reg*2
)[7:0]; reg := (reg*2
)[15:8]
Cmp reg,#data[7:0]
Cmp reg1, reg2
Cmp reg, eaddr
Cmpa reg,#data[7:0]
Cmpa reg1, reg2
Cmpa reg, eaddr
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
Tstb reg,#bit[2:0]
Setb reg,#bit[2:0]
Clrb reg,#bit[2:0]
Invb reg,#bit[2:0]
-, -, Z, a
-, -, Z, a
-, -, Z, a
-, -, Z, a
a[bit] := reg[bit]; other bits in a are 0
reg[bit] := 1; other bits unchanged; a := reg
reg[bit] := 0; other bits unchanged; a := reg
reg[bit] := not reg[bit]; other bits unchanged; a := reg
shift
shift
© Semtech 2006
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3-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Sflag
-,-,-, a
a[7] := C; a[6] := C xor V; a[5] := ST full; a[4] := ST empty
Rflag reg
Rflag eaddr
C, V, Z, a
C, V, Z, a
a := reg << 1; ; a[0] := 0; C := reg[7]
a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7]
Freq divn
-,-,-, -
reduces the CPU frequency (divn=nodiv, div2, div4, div8, div16)
Halt
-,-,-, -
halts the CPU
Nop
-,-,-, -
no operation
- = unchanged, u = undefined, *MSHR reg,# 1 doesn’t shift by 1
Table 3-4. Instruction short reference
The Coolrisc816 has 8 different addressing modes. These modes are described in Table 3-5. In this table, the
notation ix refers to one of the data memory index registers i0, i1, i2 or i3. Using eaddr in an instruction of Table 3-4
will access the data memory at the address DM(eaddr) and will simultaneously execute the index operation.
extended address
eaddr
addr[7:0]
(ix)
(ix, offset[7:0])
(ix,r3)
(ix)+
(ix,offset[7:0])+
-(ix)
-(ix,offset[7:0])
accessed data memory
location
DM(eaddr)
DM(h00&addr[7:0])
DM(ix)
DM(ix+offset)
DM(ix+r3)
DM(ix)
DM(ix+offset)
DM(ix-1)
DM(ix-offset)
index
operation
ix := ix+1
ix := ix+offset
ix := ix-1
ix := ix -offset
direct addressing
indexed addressing
indexed addressing with immediate offset
indexed addressing with register offset
indexed addressing with index post-increment
indexed addressing with index post-increment by the offset
indexed addressing with index pre-decrement
indexed addressing with index pre-decrement by the offset
Table 3-5. Extended address mode description
Eleven different jump conditions are implemented as shown in Table 3-6. The contents of the column CC in this
table should replace the CC notation in the instruction description of Table 3-4.
CC
condition
CS
CC
ZS
ZC
VS
VC
EV
C=1
C=0
Z=1
Z=0
V=1
V=0
(EV1 or EV0)=1
After CMP op1,op2
EQ
NE
GT
GE
LT
LE
op1=op2
op1≠op2
op1>op2
op1≥op2
op1<op2
op1≤op2
Table 3-6. Jump condition description
© Semtech 2006
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3-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4 Memory Mapping
4.1
Memory organisation
4-2
4.2
Instruction memory and NFASTREAD
4-2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.3.15
4.3.16
4.3.17
4.3.18
4.3.19
4.3.20
Quick reference data memory register map
Low power data registers (h0000-h0007)
System, clock configuration and reset configuration (h0010-h001F)
Port A (h0020-h0027)
Port B (h0028-h002F)
Port D1 (h0030-h0033)
Port D2 (h0034-h0037)
Flash programming (h0038-003B)
Event handler (h003C-h003F)
Interrupt handler (h0040-h0047)
USRT (h0048-h004F)
UART (h0050-h0057)
Counter/Timer/PWM registers (h0058-h005F)
Acquisition chain registers (h0060-h0067)
SPI registers (h0068-h006F)
LCD voltage generator registers (h0070)
Comparator registers (h0072-h0073)
Voltage multiplier (h007C)
Voltage Level Detector registers (h007E-h007F)
RAM (h0080-h047F)
LCD driver (h8000-8022)
© Semtech 2006
4-3
4-4
4-4
4-5
4-5
4-5
4-6
4-6
4-6
4-7
4-7
4-8
4-8
4-8
4-9
4-9
4-9
4-9
4-9
4-9
4-10
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4-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.1
Memory organisation
The XE8802 CPU is built with Harvard architecture. Harvard architecture uses separate instruction and data
memories. The instruction bus and data bus are also separated. The advantage of such a structure is that the CPU
can get a new instruction and read/write data simultaneously. The circuit configuration is shown in Figure 4-1. The
CPU has its 16 internal registers. The instruction memory has a capacity of 8192 22-bit instructions if the pin
NFASTREAD=1. The instruction memory has a capacity of 4096 22-bit instructions if the pin NFASTREAD=0. The
data memory space has 8 low power registers, the peripheral register space, 1024 bytes of RAM and the LCD
control register space.
µF0h1FFF
µF
0h8022
LCD registers
CPU
4k x 22bit
NFASTREAD=0
capacity:
1024 bytes
r1
r2
r3
i0h
i0l
i1h
i1l
i2h
i2l
i3h
i3l
0h007F
Peripheral
registers
iph
ipl
0h0008
0h0080
stat
Data memory
NFASTREAD=1
RAM
r0
data bus
capacity:
8k x 22bit
0h047F
CPU internal registers
Instruction
memory
instruction bus
0h8000
Low power
RAM
0h0000
a
Figure 4-1. Memory mapping
The CPU internal registers are described in the CPU chapter. A short reference of the low power registers and
peripheral registers is given in 4.3.
4.2
Instruction memory and NFASTREAD
As indicated in chapter 4.1, the instruction memory can be organized in two ways: 4096 instructions with a speed
of 4 to 6 MIPS or 8192 instructions with a speed of 2 to 3 MIPS (see XE8802 performance chapter for more
details).
Important Note:
When programming the device, the correct NFASTREAD option has to be selected in the programmer.
Failure to do so may result in non-functional software. The default option in the programme is
NFASTREAD=1, i.e. the 8k instruction slower operation mode.
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4-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Important Note:
In the actual version of the Prostart, the NFASTREAD pin is hard wired to VBAT. Nevertheless, the Prostart
can be used to program the device for both modes by (un)checking the NFASTREAD selection box in the
software loader. If the user wants to run the software programmed in the NFASTREAD=0 mode, he will
need to build his own application board which connects NFASTREAD=VSS.
4.3
Quick reference data memory register map
The data register map is given in the tables below. A more detailed description of the different registers is given in
the detailed description of the different peripherals.
The tables give the following information:
1. The register name and register address
2. The different bits in the register
3. The access mode of the different bits (see Table 4-4-1 for code description)
4. The reset source and reset value of the different bits
The reset source coding is given in Table 4-4-2. To get a full description of the reset sources, please refer to the
reset block chapter.
code
r
w
r0
r1
c
c1
ca
s
access mode
bit can be read
bit can be written
bit always reads 0
bit always reads 1
bit is cleared by writing any value
bit is cleared by writing a 1
bit is cleared after reading
special function, verify the detailed description in the respective peripherals
Table 4-4-1. Access mode codes used in the register definitions
code
glob
cold
pconf
sleep
reset source
nresetglobal
nresetcold
nresetpconf
nresetsleep
Table 4-4-2. Reset source coding used in the register definitions
© Semtech 2006
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4-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.3.1
Low power data registers (h0000-h0007)
Name
Address
7
6
5
Reg00
h0000
Reg01
h0001
Reg02
h0002
Reg03
h0003
Reg04
h0004
Reg05
h0005
Reg06
h0006
Reg07
h0007
4
3
Reg00[7:0]
rw, 00000000, glob
Reg01[7:0]
rw,00000000,glob
Reg02[7:0]
rw,00000000,glob
Reg03[7:0]
rw,00000000,glob
Reg04[7:0]
rw,00000000,glob
Reg05[7:0]
rw,00000000,glob
Reg06[7:0]
rw,00000000,glob
Reg07[/:0]
rw,0000000,glob
2
1
0
Table 4-4-3. Low power data registers
4.3.2
System, clock configuration and reset configuration (h0010-h001F)
Name
Address
7
RegSysCtrl SleepEn
h0010
rw,0,cold
RegSysReset
Sleep
h0011
rw,0,glob
RegSysClock
CpuSel
h0012
rw,0,sleep
RegSysMisc
h0013
r0
RegSysWd
h0014
r0
RegSysPre0
h0015
r0
RegSysRcTrim1
h001B
RegSysRcTrim2
h001C
6
ResetfromportA
r0
rc, 0, cold
EnExtClock
rw,0,cold
4
EnResetWD
rw,0,cold
ResetWD
rc, 0, cold
BiasRC
rw,1,cold
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
RcFreqRange
rw,0,cold
EnResetPConf
rw,0,cold
SleepFlag
rc,0,cold
r0
r0
r0
r0
5
EnBusError
rw,0,cold
ResetBusError
3
2
1
0
r0
r0
r0
r0
rc, 0, cold
ColdXtal
r,1,sleep
r0
r0
r0
r0
EnableXtal EnableRC
r0
rw,0,sleep rw,1,sleep
Output16k OutputCpuCk
r0
rw,0,sleep rw,0,sleep
WatchDog[3:0]
s,0000,glob
r0
r0
ClearLowPresca
l
c1r0,0,-
RcFreqCoarse[3:0]
rw,0001,cold
RcFreqFine[5:0]
rw,00000,cold
Table 4-4-4. Reset block and clock block registers
© Semtech 2006
www.semtech.com
4-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.3.3
Port A (h0020-h0027)
Name
Address
7
6
5
3
PAIn[7:0]
r
PADebounce[7:0]
rw,00000000,pconf
PAEdge[7:0]
rw,00000000,glob
PAPullup[7:0]
rw,11111111,pconf
PARes0[7:0]
rw, 00000000, glob
PARes1[7:0]
rw,00000000,glob
2
1
0
r0
r0
r0
r0
r0
PASnaptorail[7:0]
rw,00000000,pconf
r0
r0
DebFast
rw,0,pconf
RegPAIn
h0020
RegPADebounce
h0021
RegPAEdge
h0022
RegPAPullup
h0023
RegPARes0
h0024
RegPARes1
h0025
RegPACtrl
h0026
RegPASnaptorail
h0027
4
Table 4-4-5. Port A registers
4.3.4
Port B (h0028-h002F)
Name
Address
7
6
5
3
PBOut[7:0]
rw,00000000,pconf
PBIn[7:0]
r
PBDir[7:0]
rw,00000000,pconf
PBOpen[7:0]
rw,00000000,pconf
PBPullup[7:0]
rw,11111111,pconf
PBAna[7:0]
rw,00000000,pconf
2
1
0
5
4
3
PD1Out[7:0]
rw,00000000,pconf
PD1In[7:0]
r
PD1Dir[7:0]
rw,00000000,pconf
2
1
0
RegPBOut
h0028
RegPBIn
h0029
RegPBDir
h002A
RegPBOpen
h002B
RegPBPullup
h002C
RegPBAna
h002D
4
Table 4-4-6. Port B registers
4.3.5
Port D1 (h0030-h0033)
Name
Address
RegPD1Out
h0030
RegPD1In
h0031
RegPD1Dir
h0032
RegPD1Pullup
h0033
7
6
PD1SnapToRail[3:0]
rw,0000,pconf
PD1Pullup[3:0]
rw,1111,pconf
Table 4-4-7. Port D1 registers
© Semtech 2006
www.semtech.com
4-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.3.6
Port D2 (h0034-h0037)
Name
Address
RegPD2Out
h0034
RegPD2In
h0035
RegPD2Dir
h0036
RegPD2Pullup
h0037
7
6
5
4
3
PD2Out[7:0]
rw,00000000,pconf
PD2In[7:0]
r
PD2Dir[7:0]
rw,00000000,pconf
PD2SnapToRail[3:0]
rw,0000,pconf
2
1
0
PD2Pullup[3:0]
rw,1111,pconf
Table 4-4-8. Port D2 registers
4.3.7
Flash programming (h0038-003B)
These four registers are used during flash programming only. Refer to the flash programming algorithm
documentation for more details.
4.3.8
Event handler (h003C-h003F)
Name
Address
RegEvn
h003C
RegEvnEn
h003D
RegEvnPriority
h003E
RegEvnEvn
h003F
7
CntIrqA
rc1,0,glob
6
CntIrqC
rc1,0,glob
5
128Hz
rc1,0,glob
r0
r0
r0
4
3
PAEvn[1]
CntIrqB
rc1,0,glob rc1,0,glob
EvnEn[7:0]
rw,00000000,glob
EvnPriority[7:0]
r,11111111,glob
r0
r0
2
CntIrqD
rc1,0,glob
1
1Hz
rc1,0,glob
0
PAEvn[0]
rc1,0,glob
r0
EvnHigh
r,0,glob
EvnLow
r,0,glob
Table 4-4-9. Event handler registers
The origin of the different events is summarised in the table below.
Event
CntIrqA
CntIrqB
CntIrqC
CntIrqD
128Hz
1Hz
PAEvn[1:0]
Event source
Counter/Timer A (counter block)
Counter/Timer B (counter block)
Counter/Timer C (counter block)
Counter/Timer D (counter block)
Low prescaler (clock block)
Low prescaler (clock block)
Port A
Table 4-4-10. Event source description
© Semtech 2006
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4-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.3.9
Interrupt handler (h0040-h0047)
Name
Address
7
IrqAC
h0040
rc1,0,glob
RegIrqMid UsrtCond2
h0041
rc1,0,glob
RegIrqLow PAIrq[7]
h0042
rc1,0,glob
RegIrqEnHig
h0043
RegIrqEnMid
h0044
RegIrqEnLow
h0045
RegIrqPriority
h0046
RegIrqIrq
h0047
r0
RegIrqHig
6
128Hz
rc1,0,glob
UrstCond1
rc1,0,glob
PAIrq[6]
rc1,0,glob
5
IrqSPI
rc1,0,glob
PAIrq[5]
rc1,0,glob
CntIrqB
rc1,0,glob
r0
r0
4
3
CntIrqA
CntIrqC
rc1,0,glob rc1,0,glob
PAIrq[4]
1Hz
rc1,0,glob rc1,0,glob
CntIrqD
PAIrq[3]
rc1,0,glob rc1,0,glob
IrqEnHig[7:0]
rw,0000000,glob
IrqEnMid[7:0]
rw,0000000,glob
IrqEnLow[7:0]
rw,0000000,glob
IrqPriority[7:0]
r,11111111,glob
r0
r0
2
CmpdIrq
rc1,0,glob
VldIrq
rc1,0,glob
PAIrq[2]
rc1,0,glob
1
UartIrqTx
rc1,0,glob
PAIrq[1]
rc1,0,glob
0
UartIrqRx
rc1,0,glob
PAIrq[0]
rc1,0,glob
r0
r0
IrqHig
r,0,glob
IrqMid
r,0,glob
IrqLow
r,0,glob
1
Table 4-4-11. Interrupt handler registers
The origin of the different interrupts is summarised in the table below.
Event
CmpdIrq
CntIrqA
CntIrqB
CntIrqC
CntIrqD
128Hz
1Hz
PAIrq[7:0]
UartIrqRx
UartIrqTx
UrstCond1
UsrtCond2
VldIrq
IrqAC
IrqSPI
Event source
Low power comparators
Counter/Timer A (counter block)
Counter/Timer B (counter block)
Counter/Timer C (counter block)
Counter/Timer D (counter block)
Low prescaler (clock block)
Low prescaler (clock block)
Port A
UART reception
UART transmission
USRT condition 1
USRT condition 2
Voltage level detector
Acquisition chain end of conversion interrupt
SPI end of reception/transmission interrupt
Table 4-4-12. Interrupt source description
4.3.10
USRT (h0048-h004F)
Name
Address
7
6
5
4
3
2
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
UsrtEnWaitCond1
RegUsrtS1
h0048
RegUsrtS0
h0049
RegUsrtCond1
h004A
RegUsrtCond2
h004B
RegUsrtCtrl
h004C
RegUsrtBufferS1
h004D
RegUsrtEdgeS0
h004E
r0
r0
r0
r0
r0
UsrtWaitS0
r,0,glob
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
rw,0,glob
0
UsrtS1
r0
s,1,glob
UsrtS0
r0
s,1,glob
UsrtCond1
r0
rc,0,glob
UsrtCond2
r0
rc,0,glob
UsrtEnWaitS0 UsrtEnable
rw,0,glob
rw,0,glob
UsrtBufferS1
r0
r,0,glob
UsrtEdgeS0
r0
r,0,glob
Table 4-4-13. USRT register description
© Semtech 2006
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4-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.3.11
UART (h0050-h0057)
Name
Address
RegUartCtrl
h0050
RegUartCmd
h0051
RegUartTx
h0052
RegUartTxSta
h0053
RegUartRx
h0054
RegUartRxSta
h0055
7
UartEcho
rw,0,glob
SelXtal
rw,0,glob
6
UartEnRx
rw,0,glob
r0
r0
r0
r0
5
UartEnTx
rw,0,glob
r0
4
3
UartXRx
UartXTx
rw,0,glob
rw,0,glob
UartRcSel[2:0]
rw,000,glob
UartTx[7:0]
rw,0000000,glob
2
UartPM
rw,0,glob
1
UartBR[2:0]
rw,101,glob
UartPE
rw,0,glob
0
UartWL
rw,1,glob
UartTxBusy UartTxFull
r0
r0
r0
r,0,glob
r,0,glob
UartRx[7:0]
r,00000000,glob
UartRxSErr UartRxPErr UartRxFErr UartRxOerr UartRxBusy UartRxFull
r,0,glob
r,0,glob
r,0,glob
rc,0,glob
r,0,glob
r,0,glob
r0
Table 4-14. UART register description
4.3.12
Counter/Timer/PWM registers (h0058-h005F)
Name
Address
7
RegCntA
h0058
RegCntB
h0059
RegCntC
h005A
RegCntD
h005B
RegCntCtrlCk
h005C
RegCntConfig1
h005D
RegCntConfig2
h005E
RegCntOn
h005F
6
5
4
3
2
1
0
CounterA[7:0]
s,00000000,glob
CounterB[7:0]
s,00000000,glob
CounterC[7:0]
s,00000000,glob
CounterD[7:0]
s,00000000,glob
CntDCkSel[1:0]
CntCCkSel[1:0]
CntBCkSel[1:0]
CntACkSel[1:0]
rw,00,glob
rw,00,glob
rw,00,glob
rw,00,glob
CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD CascadeAB CntPWM1 CntPWM0
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
CapSel[1:0]
CapFunc[1:0]
Pwm1Size[1:0]
Pwm0Size[1:0]
rw,00,glob
rw,00,glob
rw,00,glob
rw,00,glob
CntDExtDiv CntCExtDiv CntBExtDiv CntAExtDiv CntDEnable CntCEnable CntBEnable CntAEnable
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
rw,0,glob
Table 4-15. Counter/timer/PWM register description.
4.3.13
Acquisition chain registers (h0060-h0067)
Name
Address
7
6
5
4
3
2
1
RegAcOutLsb
OUT[7:0]
h0060
r,0,glob
RegAcOutMsb
OUT[15:8]
h0061
r,0,glob
RegAcCfg0
START
SET_NELCONV[1:0]
SET_OSR[2:0]
CONT
h0062
w r0,0,glob
rw,01,glob
rw,010,glob
rw,0,glob
RegAcCfg1
IB_AMP_ADC[1:0]
IB_AMP_PGA[1:0]
ENABLE[3:0]
h0063
rw,11,glob
rw,11,glob
rw,0000,glob
RegAcCfg2
FIN
PGA2_GAIN[1:0]
PGA2_OFFSET[3:0]
h0064
rw,00,glob
rw,00,glob
rw,0000,glob
RegAcCfg3 PGA1_GAIN
PGA3_GAIN[6:0]
h0065
rw,0000000,glob
Rw,0,glob
RegAcCfg4
PGA3_OFFSET
h0066
r0
rw,0000000,glob
RegAcCfg5
BUSY
DEF
AMUX[4:0]
h0067
r,0,glob
w r0
rw,00000,glob
0
r0
VMUX
rw,0,glob
Table 4-16. Acquisition chain register description.
© Semtech 2006
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4-8
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.3.14
SPI registers (h0068-h006F)
Name
Address
7
6
RegSpiControl ClearCounter NotSlaveSelect
rw,1,glob
h0068
c1 r0
RegSpiStatus
h0069
r0
r0
RegSpiDataOut
h006A
RegSpiDataIn
h006B
RegSpiPullup
h006C
r0
r0
RegSpiDir
h006D
r0
r0
5
SpiMaster
rw,1,glob
r0
r0
r0
4
3
2
1
0
SpiEnable ClockPhase ClockPolarity
BaudRate[1:0]
rw,0,glob
rw,1,glob
rw,00,glob
rw,0,glob
SpiOverflow SpiRxFull
SpiTxEmpty
r0
r0
r c1,0,glob
r,0,glob
r w1,1,glob
SpiDataOut[7:0]
rw,00000000,glob
SpiDataIn[7:0]
r,00000000,glob
SpiPullup[3:0]
r0
rw,1111,pconf
SpiDir[3:0]
r0
rw,0000,pconf
Table 4-17. SPI register description.
4.3.15
LCD voltage generator registers (h0070)
Name
Address
RegVgenCfg0
h0070
7
6
r0
r0
5
4
VgenClkSel[1:0]
rw,10,glob
3
VgenOff
rw,1,glob
2
VgenMode
rw,0,glob
1
VgenStdb
rw,0,glob
0
VgenRefEn
rw,0,glob
Table 4-18. LCD voltage generator register.
4.3.16
Comparator registers (h0072-h0073)
Name
Address
RegCmpdStat
h0072
RegCmpdCtrl
h0073
7
6
5
CmpdStat[3:0]
rca,0000,glob
IrqOnRising[2:0]
rw,000,glob
4
3
2
1
CmpdOut[3:0]
r,0000,glob
EnIrqCh[3:0]
rw,0000,glob
0
Enable
rw,0,glob
Table 4-19. Low power comparator registers
4.3.17
Voltage multiplier (h007C)
Name
Address
RegVmultCfg0
h007C
7
r0
6
r0
5
r0
4
3
r0
r0
2
Enable
rw,0,glob
1
0
Fin[1:0]
rw,00,glob
Table 4-20. VMULT register.
4.3.18
Voltage Level Detector registers (h007E-h007F)
Name
Address
7
6
5
4
r0
r0
r0
r0
3
VldRange
rw,0,glob
r0
r0
r0
r0
r0
RegVldCtrl
h007E
RegVldStat
h007F
2
1
VldTune[2:0]
rw,000,glob
VldResult
VldValid
r,0,glob
r,0,glob
0
VldEn
rw,0,glob
Table 4-21. Voltage level detector register description
4.3.19
RAM (h0080-h047F)
The 1024 RAM bytes can be accessed for read and write operations. The RAM has no reset function. Variables
stored in the RAM should be initialised before use since they can have any value at circuit start up.
© Semtech 2006
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4-9
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4.3.20
LCD driver (h8000-8022)
Name
Address
RegLcdData0
h8000
RegLcdData1
h8001
RegLcdData2
h8002
RegLcdData3
h8003
RegLcdData4
h8004
RegLcdData5
h8005
RegLcdData6
h8006
RegLcdData7
h8007
RegLcdData8
h8008
RegLcdData9
h8009
RegLcdData10
h800A
RegLcdData11
h800B
RegLcdData12
h800C
RegLcdData13
h800D
RegLcdData14
h800E
RegLcdData15
h800F
RegPLcdOut0
h8010
RegPLcdOut1
h8011
RegPLcdOut2
h8012
RegPLcdOut3
h8013
RegPLcdDir0
h8014
RegPLcdDir1
h8015
RegPLcdDir2
h8016
RegPLcdDir3
h8017
RegPLcdPullup0
h8018
RegPLcdPullup1
h8019
RegPLcdPullup2
h801A
RegPLcdPullup3
h801B
RegPLcdIn0
h801C
RegPLcdIn1
h801D
RegPLcdIn2
h801E
RegPLcdIn3
h801F
7
6
5
4
3
LcdData0[7:0]
rw,00000000,pconf
LcdData1[7:0]
rw,00000000,pconf
LcdData2[7:0]
rw,00000000,pconf
LcdData3[7:0]
rw,00000000,pconf
LcdData4[7:0]
rw,00000000,pconf
LcdData5[7:0]
rw,00000000,pconf
LcdData6[7:0]
rw,00000000,pconf
LcdData7[7:0]
rw,00000000,pconf
LcdData8[7:0]
rw,00000000,pconf
LcdData9[7:0]
rw,00000000,pconf
LcdData10[7:0]
rw,00000000,pconf
LcdData11[7:0]
rw,00000000,pconf
LcdData12[7:0]
rw,00000000,pconf
LcdData13[7:0]
rw,00000000,pconf
LcdData14[7:0]
rw,00000000,pconf
LcdData15[7:0]
rw,00000000,pconf
PLcdOut0[7:0]
rw,00000000,pconf
PLcdOut1[7:0]
rw,00000000,pconf
PLcdOut2[7:0]
rw,00000000,pconf
PLcdOut3[7:0]
rw,00000000,pconf
PLcdDir0[7:0]
rw,00000000,pconf
PLcdDir1[7:0]
rw,00000000,pconf
PLcdDir2[7:0]
rw,00000000,pconf
PLcdDir3[7:0]
rw,00000000,pconf
PLcdPullup0[7:0]
rw,00000000,pconf
PLcdPullup1[7:0]
rw,00000000,pconf
PLcdPullup2[7:0]
rw,00000000,pconf
PLcdPullup3[7:0]
rw,00000000,pconf
PLcdIn0[7:0]
r
PLcdIn1[7:0]
r
PLcdIn2[7:0]
r
PLcdIn3[7:0]
r
© Semtech 2006
2
1
0
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4-10
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
r0
LcdSe15
rw,1,glob
r0
LcdSe19
rw,1,glob
LcdSleep
rw,1,glob
LcdSe23
rw,1,glob
r0
r0
r0
RegLcdOn
h8020
RegLcdSe
h8021
RegLcdClkFrame
h8022
r0
LcdSe3
rw,1,glob
r0
r0
LcdSe7
LcdSe11
rw,1,glob
rw,1,glob
LcdDivFreq[2:0]
rw,000,glob
LcdMux[1:0]
rw,00,glob
LcdSe27
LcdSe31
rw,1,glob
rw,1,glob
LcdFreq[1:0]
rw,00,glob
Table 4-22. LCD driver registers.
© Semtech 2006
www.semtech.com
4-11
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
5. Low Power Modes
5.1
5.1.1
5.2
FEATURES ........................................................................................................................................ 5-2
Overview ......................................................................................................................................... 5-2
OPERATING MODE ............................................................................................................................. 5-2
© Semtech 2006
www.semtech.com
5-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
5.1
5.1.1
Features
Overview
The XE8000 chips have three operating modes. These are the normal, low current and very low current modes
(see Figure 5-1). The different modes are controlled by the reset and clock blocks (see the documentation of the
respective blocks).
5.2
Operating mode
Start-up
All bits are reset in the design when a POR or padnreset is active.
RC is enabled, Xtal is disabled and CPU is reset (pmaddr = 0000).
If the port A is used to return from the sleep mode, all bits with nresetcold do not change (see sleep mode)
Start-up
All bits with nresetglobal and nresetpconf(if enabled) are reset. Clock configuration doesn’t change except cpuck
(freqdiv is reset, see clock block). CPU is reset
Active mode
This is the mode where the CPU and all peripherals can work and execute the embedded software.
Standby mode
Executing a HALT instruction moves the XE8000 into the Standby mode. The CPU is stopped, but the clocks
remain active. Therefore, the enabled peripherals remain active e.g. for time keeping. A reset or an interrupt/event
request (if enabled) cancels the standby mode.
Sleep mode
This is a very low-power mode because all circuit clocks and all peripherals are stopped. Only some service blocks
remain active. No time-keeping is possible. Two instructions are necessary to move into sleep mode. First, the
SleepEn (sleep enable) bit in RegSysCtrl has to be set to 1. The sleep mode can then be activated by setting the
Sleep bit in RegSysReset to 1.
There are three possibe ways to wake-up from the sleep mode:
1. The POR (power-on-reset caused by a power-down followed by power-on). The RAM information is
lost.
2. The padnreset
3. The Port A reset combination (if the Port A is present in the product). See Port A documentation for
more details.
Note:
If the Port A is used to return from the sleep mode, all bits with nresetcold do not change (RegSysCtrl,
RegSysReset (except bit sleep), Enextclock and Biasrc in RegSysClock, RegSysRcTrim1 and
RegSysRcTrim2). The SleepFlag bit in RegSysReset, reads back a 1 if the circuit was in sleep mode
since the flag was last cleared (see reset block for more details).
Note:
It is recommended to insert a NOP instruction after the instruction that sets the circuit in sleep mode
because this instruction can be executed when the sleep mode is left using the resetfromportA.
© Semtech 2006
www.semtech.com
5-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
START-UP
without
condition
por
padnreset
por
padnreset
RESET
por
padnreset
without
condition
por
padnreset
portA reset
portA reset
watchdog reset
portA reset
watchdog reset
buserror reset
Halt instruction
ACTIVE
Interrupt/event
STAND-BY
SLEEP
set bit sleep
normal mode
low current
very low current
Figure 5-1. XE8000 operating modes.
© Semtech 2006
www.semtech.com
5-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
6. Reset Generator
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.6
6.7
6.8
6.9
FEATURES
OVERVIEW
REGISTER MAP
RESET HANDLING CAPABILITIES
RESET SOURCE DESCRIPTION
Power On Reset
NRESET pin
Programmable Port A input combination
Watchdog reset
BusError reset
SLEEP MODE
CONTROL REGISTER DESCRIPTION AND OPERATION
WATCHDOG
START-UP AND WATCHDOG SPECIFICATIONS
© Semtech 2006
6-2
6-2
6-2
6-3
6-4
6-4
6-4
6-4
6-4
6-5
6-5
6-5
6-5
6-6
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6-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
6.1
•
•
•
•
•
Features
Power On Reset (POR)
External reset from the NRESET pin
Programmable Watchdog timer reset
Programmable BusError reset
Sleep mode management
Product dependant:
• Programmable Port A input combination reset
6.2
Overview
The reset block is the reset manager. It handles the different reset sources and distributes them through the
system. It also controls the sleep mode of the circuit.
6.3
Register map
register name
RegSysCtrl
RegSysReset
RegSysWd
Table 6-1. Reset registers
Table 6-1 gives the different registers used by this block.
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6-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Pos.
7
RegSysCtrl
SleepEn
Rw
rw
Reset
0 nresetcold
6
EnResetPConf
rw
0 nresetcold
5
EnBusError
rw
0 nresetcold
4
EnResetWD
rw
0 nresetcold
-
r
0000
3–0
Function
enables Sleep mode
0: sleep mode is disabled
1: sleep mode is enabled
enables the nresetpconf signal when the
nresetglobal is active
0: nresetpconf is disabled
1: nresetpconf is enabled
enables reset from BusError
0: BusError reset source is disabled
1: BusError reset source is enabled
enables reset from Watchdog
0: Watchdog reset source is disabled
1: Watchdog reset source is enabled
this bit can not be set to 0 by SW
unused
Table 6-2. RegSysCtrl register.
Pos.
7
6
5
4
3
2–0
RegSysReset
Sleep
SleepFlag
ResetBusError
ResetWD
ResetfromportA
Rw
rw
rc
rc
rc
rc
r
Reset
0 nresetglobal
0 nresetcold
0 nresetcold
0 nresetcold
0 nresetcold
000
Function
Sleep mode control (reads always 0)
Sleep mode was active before
reset source was BusError
reset source was Watchdog
reset source was Port A combination
unused
Table 6-3. RegSysReset register
Pos.
7-4
3
2
1
0
RegSysWd
WDKey[3]
WDCounter[3]
WDKey[2]
WDCounter[2]
WDKey[1]
WDCounter[1]
WDKey[0]
WDCounter[0]
Rw
r
w
r
w
r
w
r
w
r
Reset
0000
Function
unused
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
Watchdog Key bit 3
Watchdog counter bit 3
Watchdog Key bit 2
Watchdog counter bit 2
Watchdog Key bit 1
Watchdog counter bit 1
Watchdog Key bit 0
Watchdog counter bit 0
Table 6-4. RegSysWd register
6.4
Reset handling capabilities
There are 5 reset sources:
• Power On Reset (POR)
• External reset from the NRESET pin
• Programmable port A input combination
• Programmable watchdog timer reset
• Programmable BusError reset on processor access outside the allocated memory map
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6-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Another reset source is the bit Sleep in the RegSysReset register. This source is fully controlled by software and is
only used during the sleep mode.
Four internal reset signals are generated from these sources and distributed through the system:
• nresetcold:
is asserted on POR or by the NRESET pin
• nresetglobal: is asserted when nresetcold or any other enabled reset source is active
• nresetsleep: is asserted when the circuit is in sleep mode
• nresetpconf: is asserted when nresetglobal is active and if the EnResetPConf bit in the RegSysCtrl
register is set. This reset is generally used in the different ports. It allows to maintain the port configuration
unchanged while the rest of the circuit is reset.
Table 6-5 shows a summary of the dependency of the internal reset signals on the various reset sources.
In all the tables describing the different registers, the reset source is indicated.
Internal reset signals
Asserted
reset source
nresetglobal
POR
NRESET pin
PortA input
Watchdog
BusError
Sleep
Asserted
Asserted
Asserted
Asserted
Asserted
-
nresetpconf
when
when
EnResetPConf EnRestPConf
is set to 0
is set to 1
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
-
nresetsleep
nresetcold
Asserted
Asserted
Asserted
Asserted
Asserted
-
Table 6-5. Internal reset assertion as a function of the reset source.
6.5
6.5.1
Reset source description
Power On Reset
The power on reset (POR) monitors the external supply voltage. It activates a reset on a rising edge of this supply
voltage. The reset is inactivated only if the internal voltage regulator has started up. The POR block performs no
precise voltage level detection.
6.5.2
NRESET pin
Applying a low input state on the NRESET pin can activate the reset.
6.5.3
Programmable Port A input combination
Port A (if present in the product) can generate a reset signal.
information.
6.5.4
See the description of the Port A for further
Watchdog reset
The Watchdog will generate a reset if the EnResetWD bit in the RegSysCtrl register has been set and if the
watchdog is not cleared in time by the processor. See chapter 6.8 describing the watchdog for further information.
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6-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
6.5.5
BusError reset
The address space is assigned as shown in the register map of the product. If the EnBusError bit in the
RegSysCtrl register is set and the software accesses an unused address, a reset is generated.
6.6
Sleep mode
Entering the sleep mode will reset a part of the circuit. The reset is used to configure the circuit for correct wake-up
after the sleep mode. If the SleepEn bit in the RegSysCtrl register has been set, the sleep mode can be entered
by setting the bit Sleep in RegSysReset. During the sleep mode, the nresetsleep signal is active. For detailed
information on the sleep mode, see the system documentation.
6.7
Control register description and operation
Two registers are dedicated for reset status and control, RegSysReset and RegSysCtrl. The bits Sleep,
SleepFlag and SleepEn are also located in those registers and are described in the chapter dedicated to the
different operating modes of the circuit (system block).
The RegSysReset register gives information on the source that generated the last reset. It can be read at the
beginning of the application program to detect if the circuit is recovering from an error or exception condition, or if
the circuit is starting up normally.
• when ResetBusError is 1, a forbidden address access generated the reset.
• when ResetWD is 1, the watchdog generated the reset.
• when ResetfromPortA is 1, a PortA combination generated the reset.
Note: If no bit is set to 1, the reset source was either the NRESET pin or the internal POR.
Note: Several bits might be set or not, if the register was not cleared in between 2 reset occurrences.
The two other bits concern the sleep mode control and information (see system documentation for the sleep mode
description).
• When SleepFlag is 1, the sleep mode was active before the reset occurred. This bit will always appear
together with the ResetfromPortA bit since all other possibilities to leave the sleep mode (POR and
NRESET pin) will clear the SleepFlag.
• When Sleep is set to 1, and SleepEn is 1, the sleep mode is entered. The bit always reads back a 0.
The RegSysCtrl register enables the different available reset sources and the sleep mode.
• EnBusError enables the reset due to a bus error condition.
• EnResetWD enables the reset due to the watchdog (can not be disabled once enabled).
• EnResetPConf enables the reset of the port configurations when reset by Port A, a Bus Error or the
watchdog.
• SleepEn unlocks the Sleep bit. As long as SleepEn is 0, the Sleep bit has no effect.
6.8
Watchdog
The watchdog is a timer, which has to be cleared at least every 2 seconds by the software to prevent a reset to be
generated by the timeout condition.
The watchdog can be enabled by software by setting the EnResetWD bit in the RegSysCtrl register to 1. It can
then only be disabled by a power on reset or by setting the NRESET pin to a low state.
The watchdog timer can be cleared by writing consecutively the values Hx0A and Hx03 to the RegSysWd register.
The sequence must strictly be respected to clear the watchdog.
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6-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
In assembler code, the sequence to clear the watchdog is:
move AddrRegSysWd, #0x0A
move AddrRegSysWd, #0x03
Only writing Hx0A followed by Hx03 resets the WD. If some other write instruction is done to the RegSysWd
between the writing of the Hx0A and Hx03 values, the watchdog timer will not be cleared.
It is possible to read the status of the watchdog in the RegSysWd register. The watchdog is a 4 bit counter with a
count range between 0 and 7. The system reset is generated when the counter is reaching the value 8.
6.9
Start-up and watchdog specifications
At start-up of the circuit, the POR block generates a reset signal during tPOR. The circuit starts software execution
after this period (see system chapter). The POR is intended to force the circuit into a correct state at start-up. For
precise monitoring of the supply voltage, the voltage level detector (VLD) has to be used.
Symbol
TPOR
Parameter
POR reset duration
Vbat_sl
Supply ramp up
WDtime
Watchdog timeout period
Min
Typ
5
Max
Unit
20
ms
Comments
0.5
V/ms
1
2
s
2
Table 6. Electrical and timing specifications
Note: 1) The Vbat_sl defines the minimum slope required on VBAT. Correct start-up of the circuit is not guaranteed
if this slope is too slow. In such a case, a delay has to be built using the NRESET pin.
Note: 2) The minimal watchdog timeout period is guaranteed when the internal oscillators are used. In case an
external clock source is used, the watchdog timeout period will be correct in so far the contents of the
RegSysRCTrim1 and RegSysRCTrim2 registers are correct (see clock block documentation for more details).
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6-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
7. Clock Generation
7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
7.5.3
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.8
7.9
7.10
FEATURES ........................................................................................................................................... 7-2
OVERVIEW ........................................................................................................................................... 7-2
REGISTER MAP ..................................................................................................................................... 7-2
INTERRUPTS AND EVENTS MAP ............................................................................................................... 7-3
CLOCK SOURCES .................................................................................................................................. 7-5
RC oscillator Configuration................................................................................................................. 7-5
RC oscillator frequency tuning............................................................................................................ 7-5
RC oscillator specifications ................................................................................................................ 7-6
XTAL OSCILLATOR................................................................................................................................. 7-7
Xtal configuration ............................................................................................................................... 7-7
Xtal oscillator specifications................................................................................................................ 7-7
EXTERNAL CLOCK ................................................................................................................................. 7-8
External clock configuration ............................................................................................................... 7-8
External clock specification ................................................................................................................ 7-8
CLOCK SOURCE SELECTION ................................................................................................................... 7-8
PRESCALERS ....................................................................................................................................... 7-9
32 KHZ FREQUENCY SELECTOR ........................................................................................................... 7-10
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7-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
7.1
Features
3 available clock sources (RC oscillator, quartz oscillator and external clock).
• 2 divider chains: high-prescaler (8 bits) and low-prescaler (15 bits).
• CPU clock disabling in halt mode.
7.2
Overview
The XE88LCxx chips can work on different clock sources (RC oscillator, quartz oscillator and external clock). The
clock generator block is in charge of distributing the necessary clock frequencies to the circuit.
Figure 7-1 represents the functionality of the clock block.
The internal RC oscillator or an external clock source can be selected to drive the high prescaler. This prescaler
generates frequency divisions down to 1/256 of its input frequency. A 32kHz clock is generated by enabling the
quartz oscillator (if present in the product) or by selecting the appropriate tap on the high prescaler. The low
prescaler generates clock signals from 32kHz down to 1Hz. The clock source for the CPU can be selected from the
RC oscillator, the external clock or the 32kHz clock.
7.3
Register map
pos.
7
6
5
4
3
2
1
0
RegSysClock
CpuSel
EnExtClock
BiasRc
ColdXtal
EnableXtal
EnableRc
rw
r/w
r
r/w
r/w
r
r
r/w
r/w
reset
0 nresetsleep
0
0 nresetcold
1 nresetcold
1 nresetsleep
0
0 nresetsleep
1 nresetsleep
function
Select speed for cpuck
Unused
Enable for external clock
Enable Rcbias (reduces start-up time of RC).
Xtal in start phase
Unused
Enable Xtal oscillator
Enable RC oscillator
Table 7-1: RegSysClock register
pos.
7-2
1
0
RegSysMisc
-Output16k
OutputCpuCk
rw
r
r/w
r/w
reset
000000
0 nresetsleep
0 nresetsleep
function
Unused
Output 16 kHz signal on PB[3]
Output CPU clock on PB[2]
Table 7-2: RegSysMisc register
pos.
7-1
0
RegSysPre0
-ClearLowPrescal
rw
r
w1
r0
reset
0000000
0
function
Unused
Write 1 to reset low prescaler, but always
reads 0
Table 7-3: RegSysPre0 register
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7-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7-5
4
3
2
1
0
RegSysRcTrim1
-RcFreqRange
RcFreqCoarse[3]
RcFreqCoarse[2]
RcFreqCoarse[1]
RcFreqCoarse[0]
rw
r
r/w
r/w
r/w
r/w
r/w
reset
000
0 nresetcold
0 nresetcold
0 nresetcold
0 nresetcold
1 nresetcold
function
Unused
Low/high freq. range (low=0)
RC coarse trim bit 3
RC coarse trim bit 2
RC coarse trim bit 1
RC coarse trim bit 0
Table 7-4: RegSysRCTrim1 register
pos.
7-6
5
4
3
2
1
0
RegSysRcTrim2
-RcFreqFine[5]
RcFreqFine[4]
RcFreqFine[3]
RcFreqFine[2]
RcFreqFine[1]
RcFreqFine[0]
rw
r
r/w
r/w
r/w
r/w
r/w
r/w
reset
00
0 nresetcold
0 nresetcold
0 nresetcold
0 nresetcold
0 nresetcold
0 nresetcold
function
Unused
RC fine trim bit 5
RC fine trim bit 4
RC fine trim bit 3
RC fine trim bit 2
RC fine trim bit 1
RC fine trim bit 0
Table 7-5: RegSysRCTrim2 register
pos.
7-1
0
RegSysPtckmode
-Reserved
rw
r
r/w
reset
0000000
0 nresetglobal
function
Unused
Reserved
Table 7-6: RegSysPtckmode register
7.4
Interrupts and events map
interrupt source
ck128Hz
ck1Hz
Default mapping in the interrupt
manager
RegIrqHig(6)
Default mapping in the event
manager
RegEvn(5)
RegIrqMid(3)
RegEvn(1)
Table 7-7: Interrupts and events map
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7-3
Xtal
Ext
RC
by 2
div.
1
0
ckRCExt
En Ext Clock
high
© Semtech 2006
7-4
0
1
1
0
system clock
ck32kHz
Cpu
Sel
0
1
prescaler
low
EnableXtal and not(En Ext Clock)
RegSysRcTrim1&2
EnableRc or
En Ext Clock
prescaler
cpuck
ck1Hz
ck32kHz ...
ckRCExt/256
ckRCExt ...
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Figure 7-1. Clock block structure
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XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
7.5
7.5.1
Clock sources
RC oscillator Configuration
The RC oscillator is always turned on and selected for CPU and system operation at power-on reset, pad NRESET,
and when exiting sleep mode. It can be turned off after the Xtal (quartz oscillator) has been started, after selection
of the external clock or by entering sleep mode.
The RC oscillator has two frequency ranges: sub-MHz (50 kHz to 0.5 MHz) and above-MHz (0.5 MHz to 5 MHz).
Inside a range, the frequency can be tuned by software for coarse and fine adjustment. See registers
RegSysRcTrim1 and RegSysRcTrim2.
Bit EnableRc in register RegSysClock controls the propagation of the RC clock signal and the operation of the
oscillator. The user can stop the RC oscillator by resetting the bit EnableRc. Entering the sleep mode disables the
RC oscillator.
Note: The RC oscillator bias can be maintained while the oscillator is disabled by setting the bit BiasRc in
RegSysClock. This allows a faster restart of the RC oscillator at the cost of increased power consumption (see
section 7.5.3).
7.5.2
RC oscillator frequency tuning
The RC oscillator frequency can be set using the bits in the RegSysRcTrim1 and RegSysRcTrim2 registers.
Figure 7-2 shows the nominal frequency of the RC oscillator as a function of these bits. The absolute value of the
frequency for a given register content may change by ±35% from chip to chip due to the tolerances on the
integrated capacitors and resistors. However, the modification of the frequency as a function of a modification of
the register content is fairly precise. This means that the curves in Figure 7-2 can shift up and down but that the
slope remains unchanged.
The bit RcFreqRange modifies the oscillator frequency by a factor of 10. The upper curve in the figure corresponds
to RcFreqRange=1.
The RcFreqCoarse modifies the frequency of the oscillator by a factor (RcFreqCoarse+1). The figure represents
the frequency for 5 different values of the bits RcFreqCoarse: for each value the frequency is multiplied by 2.
Incrementing the RcFreqFine code, increases the frequency by about 1.4%.
The frequency of the oscillator is therefor given by:
fRC=fRcmin⋅(1+9⋅RcFreqRange)⋅(1+RcFreqCoarse)⋅(1.014)RcFreqFine
with fRcmin the RC oscillator frequency if the registers are all 0.
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7-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
1E+07
1
11
00
0
11
0
1
11
0
10
00
00
1
11
0
0
00
11
11
0
11
0
00
00
0
01
11
0
11
0
00
0
00
00
0
0
0
01
0
RcFreqFine(5:0)
0
0
0
10
0
00
11
11
0
00
11
11
0
00
0
10
00
0
00
0
00
Nominal RC oscillator frequency [Hz]
1
00
00
00
00
1
00
00
00
1
00
00
1
11
00
00
00
11
00
00
01
11
11
11
0
10
01
00
00
0
00
11
00
0
00
0
00
00
01
00
0
10
0
00
11
11
00
0
01
11
0
00
00
10
00
11
0
00
0
01
11
11
11
1E+05
11
00
11
10
11
11
00
10
01
11
0
11
10
11
0
11
0
10
RcFreqFine(5:0)
0
01
11
1E+06
00
01
1
11
RcFreqRange='1'
RcFreqRange='0'
00
RcFreqCoarse(3:0)
1E+04
0000
0001
0011
0111
1111
Figure 7-2. RC oscillator nominal frequency tuning.
7.5.3
RC oscillator specifications
sym
fRCmin
RcFreqFine
RC_su
description
Lowest RC frequency
fine tuning step
startup time
PSRR @ DC
Supply voltage
dependence
Temperature
dependence
∆f/∆T
min
25
typ
40
1.4
30
3
TBD
TBD
0.1
max
55
2.0
50
5
unit
kHz
%
us
us
%/V
%/V
%/°C
Comments
Note 1
BiasRc=0
BiasRc=1
Note 2
Note 3
Table 7-8. RC oscillator specifications
Note 1: this is the frequency tolerance when all trimming codes are 0. The frequency at start-up is about twice as
high.
Note 2: frequency shift as a function of VBAT with normal regulator function.
Note 3: frequency shift as a function of VBAT while the regulator is short-circuited to VBAT.
The tolerances on the minimal frequency and the drift with supply or temperature can be cancelled using the
software or hardware DFLL (digital frequency locked loop) which uses the crystal oscillator as a reference
frequency.
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7-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
7.6
Xtal oscillator
7.6.1
Xtal configuration
The Xtal operates with an external crystal of 32’768 Hz. During Xtal oscillator start-up, the first 32768 cycles are
masked. The two bits EnableXtal and ColdXtal in register RegSysClock control the oscillator.
At power-on reset, a pad NRESET pulse or during sleep mode, EnableXtal is reset and ColdXtal is set (Xtal
oscillator is not selected at start-up). The user can start Xtal oscillator by setting EnableXtal. When the Xtal
oscillator starts, bit ColdXtal is reset after 32768 cycles. Before ColdXtal is reset by the system, the Xtal frequency
precision is not guaranteed. The Xtal oscillator can be stopped by the user by resetting bit EnableXtal.
When the user enters into sleep mode, the Xtal is stopped.
7.6.2
Xtal oscillator specifications
The crystal oscillator has been designed for a crystal with the specifications given in Table 7-9. The oscillator
precision can only be guaranteed for this crystal.
Symbol
Fs
CL
Description
Resonance frequency
CL for nominal
frequency
Rm
Cm
C0
Rmp
Motional resistance
Motional capacitance
Shunt capacitance
Motional resistance of
6th overtone (parasitic)
Quality factor
Q
Min
Typ
32768
8.2
Max
1.8
0.7
4
40
2.5
1.1
8
100
3.2
2.0
kΩ
fF
pF
kΩ
30k
50k
400k
-
15
Unit
Hz
pF
Comments
Table 7-9. Crystal specifications.
For safe operation, low power consumption and to meet the specified precision, careful board layout is required:
Keep lines XIN and XOUT short and insert a VSS line in between them.
Connect the crystal package to VSS.
No noisy or digital lines near XIN or XOUT.
Insert guards where needed.
Respect the board specifications of Table 7-10.
Symbol
Rh_xin
Rh_xout
Rh_xin_xout
Cp_xin
Cp_xout
Cp_xin_xout
Description
Resistance XIN-VSS
Resistance XOUTVSS
Resistance XINXOUT
Capacitance XINVSS
Capacitance XOUTVSS
Capacitance XINXOUT
Min
10
10
Typ
Max
50
Unit
MΩ
MΩ
Comments
MΩ
0.5
3.0
pF
0.5
3.0
pF
0.2
1.0
pF
Table 7-10. Board layout specifications.
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7-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
The oscillator characteristics are given in Table 7-11. The characteristics are valid only if the crystal and board
layout meet the specifications above.
Symbol
fXtal
St_xtal
Fstab
Description
Nominal frequency
Start-up time
Frequency deviation
Min
Typ
32768
1
-100
Max
2
300
Unit
Hz
s
ppm
Comments
Note 1
Table 7-11. Crystal oscillator characteristics.
Note 1. This gives the relative frequency deviation from nominal for a crystal with CL=8.2pF and within the
temperature range -40°C to 85°C. The crystal tolerance, crystal aging and crystal temperature drift are not included
in this figure.
7.7
External clock
7.7.1
External clock configuration
The user can provide an external clock instead of the internal oscillators. The external provided frequency is
internally divided by two. The external clock input pin is XIN.
The system is configured for external clock by bit EnExtClock in register RegSysClock. Using the bits in the
registers RegSysRcTrim1 and RegSysRcTrim2, the ck32kHz clock frequency can be controlled (see section
7.10).
Note: when using the external clock, the Xtal is not available.
7.7.2
External clock specification
The external clock has to satisfy the specifications in the table below. Correct behavior of the circuit can not be
guaranteed if the external clock signal does not respect the specifications below.
Symbol
FEXT
PW_1
PW_0
FEXT_LV
PW_1_LV
PW_0_LV
Description
External clock
frequency
Pulse 1 width
Pulse 0 width
External clock
frequency
Pulse 1 width
Pulse 0 width
Min
Typ
0.06
0.03
TBD
TBD
Max
8
Unit
MHz
Comments
Note 1
20
TBD
µs
µs
kHz
Note 1
Note 1
Note 2
µs
µs
Note 2
Note 2
20
Table 7-12. External clock specifications.
Note 1. For VBAT≥2.4V
Note 2. For VBAT=VREG=1.2V
7.8
Clock source selection
There are three possible clock sources available for the CPU clock. The RC clock is always selected after powerup, a negative pulse on NRESET or after Sleep mode. The CPU clock selection is done with the bit CpuSel in
RegSysClock (0= fastest clock, 1= 32 kHz from Xtal if EnableXtal =1 and EnExtClock = 0 else from high
prescaler 32 kHz output).
Switching from one clock source to another is glitch free.
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7-8
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
The next table summarizes the different clock configurations of the circuit:
EnableRc
EnableXtal
Sleep
Xtal
RC
RC + Xtal
External
Clock targets
EnExtClock
Clock Sources
Mode
name
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Cpuck
CpuSel=0
CpuSel=1
off
Xtal
RCNOTE 2
RCNOTE 1 and 2
External NOTE
off
Xtal
High presc.
Xtal
High presc.
2
High
Prescaler
Clock
input
Low
Prescaler
Clock
input
off
off
RC
RCNOTE 1
External
off
Xtal
High presc.
Xtal
High presc.
Table 7-13: Table of clocking modes.
Note 1: The frequency of the RC must be higher than 100 kHz when Xtal is enabled in order to ensure a proper 32
kHz operation.
Note 2: The clock RC can be divided by the value of freq instruction (see coolrisc instruction information)
freq instruction
nodiv
div2
div4
div8
div16
cpuck
RC or external
RC/2 or external/2
RC/4 or external/4
RC/8 or external/8
RC/16 or external/16
Note 3: Switching from one clock source to another and stopping the unused clock source must be performed
using 2 MOVE instructions to RegSysClock. First select the new clock source and then stop the unused one.
7.9
Prescalers
The clock generator block embeds two divider chains: the high prescaler and the low one.
The high prescaler is made of an 8 stage dividing chain and the low prescaler of a 15 stage dividing chain.
Features:
• High prescaler can only be driven with RC clock or external clock (bits EnableRc or EnExtClock have to be
set, see Table 7-13).
• Low prescaler can be driven from the high prescaler or directly with the Xtal clock when bit EnableXtal is set to
1 and bit EnExtClock is set to 0.
• Bit ClearLowPrescal in the RegSysPre0 register allows to reset synchronously the low prescaler, the low
prescaler is also automatically cleared when bit EnableXtal is set. Both dividing chains are reset
asynchronously by the nresetglobal signal.
• Bit ColdXtal=1 indicates the Xtal is in its start phase. It is active for 32768 Xtal cycles after setting EnableXtal.
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7-9
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
7.10 32 kHz frequency selector
A decoder is used to select from the high prescaler, the frequency tap that is the closest to 32 kHz to operate the
low prescaler when the Xtal is not running. In this case, the RC oscillator frequency of ±35% will also be valid for
the low prescaler frequency outputs.
The next table shows how the RC trimming values in the RegSysRcTrim1 and RegSysRcTrim2 registers select
the 32 kHz frequency. The least significant bits of the RcFreqFine word are not used.
In order to ensure the correct frequency selection for the low prescaler when having an external clock, a proper
value must be set in the RC trim registers. The code can be selected from the table below as a function of the
frequency ratio between half the frequency of the external clock and 32kHz. If the frequency is not set correctly, all
timings derived from the low prescaler will be shifted accordingly (e.g. watchdog frequencies) and some peripherals
may no longer function correctly if the deviation from 32kHz is too large (e.g. the voltage level detector).
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7-10
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
RcFreqRange&RcFreqCoarse(3:0)&RcFreqFine(5:3)
Selected high prescaler tap
Default case (0’0001’000)
From 0’0000’000 to 0’0000’100
From 0’0000’101 to 0’0001’100
From 0’0001’101 to 0’0001’111
0’0010’000
From 0’0010’001 to 0’0010’110
0’0010’111
From 0’0011’000 to 0’0011’100
From 0’0011’101 to 0’0011’111
From 0’0100’000 to 0’1000’010
From 0’0100’011 to 0’0100’111
0’0101’000
From 0’0101’001 to 0’0101’110
0’0101’111
From 0’0110’000 to 0’0110’101
From 0’0110’110 to 0’0110’111
From 0’0111’000 to 0’0111’100
From 0’0111’101 to 0’0111’111
From 0’1000’000 to 0’1000’011
From 0’1000’100 to 0’1000’111
From 0’1001’000 to 0’1001’010
From 0’1001’011 to 0’1001’111
From 0’1010’000 to 0’1010’001
From 0’1010’010 to 0’1010’111
0’1011’000
From 0’1011’001 to 0’1011’110
0’1011’111
From 0’1100’000 to 0’1100’110
0’1100’111
From 0’1101’000 to 0’1101’101
From 0’1101’110 to 0’1101’111
From 0’1110’000 to 0’1110’100
From 0’1110’101 to 0’1110’111
From 0’1111’000 to 0’1111’100
From 0’1111’101 to 0’1111’111
From 1’0000’000 to 1’0000’010
From 1’0000’011 to 1’0001’010
From 1’0001’011 to 1’0010’100
From 1’0010’101 to 1’0010’111
From 1’0011’000 to 1’0011’010
From 1’0011’011 to 1’0011’111
1’0100’000
From 1’0100’001 to 1’0100’110
1’0100’111
From 1’0101’000 to 1’0101’100
From 1’0101’101 to 1’0101’111
From 10110’000 to 1’0110’011
From 1’0110’100 to 1’0110’111
From 1’0111’000 to 1’0111’010
From 1’0111’011 to 1’0111’111
From 1’1000’000 to 1’1000’001
From 1’1000’010 to 1’1000’111
1’1001’000
From 1’1001’001 to 1’1111’111
Ckrcext/2
Ckrcext
Ckrcext/2
Ckrcext/4
Ckrcext/2
Ckrcext/4
Ckrcext/8
Ckrcext/4
Ckrcext/8
Ckrcext/4
Ckrcext/8
Ckrcext/4
Ckrcext/8
Ckrcext/16
Ckrcext/8
Ckrcext/16
Ckrcext/8
Ckrcext/16
Ckrcext/8
Ckrcext/16
Ckrcext/8
Ckrcext/16
Ckrcext/8
Ckrcext/16
Ckrcext/8
Ckrcext/16
Ckrcext/32
Ckrcext/16
Ckrcext/32
Ckrcext/16
Ckrcext/32
Ckrcext/16
Ckrcext/32
Ckrcext/16
Ckrcext/32
Ckrcext/8
Ckrcext/16
Ckrcext/32
Ckrcext/64
Ckrcext/32
Ckrcext/64
Ckrcext/32
Ckrcext/64
Ckrcext/128
Ckrcext/64
Ckrcext/128
Ckrcext/64
Ckrcext/128
Ckrcext/64
Ckrcext/128
Ckrcext/64
Ckrcext/128
Ckrcext/64
Ckrcext/128
Table 7-14: Table of 32kHz high prescaler tap decoder.
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7-11
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
8. Interrupt Handler
8.1
8.2
8.3
8.4
8.5
FEATURES .............................................................................................................................8-2
OVERVIEW ............................................................................................................................8-2
REGISTER MAP ......................................................................................................................8-2
DETAILED DESCRIPTION ..........................................................................................................8-4
INTERRUPT HANDLING SOFTWARE............................................................................................8-5
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8-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
8.1
Features
The XE8000 chips support 24 interrupt sources, divided into 3 levels of priority.
8.2
Overview
The interrupt handler allows to manage 24 interrupt sources individually.
The 24 interrupt sources are divided into 3 levels of priority: High (8 interrupt sources), Mid (8 interrupt sources),
and Low (8 interrupt sources). Those 3 levels of priority are directly mapped to those supported by the CoolRisc
(IN0, IN1 and IN2; see CoolRisc documentation for more information).
Additional functions are given that allow fast detection of the highest priority interrupt that has been activated.
8.3
Register map
Register name
RegIrqHig
RegIrqMid
RegIrqLow
RegIrqEnHig
RegIrqEnMid
RegIrqEnLow
RegIrqPriority
RegIrqIrq
Table 8-1: IRQ handler registers
pos.
7
RegIrqHig
RegIrqHig[7]
6
RegIrqHig[6]
5
RegIrqHig[5]
4
RegIrqHig[4]
3
RegIrqHig[3]
2
RegIrqHig[2]
1
RegIrqHig[1]
0
RegIrqHig[0]
rw
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
reset
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
function
interrupt #23 (high priority)
clear interrupt #23 when 1 is written
interrupt #22 (high priority)
clear interrupt #22 when 1 is written
interrupt #21 (high priority)
clear interrupt #21 when 1 is written
interrupt #20 (high priority)
clear interrupt #20 when 1 is written
interrupt #19 (high priority)
clear interrupt #19 when 1 is written
interrupt #18 (high priority)
clear interrupt #18 when 1 is written
interrupt #17 (high priority)
clear interrupt #17 when 1 is written
interrupt #16 (high priority)
clear interrupt #16 when 1 is written
Table 8-2: RegIrqHig
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8-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7
RegIrqMid
RegIrqMid[7]
6
RegIrqMid[6]
5
RegIrqMid[5]
4
RegIrqMid[4]
3
RegIrqMid[3]
2
RegIrqMid[2]
1
RegIrqMid[1]
0
RegIrqMid[0]
rw
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
reset
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
function
interrupt #15 (mid priority)
clear interrupt #15 when 1 is written
interrupt #14 (mid priority)
clear interrupt #14 when 1 is written
interrupt #13 (mid priority)
clear interrupt #13 when 1 is written
interrupt #12 (mid priority)
clear interrupt #12 when 1 is written
interrupt #11 (mid priority)
clear interrupt #11 when 1 is written
interrupt #10 (mid priority)
clear interrupt #10 when 1 is written
interrupt #9 (mid priority)
clear interrupt #9 when 1 is written
interrupt #8 (mid priority)
clear interrupt #8 when 1 is written
Table 8-3: RegIrqMid
pos.
7
RegIrqLow
RegIrqLow[7]
6
RegIrqLow[6]
5
RegIrqLow[5]
4
RegIrqLow[4]
3
RegIrqLow[3]
2
RegIrqLow[2]
1
RegIrqLow[1]
0
RegIrqLow[0]
rw
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
reset
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
function
interrupt #7 (low priority)
clear interrupt #7 when 1 is written
interrupt #6 (low priority)
clear interrupt #6 when 1 is written
interrupt #5 (low priority)
clear interrupt #5 when 1 is written
interrupt #4 (low priority)
clear interrupt #4 when 1 is written
interrupt #3 (low priority)
clear interrupt #3 when 1 is written
interrupt #2 (low priority)
clear interrupt #2 when 1 is written
interrupt #1 (low priority)
clear interrupt #1 when 1 is written
interrupt #0 (low priority)
clear interrupt #0 when 1 is written
Table 8-4: RegIrqLow
pos.
7
6
5
4
3
2
1
0
RegIrqEnHig
RegIrqEnHig[7]
RegIrqEnHig[6]
RegIrqEnHig[5]
RegIrqEnHig[4]
RegIrqEnHig[3]
RegIrqEnHig[2]
RegIrqEnHig[1]
RegIrqEnHig[0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0
0
0
0
0
0
0
0
function
1= enable interrupt #23
1= enable interrupt #22
1= enable interrupt #21
1= enable interrupt #20
1= enable interrupt #19
1= enable interrupt #18
1= enable interrupt #17
1= enable interrupt #16
Table 8-5: RegIrqEnHig
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8-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7
6
5
4
3
2
1
0
RegIrqEnMid
RegIrqEnMid[7]
RegIrqEnMid[6]
RegIrqEnMid[5]
RegIrqEnMid[4]
RegIrqEnMid[3]
RegIrqEnMid[2]
RegIrqEnMid[1]
RegIrqEnMid[0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0
0
0
0
0
0
0
0
function
1= enable interrupt #15
1= enable interrupt #14
1= enable interrupt #13
1= enable interrupt #12
1= enable interrupt #11
1= enable interrupt #10
1= enable interrupt #9
1= enable interrupt #8
Table 8-6: RegIrqEnMid
pos.
7
6
5
4
3
2
1
0
RegIrqEnLow
RegIrqEnLow[7]
RegIrqEnLow[6]
RegIrqEnLow[5]
RegIrqEnLow[4]
RegIrqEnLow[3]
RegIrqEnLow[2]
RegIrqEnLow[1]
RegIrqEnLow[0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0
0
0
0
0
0
0
0
function
1= enable interrupt #7
1= enable interrupt #6
1= enable interrupt #5
1= enable interrupt #4
1= enable interrupt #3
1= enable interrupt #2
1= enable interrupt #1
1= enable interrupt #0
Table 8-7: RegIrqEnLow
pos.
7-0
RegIrqPriority
RegIrqPriority
rw
r
reset
11111111
function
code of highest priority set
Table 8-8: RegIrqPriority
pos.
7-3
2
1
0
RegIrqIrq
IrqHig
IrqMid
IrqLow
rw
r
r
r
r
reset
00000
0
0
0
function
unused
one or more high priority interrupts is set
one or more mid priority interrupts is set
one or more low priority interrupts is set
Table 8-9: RegIrqIrq
8.4
Detailed description
The CoolRISC core has 3 different interrupt levels IN0, IN1 and IN2 (Figure 8-1). When these interrupts are
triggered, the program counter (PC) is loaded with a fixed address. In case more than one interrupt occurs
simultaneously, the execution order is IN0, IN1, IN2.
The masking, setting and clearing of these interrupts can be done in the stat register (see chapter describing the
CPU).
The interrupt handler bundles a certain number of interrupt sources and routes them to one of these three
interrupts and provides the possibility to enable/disable each of them individually. The definition of the interrupt
sources is given in the memory mapping chapter.
RegIrqHig, RegIrqMid, and RegIrqLow are 8-bit registers containing flags for the interrupt sources. Those flags are
set when the interrupt is enabled (i.e. if the corresponding bit in the registers RegIrqEnHig, RegIrqEnMid or
RegIrqEnLow is set) and a rising edge is detected on the corresponding interrupt source.
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8-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Once memorized, an interrupt flag can be cleared by writing a ‘1’ in the corresponding bit of RegIrqHig, RegIrqMid
or RegIrqLow. Writing a ‘0’ does not modify the flag. To definitively clear the interrupt, one has to clear the
CoolRISC interrupt in the CoolRISC stat register. All interrupts are automatically cleared after a reset.
Two registers are provided to facilitate the writing of interrupt service software. RegIrqPriority contains the number
of the highest priority set (its value is 0xFF when no interrupt is memorized). RegIrqIrq indicates the priority level of
the currently activated interrupts.
stat
IE2
IE1
GIE
IN2
…
high priority
PC=h0003
medium priority
PC=h0001
low priority
PC=h0002
All interrupt sources are sampled by the highest frequency in the system. A CPU interruption is generated and
memorized when an interrupt becomes high. Between the rising edge of the interrupt on the peripheral and the
rising edge on the CoolRISC core, there is a latency of one clock cycle.
IN1
IN0
EV1
EV0
…
RegIrqLow RegIrqMid
7
6
5
4
3
2
1
0
RegIrqEnHig
7
6
5
4
3
2
1
0
interrupt sources
RegIrqHig
Figure 8-1. Principle of the interrupt handler.
8.5
Interrupt handling software
This chapter describes an example of the software used for the interrupt handler. This software is present by
default in the software development environments. It represents only one of several possible ways of handling the
interrupts.
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8-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
First of all, the jump addresses are defined at the beginning of the crt0.s file. In our case, all three interrupt levels
jump to the same place (defined by the _interrupt label), but this can be changed if required.
########################################################################
## Reset & interrupt vectors
########################################################################
_start:
jump main_init
; reset
jump _interrupt ; IN1
jump _interrupt ; IN2
jump _interrupt ; IN0
The first thing to do when an interrupt is activated is to save the context. You have to start with saving the contents
of the accumulator, then the flags and finally the internal CPU registers. You will find this part of the code in the
IRQComon_xx.s file.
_interrupt:
########################################################################
## Save all registers and flags
########################################################################
move
-(i3), a
move
a, r0
sflag
move
-(i3), a
move
-(i3), ipl
move
-(i3), iph
move
-(i3), i0l
move
-(i3), i0h
move
-(i3), i1l
move
-(i3), i1h
move
-(i3), i2l
move
-(i3), i2h
move
-(i3), r0
move
-(i3), r1
move
-(i3), r2
move
-(i3), r3
Next step is to determine which interrupt is activated. In this case, we use the value in the RegIrqPriority register
to determine the highest priority interrupt that was activated. Other ways can be used, especially when the priority
order fixed in the hardware needs to be changed. You will find this part of the code in the IRQComon_xx.s file. In
this example, the labels are used as defined for the XE8802.
########################################################################
## The following lines enables the adress calculation of the interrupt
## table. Where RegIrqPriority is the addres offset for the table.
## The RegIrqPriority valid values are between 0x00 until 0x017. The
## 0xFF value should never exist.
########################################################################
move r0,RegIrqPriority
calls _interrupttab
; save pc+1 in ip
_interrupttab:
add
ipl,#0x05
; add the offset, nb instr. before table
addc iph,#0x00
; propagate carry
add
ipl,r0
; add the offset of the regirqpriority
addc iph,#0x00
; propagate carry
rets
; put ip in pc
; interrupt table
jump ret_int
jump ret_int
jump Irq_Pa2
jump Irq_Pa3
jump Irq_CntD
jump Irq_CntB
jump Irq_Pa6
jump Irq_Pa7
jump Irq_Pa0
;
;
;
;
;
;
;
;
;
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
© Semtech 2006
=
=
=
=
=
=
=
=
=
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
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8-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
jump
jump
jump
jump
jump
jump
jump
jump
jump
jump
jump
jump
jump
jump
jump
Irq_Pa1
Irq_Vld
Irq_1Hz
Irq_Pa4
Irq_Pa5
Irq_UsrtCond1
Irq_UsrtCond2
Irq_UartRx
Irq_UartTx
Irq_Cmpd
Irq_CntC
Irq_CntA
Irq_Spi
Irq_128Hz
Irq_AC
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
RegIrqPriority
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
The next steps are to clear the interrupt flag in the interrupt handler, to call the specific function for the identified
interrupt source and to clear the interrupt in the stat register. This code can be found in the file IRQSave0_xx.s.
########################################################################
Irq_AC:
move RegIrqHig, #0x80
calls Handle_Irq_AC
jump ret_int0
########################################################################
Irq_128Hz:
move RegIrqHig, #0x40
calls Handle_Irq_128Hz
jump ret_int0
########################################################################
Irq_Spi:
move RegIrqHig, #0x20
calls Handle_Irq_Spi
jump ret_int0
…
ret_int0:
clrb stat, #2
jump ret_int
Finally, the context and the PC have to be restored. This code can be found in the IRQComon_xx.s file.
ret_int:
########################################################################
## Restore all registers and flags
########################################################################
move
r3, (i3)+
move
r2, (i3)+
move
r1, (i3)+
move
r0, (i3)+
move
i2h, (i3)+
move
i2l, (i3)+
move
i1h, (i3)+
move
i1l, (i3)+
move
i0h, (i3)+
move
i0l, (i3)+
move
iph, (i3)+
move
ipl, (i3)+
rflag
(i3)+
move
a, (i3)+
reti
########################################################################
## End of interrupt handlers
########################################################################
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8-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
9. Event Handler
9.1
9.2
9.3
9.4
FEATURES .............................................................................................................................9-2
OVERVIEW ............................................................................................................................9-2
REGISTER MAP ......................................................................................................................9-2
DETAILED DESCRIPTION ..........................................................................................................9-3
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9-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
9.1
Features
The XE8000 chips support 8 event sources, divided into 2 levels of priority.
9.2
Overview
An event is different from an interrupt in that it does not modify the program counter (PC). Events are used by two
microcontroller instructions.
First of all, events are useful to wake-up the microcontroller when it is in HALT. The software execution then simply
resumes at the instruction next to the HALT instruction. The second instruction is the conditional jump on event
(JEV). The jump is executed if one of the event flags in the stat register is set. In all other cases, the occurrence of
an event has no effect.
The event handler allows to manage 8 event sources individually. The 8 event sources are divided into 2 levels of
priority: High (4 event sources) and Low (4 event sources). Those 2 levels of priority are directly mapped to those
supported by the CoolRisc™ (EV0and IN1; see CoolRisc™ documentation for more information).
Additional functions are given that allow fast detection of the highest priority event that has been activated.
9.3
Register map
The addresses given in Table 9-1 are the default values and may be different in some products.
Register name
RegEvn
RegEvnEn
RegEvnPriority
RegEvnEvn
Table 9-1: EVN handler registers.
pos.
7
RegEvn
RegEvn[7]
6
RegEvn[6]
5
RegEvn[5]
4
RegEvn[4]
3
RegEvn[3]
2
RegEvn[2]
1
RegEvn[1]
0
RegEvn[0]
rw
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
reset
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
function
event #7 (high priority)
clear event #7 when written 1
event #6 (high priority)
clear event #6 when written 1
event #5 (high priority)
clear event #5 when written 1
event #4 (high priority)
clear event #4 when written 1
event #3 (low priority)
clear event #3 when written 1
event #2 (low priority)
clear event #2 when written 1
event #1 (low priority)
clear event #1 when written 1
event #0 (low priority)
clear event #0 when written 1
Table 9-2: RegEvn
9-2
D0405-134
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7
6
5
4
3
2
1
0
RegEvnEn
RegEvnEn[7]
RegEvnEn[6]
RegEvnEn[5]
RegEvnEn[4]
RegEvnEn[3]
RegEvnEn[2]
RegEvnEn[1]
RegEvnEn[0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
function
1= enable event #7
1= enable event #6
1= enable event #5
1= enable event #4
1= enable event #3
1= enable event #2
1= enable event #1
1= enable event #0
Table 9-3: RegEvnEn
pos.
7-0
RegEvnPriority
RegEvnPriority
rw
r
reset
11111111
nresetglobal
function
code of highest event set
FF if no event present.
Table 9-4: RegEvnPriority
pos.
7-2
1
RegEvnEvn
EvnHig
rw
r
r
reset
00000
0 nresetglobal
0
EvnLow
r
0 nresetglobal
function
unused
one or more high priority event is
set
one or more low priority event is
set
Table 9-5: RegEvnEvn
9.4
Detailed description
The CoolRISC core has 2 different event levels EV0 and EV1 (Figure 9-1).
The setting and clearing of these events can be done in the stat register (see chapter describing the CPU).
The event handler bundles a certain number of event sources and routes them to one of these two events and
provides the possibility to enable/disable each of them individually. The definition of the event sources is given in
the memory mapping chapter.
RegEvn is an 8-bit register containing flags for the event sources. Those flags are set when the event is enabled
(i.e. if the corresponding bit in the registers RegEvnEn is set) and a rising edge is detected on the corresponding
event source.
Once memorized, writing a ‘1’ in the corresponding bit of RegEvn clears an event flag. Writing a ‘0’ does not modify
the flag. All interrupts are automatically cleared after a reset.
Two registers are provided to facilitate the writing of event service software. RegEvnPriority contains the number
of the highest event set (its value is 0xFF when no event is memorized). RegEvnEvn indicates the priority level of
the current events.
All event sources are sampled by the highest frequency in the system. A CPU event is generated and memorized
when an event becomes high. The 8 event sources are divided into 2 levels of priority: High (4 event sources) and
Low (4 event sources). Those 2 levels of priority are directly mapped to those supported by the CoolRisc (EV0 and
EV1; see CoolRisc documentation for more information).
9-3
D0405-134
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
IE2
IE1
GIE
IN2
IN1
IN0
EV1
EV0
RegEvn
7
6
5
4
3
2
1
0
RegEvnEn
7
6
5
4
3
2
1
0
event sources
stat
Figure 9-1. Event handler principle.
9-4
D0405-134
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
10.
10.1
10.1.1
10.2
Low
Power RAM
FEATURES .......................................................................................................................................... 10-2
Overview.......................................................................................................................................... 10-2
REGISTER MAP ................................................................................................................................... 10-2
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10-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
10.1 Features
10.1.1
Overview
In order to save power consumption, 8 8-bit registers are provided in page 0. These memory locations should be
reserved for often-updated variables. As they are real registers and not RAM, power consumption is greatly
reduced.
10.2 Register map
pos.
7-0
7-0
7-0
7-0
7-0
7-0
7-0
7-0
Reg00
Reg00
Reg01
Reg02
Reg03
Reg04
Reg05
Reg06
Reg07
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0
0
0
0
0
0
0
0
function
low-power data memory
low-power data memory
low-power data memory
low-power data memory
low-power data memory
low-power data memory
low-power data memory
low-power data memory
Table 10-1: Low Power RAM
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10-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
11.
11.1
11.2
11.3
11.4
11.5
11.6
Port A
FEATURES .................................................................................................................................... 11-2
OVERVIEW .................................................................................................................................... 11-2
REGISTER MAP .............................................................................................................................. 11-3
INTERRUPTS AND EVENTS MAP........................................................................................................ 11-4
PORT A (PA) OPERATION .............................................................................................................. 11-4
PORT A ELECTRICAL SPECIFICATION ............................................................................................... 11-6
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11-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
11.1 Features
•
•
•
•
•
•
•
•
input port, 8 bits wide
each bit can be set individually for debounced or direct input
each bit can be set individually for pullup or not
snap-to-rail option for each input
each bit is an interrupt request source on the rising or falling edge
a system reset can be generated on an input pattern
PA[0] and PA[1] can generate two events for the CPU, individually maskable
PA[0] to PA[3] can be used as clock inputs for the counters/timers/PWM (product dependent)
11.2 Overview
PortA is a general purpose 8 bit wide digital input port, with interrupt capability. Figure 11-1 shows its structure.
Port A
VBat
8
logic
RegPASnapToRail
8
RegPAPullup
8
RegPADebounce
8x
debounce
8
0
RegPACtrl
8
8
1
RegPAIn
RegPAEdge
1
0
DebFast
(RegPACtrl(0))
1
8
events
8x
cntclocks
1kHz
32kHz
8
8
Vss
interrupts
0
RegPARes1
RegPARes0
1
11
10
01
0
resetfromporta
00
8x
Figure 11-1: structure of Port A
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11-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
11.3 Register map
There are eight registers in Port A (PA), namely RegPAIn, RegPADebounce, RegPAPullup, RegPAEdge,
RegPARes0, RegPARes1, RegPACtrl and RegPASnaptorail. Table 11-2 to Table 11-9 show the mapping of
control bits and functionality of these registers
register name
RegPAIn
RegPADebounce
RegPAEdge
RegPAPullup
RegPARes0
RegPARes1
RegPACtrl
RegPASnaptorail
Table 11-1: PA registers
pos.
7:0
RegPAIn
PAIn[7:0]
rw
r
reset
description
pad PA[7] to PA[0] input value
x
Table 11-2: RegPAIn
pos.
7:0
RegPADebounce
PADebounce[7:0]
rw
reset
description
rw
0 nresetpconf
PA[7] to PA[0]
1: debounce enabled
0: debounce disabled
Table 11-3: RegPADebounce
pos.
7:0
RegPAEdge
PAEdge[7:0]
rw
reset
rw
0 nresetglobal
description
PA[7] to PA[0] edge configuration
0: positive edge
1: negative edge
Table 11-4: RegPAEdge
pos.
7:0
RegPAPullup
PAPullup[7:0]
rw
reset
rw
1 nresetpconf
description
PA[7] to PA[0] pullup enable
0: pullup disabled
1: pullup enabled
Table 11-5: RegPAPullup
pos.
7:0
RegPARes0
PARes0[7:0]
rw
rw
reset
0 nresetglobal
description
PA[7] to PA[0] reset configuration
Table 11-6: RegPARes0
pos.
7:0
RegPARes1
PARes1[7:0]
rw
rw
reset
0 nresetglobal
description
PA[7] to PA[0] reset configuration
Table 11-7: RegPARes
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11-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7:1
0
RegPACtrl
[7:1]
DebFast
rw
r
rw
reset
0000000
0 nresetpconf
description
Unused
0 = slow debounce, 1 = fastdebounce
Table 11-8: RegPACtrl
pos.
7:0
RegPASnaptorail
PASnaptorail[7:0]
rw
rw
reset
0 nresetpconf
description
set snap-to-rail input on
Table 11-9: RegPASnaptorail
Note: Depending on the status of the EnResetPConf bit in RegSysCtrl, RegPAEdge, RegPADebounce and
RegPACtrl can be reset by any of the possible system resets or only with power-on reset and NRESET pad.
11.4 Interrupts and events map
Interrupt source
pa_irqbus[5]
pa_irqbus[4]
pa_irqbus[1]
pa_irqbus[0]
pa_irqbus[7]
pa_irqbus[6]
pa_irqbus[3]
pa_irqbus[2]
Default mapping in
the interrupt manager
RegIrqMid[5]
RegIrqMid[4]
RegIrqMid[1]
RegIrqMid[0]
RegIrqLow[7]
RegIrqLow[6]
RegIrqLow[3]
RegIrqLow[2]
Default mapping in the
event manager
RegEvn[4]
RegEvn[0]
11.5 Port A (PA) Operation
The Port A input status (debounced or not) can be read from RegPAin.
Debounce mode:
Each bit in Port A can be individually debounced by setting the corresponding bit in RegPADebounce. After reset,
the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted only if
height consecutive samples are identical. Selection of the clock is done by bit DebFast in Register RegPACtrl.
DebFast
Clock filter
0
1kHz
1
32kHz
Table 10: debounce frequency selection
Note: The tolerance on the debounce frequency depends on the selected clock source. When the external clock is
used, the pulse width will be correct if the input of the low prescaler is set to a frequency close to 32kHz (see clock
block documentation).
Pullups/Snap-to-rail:
Different functions are possible depending on the value of the registers RegPAPullup and RegPASnaptorail.
When the corresponding bit in RegPAPullup is set to 0, the inputs are floating (pullup and pulldown resistors are
disconnected). When the corresponding bit in RegPAPullup is 1 and in RegPASnaptorail is 0, a pullup resistor is
connected to the input pin. Finally, when the corresponding bit in RegPAPullup is 1 and in RegPASnaptorail is 1,
the snap-to-rail function is active.
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11-4
XE8802 Sensing Machine Data Acquisition MCU
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The snap-to-rail function connects a pullup or pulldown resistor to the input pin depending on the value forced on
the input pin. This function can be used for instance when the input port is connected to a tristate bus. When the
bus is floating, the pullup or pulldown maintains the bus in the last low impedance state before it became floating
until another low impedance output drives the bus. It also reduces the power consumption with respect to a classic
pullup since it selects the pullup or pulldown resistor so that it confirms the detected input state.
The state of input pin is summarized in the table below.
PAPullup[x]
PASnaptorail[x]
0
1
1
1
x
0
1
1
(last) externally
forced PA[x]
value
x
x
0
1
PA[x] pull
floating
pullup
pulldown
pullup
Table 11: Snap-to-rail
Port A starts up with the pullup resistor connected and the snap-to-rail function disabled.
Port A as an interrupt source:
Each Port A input is an interrupt request source and can be set on rising or falling edge with the corresponding bit
in RegPAEdge. After reset, the rising edge is selected for interrupt generation by default. The interrupt source can
be debounced by setting register RegPADebounce. The interrupt signals are sampled on the fastest clock in the
circuit. In order to guarantee that the circuit detects the interrupt, the minimal pulse length should be 1 cycle of this
clock.
Note: care must be taken when modifying RegPAEdge because this register performs an edge selection. The
change of this register may result in a transition, which may be interpreted as a valid interruption.
Port A as an event source:
The interrupt signals of the pins PA[0] and PA[1] are also available as events on the event controller.
Port A as a clock source (product dependent):
Images of the PA[0] to PA[3] input ports (debounced or not) are available as clock sources for the
counter/timer/PWM peripheral.
Port A as a reset source:
Port A can be used to generate a system reset by placing a predetermined word on Port A externally. The reset is
built using a logical and of the 8 PARes[x] signals:
resetfromportA = PAReset[7] AND PAReset[6] AND PAReset[5] AND ... AND PAReset[0]
PAReset[x] is itself a logical function of the corresponding pin PA[x]. One of four logical functions can be selected
for each pin by writing into two registers RegPARes0 and RegPARes1 as shown in Table 11-12.
PARes1[x]
0
0
1
1
PARes0[x]
0
1
0
1
PAReset[x]
0
PA[x]
not(PA[x])
1
Table 11-12: Selection bits for reset signal
A reset from Port A can be inhibited by placing a 0 on both PARes1[x] and PARes0[x] for at least 1 pin. Setting
both PARes1[x] and PARes0[x] to 1, makes the reset independent of the value on the corresponding pin. Setting
both registers to hFF, will reset the circuit independent from the Port A input value. This makes it possible to do a
reset by software.
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11-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Note: depending of the value of PA[0] to PA[7], changes to RegPARes0 and RegPARes1 can cause a reset.
Therefore it is safe to have always one (RegPARes0[x], RegPARes1[x]) equal to ‘00’ during the setting operations.
11.6 Port A electrical specification
sym
VINH
VINL
RPU
Cin
description
Input high voltage
Input low voltage
Pull-up resistance
Input capacitance
min
0.7*VBAT
VSS
20
typ
50
2.5
max
VBAT
0.2*VBAT
80
unit Comments
V
VBAT≥2.4V
V
VBAT≥2.4V
kΩ
pF
Note 1
Note 1: this value is indicative only since it depends on the package.
Table 11-13. Electrical specification
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11-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
12.
Port B
12.1
12.2
12.3
12.4
12.5
12.5.1
12.5.2
12.6
12.7
12.7.1
12.7.2
12.8
FEATURES ......................................................................................................................................... 12-2
OVERVIEW ......................................................................................................................................... 12-2
REGISTER MAP ................................................................................................................................... 12-2
PORT B CAPABILITIES ......................................................................................................................... 12-3
PORT B ANALOG CAPABILITY................................................................................................................ 12-3
Port B analog configuration .............................................................................................................. 12-3
Port B analog function specification ................................................................................................. 12-5
PORT B FUNCTION CAPABILITY ............................................................................................................. 12-5
PORT B DIGITAL CAPABILITIES .............................................................................................................. 12-6
Port B digital configuration ............................................................................................................... 12-6
Port B digital function specification................................................................................................... 12-7
LOW POWER COMPARATORS ............................................................................................................... 12-7
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2-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
12.1 Features
•
•
•
•
•
•
•
Input / output / analog port, 8 bits wide
Each bit can be set individually for input or output
Each bit can be set individually for open-drain or push-pull
Each bit can be set individually for pull-up or not (for input or open-drain mode)
In open-drain mode, pull-up is not active when corresponding pad is set to zero
The 8 pads can be connected individually to four internal analog lines (4 line analog bus)
Two internal freq. (16 kHz and cpuck) can be output on PB[2] and PB[3]
Product dependant:
• Two PWM signal can be output on pads PB[0] and PB[1]
• The synchronous serial interface (USRT) uses pads PB[5], PB[4]
• The UART interface uses pads PB[6] and PB[7] for Tx and Rx
12.2 Overview
Port B is a multi-purpose 8 bit Input/output port. In addition to digital behavior, all pins can be used for analog
signals. Each port terminal can be individually selected as digital input or output or as analog for sharing one of four
possible analog lines.
12.3 Register map
Table 12-1 shows the Port B registers.
register name
RegPBOut
RegPBIn
RegPBDir
RegPBOpen
RegPBPullup
RegPBAna
Table 12-1: Port B registers
pos.
7–0
RegPBOut
PBOut[7-0]
rw
rw
reset
0 nresetpconf
description in digital mode
Pad PB[7-0] output value
description in analog mode
Analog bus selection for pad PB[7-0]
Table 12-2: RegPBOut
RegPBIn
pos.
7–0
PBIn[7-0]
rw
rw
reset
X
description in digital mode
Pad PB[7-0] input status
description in analog mode
Unused
Table 12-3: RegPBIn
RegPBDir
pos.
7–0
PBDir [7-0]
rw
rw
reset
0 nresetpconf
description in digital mode
Pad PB[7-0] direction (0=input)
description in analog mode
Analog bus selection for pad PB[7-0]
Table 12-4: RegPBDir
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12-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7–0
RegPBOpen
PBOpen[7-0]
rw
rw
reset
description in digital mode
0 nresetpconf
Pad PB[7-0] open drain (1 = open
drain)
description in analog mode
Unused
Table 12-5: RegPBOpen
pos.
7 –0
RegPBPullup
PBPullup[7]
rw
rw
reset
description in digital mode
1 nresetpconf
Pull-up for pad PB[7-0] (1=active)
description in analog mode
Connect pad PB[7-0] on selected ana
bus
Table 12-6: RegPBPullup
pos.
7–0
RegPBAna
PBAna [7-0]
rw
rw
reset
description in digital mode
0 nresetpconf
Set PB[7-0] in analog mode
description in analog mode
Set PB[7-0] in analog mode
Table 12-7: RegPBAna
Note: Depending on the status of the EnResPConf bit in RegSysCtrl, the reset conditions of the registers are
different. See the reset block documentation for more details on the nresetpconf signal.
12.4 Port B capabilities
Port B
name
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
PB[0]
high
(analog)
analog
analog
analog
analog
analog
analog
analog
analog
utilization (priority)
medium
(functions)
uart Rx
uart Tx
usrt S1
usrt S0
16 kHz
clock CPU
PWM1 Counter C (C+D)
PWM0 Counter A (A+B)
low
(digital) (default)
I/O (with pull-up)
I/O (with pull-up)
I/O (with pull-up)
I/O (with pull-up)
I/O (with pull-up)
I/O (with pull-up)
I/O (with pull-up)
I/O (with pull-up)
Table 12-8: Different Port B functions
Table 12-8 shows the different usages that can be made of the port B with the order of priority. If a pin is selected
to be analog, it overwrites the function and digital set-up. If the pin is not selected as analog, but a function is
enabled, it overwrites the digital set-up. If neither the analog nor function is selected for a pin, it is used as an
ordinary digital I/O. This is the default configuration at start-up.
Note: the presence of the functions is product dependent.
12.5 Port B analog capability
12.5.1
Port B analog configuration
Port B terminals can be attached to a 4 line analog bus by setting the PBAna[x] bits to 1 in the RegPBAna
register.
The other registers then define the connection of these 4 analog lines to the different pads of Port B. These can be
used to implement a simple LCD driver or A/D converter. Analog switching is available only when the circuit is
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12-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
powered with sufficient voltage (see specification below). Below the specified supply voltage, only voltages that are
close to VSS or VBAT can be switched.
When PBAna[x] is set to 1, one pad of the Port B terminals is changed from digital I/O mode to analog. The usage
of the registers RegPBPullup, RegPBOut and RegPBDir define the analog configuration (see Table 12-9).
When PBAna[x] = 1, then PBPullup[x] connects the pin to the analog bus. PBDir[x] and PBPOut[x] select which
of the 4 analog lines is used.
analog bus selection
PBDir[x]
0
0
1
1
X
PBPullup[x]
PB[x] selection on
1
1
1
1
0
analog line 0
analog line 1
analog line 2
analog line 3
High impedance
PBout[x]
0
1
0
1
X
Table 12-9: Selection of the analog lines with RegPBDir, RegPBout and RegPBPullup when PBAna[x] = 1
Example:
Set the pads PB[2] and PB[5] on the analog line 3. (the values X depend on the configuration of others
pads)
• apply high impedance in the analog mode (move RegPBPullup,#0bXX0XX0XX)
• go to analog mode (move RegPBAna,#0bXX1XX1XX)
• select the analog line3 (move RegPBDir,#0bXX1XX1XX and move RegPBOut,#0bXX1XX1XX)
• apply the analog line to the output (move RegPBPullup,#0bXX1XX1XX)
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12-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
12.5.2
Port B analog function specification
The table below defines the on-resistance of the switches between the pin and the analog bus for different
conditions. The series resistance between 2 pins of Port B connected to the same analog line is twice the
resistance given in the table.
sym
Ron
Ron
Cin
Cin
description
switch resistance
switch resistance
input capacitance (off)
input capacitance (on)
min
typ
3.5
4.5
max
11
15
unit
kΩ
kΩ
pF
pF
Comments
Note 1
Note 2
Note 3
Note 4
Table 12-10. Analog input specifications.
Note 1: This is the series resistance between the pad and the analog line in 2 cases
1. VBAT ≥ 2.4V and the VMULT peripheral is present on the circuit and enabled.
2. VBAT ≥ 3.0V and the VMULT peripheral is not present on the circuit.
Note 2: This is the series resistance in case VBAT ≥ 2.8V and the peripheral VMULT is not present on the circuit.
Note 3: This is the input capacitance seen on the pin when the pin is not connected to an analog line. This value is
indicative only since it is product and package dependent.
Note 4: This is the input capacitance seen on the pin when the pin is connected to an analog line and no other pin
is connected to the same analog line. This value is indicative only since it is product and package dependent.
12.6 Port B function capability
The Port B can be used for different functions implemented by other peripherals. The description below is
applicable only in so far the circuit contains these peripherals.
When the counters are used to implement a PWM function (see the documentation of the counters), the PB[0] and
PB[1] terminals are used as outputs (PB[0] is used if CntPWM0 in RegCntConfig1 is set to 1, PB[1] is used if
CntPWM1 in RegCntConfig1 is set to 1) and the PWM generated values override the values written in RegPBout.
However, PBDir(0) and PBDir(1) are not automatically overwritten and have to be set to 1.
If Output16k is set in RegSysMisc, the frequency is output on PB[3]. This overrides the value contained in
PBOut(3). However, PBDir(3) must be set to 1. The frequency and duty cycle of the clock signal are given in
Figure 12-1. fmax is the frequency of fastest clock present in the circuit.
1/fmax
1/16k
Figure 12-1. 16 kHz output clock timing
Similarly, if OutputCkCpu is set in RegSysMisc, the CPU frequency is output on PB[2]. This overrides the value
contained in PBOut(2). However, PBDir(2) must be set to 1.
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12-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
1/f1
1/f2
Figure 12-2. CPU output clock timing.
The timing of the CPU clock (Figure 12-2) depends on the selection of the CpuSel bit in the RegSysClock register
and is given in Table 12-11. fmax is the frequency of fastest clock present in the circuit. Note that the tolerance on
the 32 kHz depends on the selected clock source (see clock block documentation).
CpuSel
0
1
f1
fmax/4
fmax
f2
fmax
32 kHz
Table 12-11. CPU clock timing parameters.
Pins PB[5] and PB[4] can be used for S1 and S0 of the USRT (see USRT documentation) when the UsrtEnable bit
is set in RegUsrtCtrl. The PB[5] and PB[4] then become open-drain. This overrides the values contained in
PBOpen(5:4), PBOut(5:4) and PBDir(5:4). If there is no external pull-up resistor on these pins, internal pull-ups
should be selected by setting PBPullup(5:4). When S0 is an output, the pin PB[4] takes the value of UsrtS0 in
RegUsrtS0. When S1 is an output, the pin PB[5] takes the value of UsrtS1 in RegUsrtS1.
Pins PB[6] and PB[7] can be used by the UART (see UART documentation). When UartEnTx in RegUartCtrl is set
to 1, PB[6] is used as output signal Tx. When UartEnRx in RegUartCtrl is set to 1, PB[7] is used as input signal
Rx. This overrides the values contained in PBOut(7:6) and PBDir(7:6).
12.7 Port B digital capabilities
12.7.1
Port B digital configuration
The direction of each bit within Port B (input only or input/output) can be individually set using the RegPBDir
register. If PBDir[x] = 1, both the input and output buffer are active on the corresponding Port B. If PBDir[x] = 0,
the corresponding Port B pin is an input only and the output buffer is in high impedance. After reset (nresetpconf)
Port B is in input only mode (PBDir[x] are reset to 0).
The input values of Port B are available in RegPBIn (read only). Reading is always direct - there is no debounce
function in Port B. In case of possible noise on input signals, a software debouncer with polling or an external
hardware filter have to be realized. The input buffer is also active when the port is defined as output and the
effective value on the pin can be read back.
Data stored in RegPBOut are outputted at Port B if PBDir[x] is 1. The default values after reset is low (0).
When a pin is in output mode (PBDir[x] is set to 1), the output can be a conventional CMOS (Push-Pull) or a Nchannel Open-drain, driving the output only low. By default, after reset (nresetpconf) the PBOpen[x] in
RegPBOpen is cleared to 0 (push-pull). If PBOpen[x] in RegPBOpen is set to 1 then the internal P transistor in
the output buffer is electrically removed and the output can only be driven low (PBOut[x]=0). When PBOut[x]=1,
the pin is high Impedance. The internal pull-up or an external pull-up resistor can be used to drive to pin high.
Note: Because the P transistor actually exists (this is not a real Open-drain output) the pull-up range is limited to
VDD + 0.2V (avoid forward bias the P transistor / diode).
Each bit can be set individually for pull-up or not using register RegPBPullup. Input is pulled up when its
corresponding bit in this register is set to 1. Default status after (nresetpconf) is 1, which means with pull up. To
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12-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
limit power consumption, pull-up resistors are only enabled when the associated pin is either a digital input or an Nchannel open-drain output with the pad set to 1. In the other cases (push-pull output or open-drain output driven
low), the pull up resistors are disabled independent of the value in RegPBPullup.
After power-on reset, the Port B is configured as an input port with pull-up. During power-on reset (see reset block
documentation) however, the pin PB[1] is pulled down in stead of pulled up. Once the power-on reset completed,
the pin PB[1] is pulled up, exactly as the other Port B pins.
The input buffer is always active, except in analog mode. This means that the Port B input should be a valid digital
value at all times unless the pin is set in analog mode. Violating this rule may lead to high power consumption.
12.7.2
sym
VINH
VINL
VOH
Port B digital function specification
description
Input high voltage
Input low voltage
Output high voltage
min
0.7*VBAT
VSS
VBAT-0.4
VOL
Output low voltage
VSS
RPU
Cin
Pull-up resistance
Input capacitance
20
typ
max
VBAT
0.2*VBAT
VBAT
VSS+0.4
50
3.5
80
unit Comments
V
VBAT≥2.4V
V
VBAT≥2.4V
V
VBAT=1.2V, IOH =0.3mA
VBAT=2.4V, IOH =5.0mA
VBAT=4.5V, IOH =8.0mA
V
VBAT=1.2V, IOL =0.3mA
VBAT=2.4V, IOL
=12.0mA
VBAT=4.5V, IOL
=15.0mA
kΩ
pF
Note 1
Note 1: this value is indicative only since it depends on the package.
12.8 Low power comparators
If the low power comparator (CMPD) peripheral is present in the circuit, the signals on the pins PB[7:4] can be used
as inputs for these low power comparators. Although the comparators are functional independent of the Port B
configuration, it is recommended to set the pins that are used for the CMPD in analog mode without selecting any
analog lines. This is to avoid high power consumption in the digital input buffer when analog or slowly varying
digital signals are applied.
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12-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
13.
Port D
13.1
Features
13-2
13.2
Overview
13-2
13.3
Register map
13-2
13.4
Port D (PD) Operation
13-4
13.5
Port D electrical specification
13-5
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13-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
13.1 Features
ƒ
ƒ
ƒ
ƒ
input / output port, 8 bits wide
each bit can be set individually for input or output
pull-ups are available in input mode
snap-to-rail option in input mode
13.2 Overview
Port D (PD) is a general purpose 8 bit input/output digital port.
Figure 13-1 shows its structure.
VBat
4
RegPDPullup[7:4]
4
logic
RegPDPullup[3:0]
8
RegPDIn
8
RegPDOut
8
RegPDDir
Vss
Figure 13-1 : structure of PortD
13.3 Register map
There are four registers in the Port D (PD), namely RegPDIn, RegPDOut, RegPDDir and RegPDPullup. Table 133 to Table 13-6 show the mapping of control bits and functionality of these registers.
register name
RegPDIn
RegPDOut
RegPDDir
RegPDPullup
Table 13-1 : PD registers
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13-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Pos.
7:0
RegPDIn
PDIn[7:0]
Rw
r
Reset
-
Description
pad PD[7:0] input value
Table 13-2 : RegPDIn
Pos.
7:0
RegPDOut
PDOut[7:0]
Rw
rw
Reset
0 nresetpconf
Description
pad PD[7:0] output value
Table 13-3 : RegPDOut
Pos.
7:0
RegPDDir
PDDir[7:0]
Rw
rw
Reset
0 nresetpconf
Description
pad PD[7:0] direction
(0=input)
Table 13-4 : RegPDDir
Pos.
7
RegPDPullup
PDSnapToRail[3]
Rw
rw
Reset
1 nresetpconf
6
PDSnapToRail[2]
rw
1 nresetpconf
5
PDSnapToRail[1]
rw
1 nresetpconf
4
PDSnapToRail[0]
rw
1 nresetpconf
3
PDPullup[3]
rw
1 nresetpconf
2
PDPullup[2]
rw
1 nresetpconf
1
PDPullup[1]
rw
1 nresetpconf
0
PDPullup[0]
rw
1 nresetpconf
Description
snap-to-rail for pad PD[7]
and PD[6] (1=active)
snap-to-rail for pad PD[5]
and PD[4] (1=active)
snap-to-rail for pad PD[3]
and PD[2] (1=active)
snap-to-rail for pad PD[1]
and PD[0] (1=active)
pullup for pad PD[7] and
PD[6] (1=active)
pullup for pad PD[5] and
PD[4] (1=active)
pullup for pad PD[3] and
PD[2] (1=active)
pullup for pad PD[1] and
PD[0] (1=active)
Table 13-5 : RegPDPullup
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13-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
13.4 Port D (PD) Operation
The direction of each pin of Port D (input or input/output) can be individually set by using the RegPDDir register. If
PDDir[x] = 1, the output buffer on the corresponding Port D pin is enabled. After reset, Port D is in input only mode
(PDDir[x] are reset to 0). The input buffer is always enabled independently from the RegPDDir contents.
Output data:
Data are stored in RegPDOut prior to output at Port D.
Input data:
The status of Port D is available in RegPDIn (read only). Reading is always direct - there is no digital debounce
function associated with Port D. In case of possible noise on input signals, a software debouncer or an external
filter must be realised.
Pull-up/Snap to Rail:
When configured as an input (PDDir[x]=0), pull-ups are available on every pin. The pull-up function of the pins is
controlled two by two by the PDPullup and PDSnapToRail bits in the register RegPDPullup. When a bit
PDPullup[x] is 0, the pull-ups on the pins PD[2x] and PD[2x+1] are disabled. When a bit PDPullup[x] is set to 1
and the bit PDSnapToRail[x] is set to 0, the pull-up resistor is connected to the pins PD[2x] and PD[2x+1]. When
both PDPullup[x] and PDSnapToRail[x] are 1, the snap-to-rail function is active on the pins PD[2x] and PD[2x+1].
The snap-to-rail function connects a pullup or pulldown resistor to the input pin depending on the value forced on
the input pin. This function can be used for instance when the input port is connected to a tristate bus. When the
bus is floating, the pullup or pulldown maintains the bus in the last low impedance state before it became floating
until another low impedance output is driving the bus. It also reduces the power consumption with respect to a
classic pullup since it selects the pullup or pulldown resistor so that it confirms the detected input state.
The function is summarised in the table below as a function of the different register settings.
PDDir[2x(+1)]
PDPullup[x]
PDSnapToRail[x]
1
0
0
0
0
x
0
1
1
1
x
x
0
1
1
(last) externally
forced
PD[2x(+1)] value
x
x
x
0
1
PD[2x(+1)] pull
resistor
not connected
not connected
pullup
pulldown
pullup
Table 13-6: Snap-to-rail and pullup function
At power-on reset, Port D is configured as an input port with all pull-ups active.
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13-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
13.5 Port D electrical specification
sym
VINH
VINL
VOH
description
Input high voltage
Input low voltage
Output high voltage
min
0.7*VBAT
VSS
VBAT-0.4
VOL
Output low voltage
VSS
RPU
Cin
Pull-up resistance
Input capacitance
20
typ
max
VBAT
0.2*VBAT
VBAT
VSS+0.4
50
3.0
80
unit Comments
V
VBAT≥2.4V
V
VBAT≥2.4V
V
VBAT=1.2V, IOH =0.3mA
VBAT=2.4V, IOH =5.0mA
VBAT=4.5V, IOH =8.0mA
V
VBAT=1.2V, IOL =0.3mA
VBAT=2.4V, IOL
=12.0mA
VBAT=4.5V, IOL
=15.0mA
kΩ
pF
Note 1
Note 1: this value is indicative only since it depends on the package.
Table 13-7. Port D electrical specification
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13-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
14.
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.8.1
14.8.2
14.8.3
14.8.4
14.9
Universal Asynchronous Receiver/Transmitter (UART)
FEATURES .................................................................................................................................... 14-2
OVERVIEW .................................................................................................................................... 14-2
REGISTERS MAP............................................................................................................................ 14-2
INTERRUPTS MAP .......................................................................................................................... 14-3
UART BAUD RATE SELECTION ......................................................................................................... 14-3
UART ON THE RC OSCILLATOR OR EXTERNAL CLOCK SOURCE ........................................................... 14-3
UART ON THE CRYSTAL OSCILLATOR ............................................................................................... 14-4
FUNCTION DESCRIPTION ................................................................................................................ 14-5
Configuration bits........................................................................................................................ 14-5
Transmission .............................................................................................................................. 14-5
Reception ................................................................................................................................... 14-6
Interrupt or polling....................................................................................................................... 14-7
SOFTWARE HINTS.......................................................................................................................... 14-7
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14-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
14.1 Features
• Full duplex operation with buffered receiver and transmitter.
• Internal baudrate generator with 10 programmable baudrates (300 - 153600).
• 7 or 8 bits word length.
• Even, odd, or no-parity bit generation and detection
• 1 stop bit
• Error receive detection: Start, Parity, Frame and Overrun
• Receiver echo mode
• 2 interrupts (receive full and transmit empty)
• Enable receive and/or transmit
• Invert pad Rx and/or Tx
14.2 Overview
The Uart pins are PB[7], which is used as Rx - receive and PB[6] as Tx - transmit.
14.3 Registers map
register name
RegUartCtrl
RegUartCmd
RegUartTx
RegUartTxSta
RegUartRx
RegUartRxSta
Table 14-1: Uart registers
pos.
7
6
5-3
2
1
0
RegUartCmd
SelXtal
UartRcSel(2:0)
UartPM
UartPE
UartWL
rw
r/w
r
r/w
r/w
r/w
r/w
reset
0 nresetglobal
0
000 nresetglobal
0 nresetglobal
0 nresetglobal
1 nresetglobal
description
Select input clock: 0 = RC/external, 1 = xtal
Unused
RC prescaler selection
Select parity mode: 1 = odd, 0 = even
Enable parity: 1 = with parity, 0 = no parity
Select word length: 1 = 8 bits, 0 = 7 bits
Table 14-2: RegUartCmd
pos.
7
RegUartCtrl
UartEcho
rw
r/w
reset
0 nresetglobal
6
5
4
3
2-0
UartEnRx
UartEnTx
UartXRx
UartXTx
UartBR(2:0)
r/w
r/w
r/w
r/w
r/w
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
101 nresetglobal
description
Enable echo mode:
1 = echo Rx->Tx, 0 = no echo
Enable uart reception
Enable uart transmission
Invert pad Rx
Invert pad Tx
Select baud rate
Table 14-3: RegUartCtrl
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14-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7-0
RegUartTx
UartTx
rw
r/w
reset
00000000
nresetglobal
description
Data to be send
Table 14-4: RegUartTx
pos.
7-2
1
0
RegUartTxSta
UartTxBusy
UartTxFull
rw
r
r
r
reset
000000
0 nresetglobal
0 nresetglobal
description
Unused
Uart busy transmitting
RegUartTx full
Set by writing to RegUartTx
Cleared when transferring RegUartTx into
internal shift register
Table 14-5: RegUartTxSta
pos.
7-0
RegUartRx
UartRx
rw
r
reset
00000000
nresetglobal
description
Received data
Table 14-6: RegUartRx
pos.
7-6
5
4
3
2
RegUartRxSta
UartRxSErr
UartRxPErr
UartRxFErr
UartRxOErr
rw
r
r
r
r
r/c
reset
00
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
1
0
UartRxBusy
UartRxFull
r
r
0 nresetglobal
0 nresetglobal
description
Unused
Start error
Parity error
Frame error
Overrun error
Cleared by writing RegUartRxSta
Uart busy receiving
RegUartRx full
Cleared by reading RegUartRx
Table 14-7: RegUartRxSta
14.4 Interrupts map
interrupt source
Irq_uart_Tx
Irq_uart_Rx
default mapping in the interrupt manager
IrqHig(1)
IrqHig(0)
Table 14-8: Interrupts map
14.5 Uart baud rate selection
In order to have correct baud rates, the Uart interface has to be fed with a stable and trimmed clock source. The
clock source can be an external clock source, the RC oscillator or the crystal oscillator. The precision of the baud
rate will depend on the precision of the selected clock source.
14.6 Uart on the RC oscillator or external clock source
To select the external clock or RC oscillator for the Uart, the bit SelXtal in RegUartCmd has to be 0. The choice
between the RC oscillator and the external clock source is made with the bit EnExtClock in RegSysClock.
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14-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
In order to obtain a correct baud rate, the RC oscillator or external clock frequency have to be set to one of the
frequencies given in the table below. The precision of the obtained baud rate is directly proportional to the
frequency deviation of the used clock source with respect to the values in the table below.
Frequency selection for correct Uart baud rates
RC oscillator (Hz)
External clock (Hz)
2’457’600
4’915’200
1’228’800
2’457’600
614’400
1’228’800
307’200
614’400
153’600
307’200
76’800
153’600
Table 14-9a
For each of these frequencies, the baud rate can be selected with the bits UartBR(2:0) in RegUartCtrl and
UartRcSel(2:0) in RegUartCmd as shown in Table 14-9.
RC frequency (Hz)
External clock freq. (Hz)
UartRcSel
UartBR
000
111
110
101
100
011
010
001
000
010
001
000
2457600
4915200
1228800
2457600
614400
1228800
307200
614400
153600
307200
76800
153600
153600
76800
38400
19200
9600
4800
2400
1200
600
300
76800
38400
19200
9600
4800
2400
1200
600
300
-
38400
19200
9600
4800
2400
1200
600
300
-
19200
9600
4800
2400
1200
600
300
-
9600
4800
2400
1200
600
300
-
4800
2400
1200
600
300
-
Table 14-9: Uart baud rate with RC clock or external clock
Note 1 : Although not documented here, the coding of the baud rate used in the circuits XE8801, XE8803 and
XE8805 can also be used.
Note 2 : The precision of the baud rate is directly proportional to the frequency deviation of the used clock from the
ideal frequency given in the table. In order to increase the precision and stability of the RC oscillator, the DFLL
(digital frequency locked loop) can be used with the crystal oscillator as a reference.
14.7 Uart on the crystal oscillator
In order to use the crystal oscillator as the clock source for the Uart, the bit SelXtal in RegUartCmd has to be set.
The crystal oscillator has to be enabled by setting the EnableXtal bit in RegSysClock. The baud rate selection is
done using the UartBR bits as shown in Table 14-10.
Xtal freq. (Hz)
UartBR
011
010
001
000
32768
2400
1200
600
300
Table 14-10: Uart baud rate with Xtal clock
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14-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Due to the odd ratio between the crystal oscillator frequency and the baud rate, the generated baud rate has a
systematic error of –2.48%.
14.8 Function description
14.8.1
Configuration bits
The configuration bits of the Uart serial interface can be found in the registers RegUartCmd and RegUartCtrl.
The bit SelXtal is used to select the clock source (see chapter 14.5). The bits UartSelRc and UartBR select the
baud rate (see chapter 14.5).
The bits UartEnRx and UartEnTx are used to enable or disable the reception and transmission.
The word length (7 or 8 data bits) can be chosen with UartWL. A parity bit is added during transmission or checked
during reception if UartPE is set. The parity mode (odd or even) can be chosen with UartPM.
Setting the bits UartXRx and UartXTx inverts the Rx respectively Tx signals.
The bit UartEcho is used to send the received data automatically back. The transmission function becomes then:
Tx = Rx XOR UartXRx XOR UartXTx.
14.8.2
Transmission
In order to send data, the transmitter has to be enabled by setting the bit UartEnTx. Data to be sent have to be
written to the register RegUartTx. The bit UartTxFull in RegUartTxSta then goes to 1, indicating to the transmitter
that a new word is available. As soon as the transmitter has finished sending the previous word, it then loads the
contents of the register RegUartTx to an internal shift register and clears the UartTxFull bit. An interrupt is
generated on Irq_uart_Tx at the falling edge of the UartTxFull bit. The bit UartTxBusy in RegUartTxSta shows
that the transmitter is busy transmitting a word.
A timing diagram is shown in Figure 14-1. Data is sent LSB first.
New data should be written to the register RegUartTx only while UartTxBusy is 0, otherwise data will be lost.
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14-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Asynchronous Transmission
write to RegUartTx
word 1
RegUartTx
reguarttx_shift
word 1
shift clock
Tx
start
b0
b1
b6/7
parity
stop
UartTxBusy
UartTxFull
Irq_uart_Tx
Asynchronous Transmission (back to back)
word 1
word 2
write to RegUartTx
RegUartTx
reguarttx_shift
word 1
word 2
word 1
word 2
shift clock
Tx
start
b0
b6/7
stop
start
UartTxBusy
UartTxFull
Irq_uart_Tx
Figure 14-1. Uart transmission timing diagram.
14.8.3
Reception
On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data are
transferred from the internal shift register to the register RegUartRx. At the same time, the UartRxFull bit is set
and an interrupt is generated on Irq_uart_Rx. This indicates that new data is available in RegUartRx. The timing
diagram is shown in Figure 14-2.
The UartRxFull bit is cleared when RegUartRx is read. If the register was not read before the receiver transfers a
new word to it, the bit UartRxOErr (overflow error) is set and the previous contents of the register are lost.
UartRxOErr is cleared by writing any data to RegUartRxSta.
The bit UartRxSErr is set if a start error has been detected. The bit is updated at data transfer to RegUartRx.
The bit UartRxPErr is set if a parity error has been detected, i.e. the received parity bit is not equal to the
calculated parity of the received data. The bit is updated at data transfer to RegUartRx.
The bit UartRxFErr in RegUartRxSta shows that a frame error has been detected. No stop bit has been detected.
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14-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Asynchronous Reception
read of RegUartRx (software)
reguartrx_shift
word 1
word 1
RegUartRx
shift clock
Rx
start
b0
b6/7
parity
stop
UartRxBusy
UartRxFull
Irq_uart_Rx
Figure 14-2. Uart reception timing diagram.
14.8.4
Interrupt or polling
The transmission and reception software can be driven by interruption or by polling the status bits.
Interrupt driven reception: each time an Irq_uart_Rx interrupt is generated, a new word is available in RegUartRx.
The register has to be read before a new word is received.
Interrupt driven transmission: each time the contents of RegUartTx is transferred to the transmission shift register,
an Irq_uart_Tx interrupt is generated. A new word can then be written to RegUartTx.
Reception driven by polling: the UartRxFull bit is to be read and checked. When it is 1, the RegUartRx register
contains new data and has to be read before a new word is received.
Transmission driven by polling: the UartTxFull bit is to read and checked. When it is 0, the RegUartTx register is
empty and a new word can be written to it.
14.9 Software hints
Example of program for a transmission with polling:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart transmission).
2. Write a byte to RegUartTx.
3. Wait untill the UartTxFull bit in RegUartTxSta register equals 0.
4. Jump to 2 to writing the next byte if the message is not finished.
5. End of transmission.
Example of program for a transmission with interrupt:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart transmission).
2. Write a byte to RegUartTx.
3. After an interrupt and if the message is not finished, jump to 2
4. End of transmission.
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14-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Example of program for a reception with polling:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart reception).
2. Wait until the UartRxFull bit in the RegUartRxSta register equals 1.
3. Read the RegUartRxSta and check if there is no error.
4. Read data in RegUartRx.
5. If data is not equal to End-Of-Line, then jump to 2.
6. End of reception.
Example of program for a reception with interrupt:
1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd
parity, 9600 baud, enable Uart reception).
2. When there is an interrupt, jump to 3
3. Read RegUartRxSta and check if there is no error.
4. Read data in RegUartRx.
5. If data is not equal to End-Of-Line, then jump to 2.
6. End of reception.
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14-8
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
15.
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Universal Synchronous Receiver/Transmitter (URST)
FEATURES ........................................................................................................................................... 15-2
OVERVIEW ........................................................................................................................................... 15-2
REGISTER MAP ..................................................................................................................................... 15-2
INTERRUPTS MAP.................................................................................................................................. 15-4
CONDITIONAL EDGE DETECTION 1 .......................................................................................................... 15-4
CONDITIONAL EDGE DETECTION 2 .......................................................................................................... 15-4
INTERRUPTS OR POLLING ...................................................................................................................... 15-5
FUNCTION DESCRIPTION........................................................................................................................ 15-5
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15-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
15.1 Features
The USRT implements a hardware support for software implemented serial protocols:
ƒ Control of two external lines S0 and S1 (read/write).
ƒ Conditional edge detection generates interrupts.
ƒ S0 rising edge detection.
ƒ S1 value is stored on S0 rising edge.
ƒ S0 signal can be forced to 0 after a falling edge on S0 for clock stretching in the low state.
ƒ S0 signal can be stretched in the low state after a falling edge on S0 and after a S1 conditional detection.
15.2 Overview
The USRT block supports software universal synchronous receiver and transmitter mode interfaces.
External lines S0 and S1 respectively correspond to clock line and data line. S0 is mapped to PB[4] and S1 to
PB[5] when the USRT block is enabled. It is independent of RegPBdir (Port B can be input or output). When
USRT is enabled, the configurations in port B for PB[4] and PB[5] are overwritten by the USRT configuration.
Internal pull-ups can be used by setting the PBPullup[5:4] bits.
Conditional edge detections are provided.
RegUsrtS1 can be used to read the S1 data line from PB[5] in receive mode or to drive the output S1 line PB[5] by
writing it when in transmit mode. It is advised to read S1 data when in receive mode from the RegUsrtBufferS1
register, which is the S1 value sampled on a rising edge of S0.
15.3 Register map
Register name
RegUsrtS1
RegUsrtS0
RegUsrtCtrl
RegUsrtCond1
RegUsrtCond2
RegUsrtBufferS1
RegUsrtEdgeS0
Table 15-1: USRT registers
Block configuration registers:
pos.
7-1
0
RegUsrtS1
“0000000”
UsrtS1
rw
reset
function
r
r/w
1 nresetglobal
Unused
Write: data S1 written to pad PB[5]),
Read: value on PB[5] (not UsrtS1 value).
Table 15-2: RegUsrtS1
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15-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7-1
0
RegUsrtS0
“0000000”
UsrtS0
rw
r
r/w
reset
1 nresetglobal
function
Unused
Write: clock S0 written to pad PB[4],
Read: value on PB[4] (not UsrtS0 value).
Table 15-3: RegUsrtS0
The values that are read in the registers RegUsrtS1 and RegUsrtS0 are not necessarily the same as the values
that were written in the register. The read value is read back on the circuit pins not in the registers themselves.
Since the outputs are open drain, an external circuit on the circuit pins may force a value different from the register
value.
pos.
7-4
3
RegUsrtCtrl
“0000”
UsrtWaitS0
rw
r
r
reset
0 nresetglobal
2
UsrtEnWaitCond1
r/w
0 nresetglobal
1
0
UsrtEnWaitS0
UsrtEnable
r/w
r/w
0 nresetglobal
0 nresetglobal
function
Unused
Clock stretching flag (0=no stretching),
cleared by writing RegUsrtBufferS1
Enable stretching on UsrtCond1 detection
(0=disable)
Enable stretching operation (0=disable)
Enable USRT operation (0=disable)
Table 15-4: RegUsrtCtrl
pos.
7-1
0
RegUsrtCond1
“0000000”
UsrtCond1
rw
r
r/c
reset
0 nresetglobal
function
Unused
State of condition 1 detection (1 =detected),
cleared when written.
Table 15-5: RegUsrtCond1
pos.
7-1
0
RegUsrtCond2
“0000000”
UsrtCond2
rw
r
r/c
reset
0 nresetglobal
function
Unused
State of condition 2 detection (1 =detected),
cleared when written.
Table 15-6: RegUsrtCond2
pos.
7-1
0
RegUsrtBufferS1
“0000000”
UsrtBufferS1
rw
r
r
reset
0 nresetglobal
function
Unused
Value on S1 at last S0 rising edge.
Table 15-7: RegUsrtBufferS1
pos.
7-1
0
RegUsrtEdgeS0
“0000000”
UsrtEdgeS0
rw
r
r
reset
0 nresetglobal
function
Unused
State of rising edge detection on S0
(1=detected). Cleared by reading
RegUsrtBufferS1
Table 15-8: RegUsrtEdgeS0
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15-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
15.4 Interrupts map
interrupt source
Irq_cond2
Irq_cond1
default mapping in the interrupt manager
RegIrqMid(7)
RegIrqMid(6)
Table 15-9: Interrupts map
15.5 Conditional edge detection 1
S1
S0
Figure 15-1: Condition 1
Condition 1 is satisfied when S0=1 at the falling edge of S1. The bit UsrtCond1 in RegUsrtCond1 is set when the
condition 1 is detected and the USRT interface is enabled (UsrtEnable=1). Condition 1 is asserted for both modes
(receiver and transmitter). The UsrtCond1 bit is read only and is cleared by all reset conditions and by writing any
data to its address.
Condition 1 occurrence also generates an interrupt on Irq_cond1.
15.6 Conditional edge detection 2
S1
S0
Figure 15-2: Condition 2
Condition 2 is satisfied when S0=1 at the rising edge of S1. The bit UsrtCond2 in RegUsrtCond2 is set when the
condition 2 is detected and the USRT interface is enabled. Condition 2 is asserted for both modes (receiver and
transmitter). The UsrtCond2 bit is read only and is cleared by all reset conditions and by writing any data to its
address.
Condition 2 occurrence also generates an interrupt on Irq_cond2.
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15-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
15.7 Interrupts or polling
In receive mode, there are two possibilities to detect condition 1 or 2: the detection of the condition can generate
an interrupt or the registers can be polled (reading and checking the RegUsrtCond1 and RegUsrtCond2 registers
for the status of USRT communication).
15.8 Function description
The bit UsrtEnable in RegUsrtCtrl is used to enable the USRT interface and controls the PB[4] and PB[5] pins.
This bit puts these two port B lines in the open drain configuration requested to use the USRT interface.
If no external pull-ups are added on PB[4] and PB[5], the user can activate internal pull-ups by setting PBPullup[4]
and PBPullup[5] in RegPBPullup.
The bits UsrtEnWaitS0, UsrtEnWaitCond1, UsrtWaitS0 in RegUsrtCtrl are used for transmitter/receiver control
of USRT interface.
Figure 15-3 shows the unconditional clock stretching function which is enabled by setting UsrtEnWaitS0.
S0
UsrtWaitS0
write Reg UsrtBufferS1
Figure 15-3: S0 Stretching (UsrtEnWaitS0=1)
When UsrtEnWaitS0 is 1, the S0 line will be maintained at 0 after its falling edge (clock stretching). UsrtWaitS0 is
then set to 1, indicating that the S0 line is forced low. One can release S0 by writing to the RegUsrtBufferS1
register.
The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 15-4
shows the conditional clock stretching function, which is enabled by setting UsrtEnWaitCond1.
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15-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
S1
S0
UsrtWaitS0
write Reg UsrtBufferS1
Figure 15-4: Conditional stretching (UsrtEnWaitCond1=1)
When UsrtEnWaitCond1 is 1, the S0 signal will be stretched in its low state after its falling edge if the condition 1
has been detected before (UsrtCond1=1). UsrtWaitS0 is then set to 1, indicating that the S0 line is forced low.
One can release S0 by writing to the RegUsrtBufferS1 register.
Figure 15-5 shows the sampling function implemented by the UsrtBufferS1 bit. The bit UsrtBufferS1 in
RegUsrtBufferS1 is the value of S1 sampled on PB[4] at the last rising edge of S0. The bit UsrtEdgeS0 in
RegUsrtEdgeS0 is set to one on the same S0 rising edge and is cleared by a read operation of the
RegUsrtBufferS1 register. The bit therefor indicates that a new value is present in the RegUsrtBufferS1 which
was not yet read.
S1
S0
UsrtBufferS1
read Reg UsrtBufferS1
UsrtEdgeS0
Figure 15-5: S1 sampling
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15-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
16 Serial Peripheral Interface
16.1
16.2
16.3
16.4
16.5
16.5.1
FEATURES .................................................................................................................................... 16-2
OVERVIEW ................................................................................................................................... 16-2
REGISTER MAP ............................................................................................................................. 16-2
INTERRUPTS MAP .......................................................................................................................... 16-4
FUNCTION DESCRIPTION ................................................................................................................ 16-4
SPI interface ............................................................................................................................... 16-4
16.5.1.1
16.5.1.2
16.5.1.3
General operation............................................................................................................................................. 16-4
Master/Slave synchronization .......................................................................................................................... 16-6
Software hints................................................................................................................................................... 16-7
16.5.2
General purpose port.................................................................................................................. 16-8
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16-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
16.1 Features
The SPI block implements the following functionality’s:
• Full duplex operating mode.
• Master or slave configuration capability.
• Separate transmissions data, shift data and receive data registers in order to perform back-to-back
transmissions.
• Four master mode frequencies available to generate serial clock.
• Serial clock with programmable polarity and phase.
• One enabled interrupt: SPI receive register full.
• Overflow detection flag.
• 4 I/O dedicated pads with 8mA drive and pull-up programmable.
• Multi-slave configuration capability.
• General purpose 4 bit wide digital input/output port mode.
16.2 Overview
The SPI can communicate with other external SPI devices. It provides flexibility to communicate with different SPI
compatible circuits from several manufacturers (Serial EEPROMs, display drivers, A/D converters, audio device).
Four dedicated input or output pads are attached to the SPI block: MISO, MOSI, SCK, NSS.
Six registers are used to run the SPI block. RegSpiControl, RegSpiStatus, RegSpiDataOut, RegSpiDataIn,
RegSpiPullup, RegSpiDir are used to configure the communication settings, read the flags, write and read the
exchanged data, and for the pad settings.
The SPI device can also be used as a 4 bit general purpose input/output port.
16.3 Register map
Register name
RegSpiControl
RegSpiStatus
RegSpiDataOut
RegSpiDataIn
RegSpiPullup
RegSpiDir
Table 16-1: Address mapping for SPI
When the peripheral is used as a general-purpose parallel I/O port, the SPI pads are mapped in the registers as
follows (RegSpiDataOut, RegSpiDatain, RegSpiPullup and RegSpiDir):
SPI pad names
NSS
MOSI
MISO
SCK
SPI register bits
3
2
1
0
Table 16-2: Pin mapping in general purpose port mode
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16-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Block configuration registers:
pos.
RegSpiControl
Rw
Reset
Function
Writing 1 clears transmission control counters.
In master mode, this bit drives the NSS output
pad. Unused in slave mode. It must be
asserted (to 0) during a byte transfer.
0: SPI slave mode.
1: SPI master mode.
peripheral configuration:
0: general purpose digital I/O port
1: SPI interface
Controls the timing relationship between the
serial clock and SPI data (cf. Figure 16-2 and
Figure 16-3).
Determines the idle-state of the SPI clock
signal (cf. Figure 16-2 and Figure 16-3).
Selects the baud rate in master mode.
00 => ckRcExt/2
01 => ckRcExt/8
10 => ckRcExt/16
11 => 4kHz
7
6
ClearCounter
NotSlaveSelect
w1
r/w
1 nresetglobal
5
SpiMaster
r/w
1 nresetglobal
4
SpiEnable
r/w
0 nresetglobal
3
ClockPhase
r/w
1 nresetglobal
2
ClockPolarity
r/w
0 nresetglobal
1-0
BaudRate
r/w
00
nresetglobal
Table 16-3: RegSpiControl
Note that the precision of the 4kHz depends on the selected clock source (see documentation of the clock block).
In slave mode, the fastest clock of the circuit should be at least 4 times faster than the baud rate of the master.
pos.
7-3
2
RegSpiStatus
-SpiOverflow
Rw
r
r
c1
Reset
00000
0
nresetglobal
1
SpiRxFull
r
0
nresetglobal
0
SpiTxEmpty
r
w1
1
nresetglobal
Function
Unused
This flag is set when a new byte is loaded in
SpiDataIn before the previous byte was read.
Writing 1 clears the flag.
This flag is set each time a byte transfers from
the shift register to SpiDataIn. It is cleared by
reading SpiDataIn.
This flag is cleared each time the CPU writes a
byte in SpiDataOut. It is set when a byte
transfers from SpiDataOut to the shift register.
In the master mode, writing 1 to this bit
performs the data transfer SpiDataOut to the
shift register and enables the start of
transmission.
In the slave mode, the byte transfer is done
automatically except for the very first byte
after nresetglobal (cf.16.6 Software hints).
Table 16-4: RegSpiStatus
Pos.
7-0
RegSpiDataOut
SpiDataOut[7:0]
Rw
r/w
Reset
00000000
nresetglobal
Function
SPI mode: transmission data buffer
I/O mode: output data (only bits 3:0, see Table
16-2)
Table 16-5: RegSpiDataOut
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16-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Pos.
7-0
RegSpiDataIn
SpiDataIn[7:0]
Rw
r
Reset
00000000
nresetglobal
Function
SPI mode: reception data byte
I/O mode: input data (only bits 3:0, see Table
16-2, bits 7:4 read 0)
Table 16-6: RegSpiDataIn
Pos.
7-4
3-0
RegSpiPullup
-SpiPullup
Rw
r
r/w
Reset
0000
1
nresetpconf
Function
Unused.
Pullup configuration in both SPI and I/O mode
(1=active). Mapping as in Table 16-2.
Table 16-7: RegSpiPullup
Note that pull-ups are disconnected independent from the value in RegSpiPullup if the corresponding pin is
configured as an output.
Pos.
7-4
3-0
RegSpiDir
-SpiDir[3:0]
Rw
r
r/w
Reset
0000
0
nresetpconf
Function
Unused.
I/O mode only (mapping in Table 16-2)
1: output enabled
0: output disabled
Table 16-8: RegSpiDir
16.4 Interrupts map
interrupt source
Irq_spi(0)
Default mapping in the interrupt manager
irq_bus(21)
Table 16-9: Interrupts map
Irq_spi(0) interrupt is activated at the assertion of the SpiRxFull flag (cf. RegSpiStatus description).
16.5 Function description
Depending on the value of the bit SpiEnable in the RegSpiControl register, the SPI peripheral can work either as
a real SPI interface (master or slave) or as a general purpose 4 bit wide digital input/output port.
16.5.1 SPI interface
16.5.1.1 General operation
The peripheral is configured as an SPI by setting the bit SpiEnable=1 in RegSpiControl. The bit SpiMaster in
RegSpiControl selects the master or slave mode.
The SPI interface supports 4 physical wires between one master device and one or more slave devices (Figure
16-1): MISO (Master In Slave Out), MOSI (Master Out Slave In), SCK (Serial Clock), NSS (Slave Select).
A byte transmission performs a rotate operation between the value stored in the 8 bit shift register of the master
device and the value stored in the 8 bit shift register of the (selected) slave device. The SCK line is used to
synchronize both SPI interfaces.
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16-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
The transmission format depends on the two configuration bits ClockPhase and ClockPolarity. These 2 bits
should be configured in the same way in the slave and the master device in order to properly run the SPI
transmission. The transmission baud rate depends on the two bits BaudRate, these 2 bits are only used in the
master device to generate the serial clock SCK signal at the selected frequency. Data are transferred in a duplex
way from master to slave through the MOSI wire and from slave to master through the MISO wire. Data are always
sent most significant bit first. Each SPI device sequentially operates in two times: one clock edge to sample the
received bit, and the other clock edge to shift the byte inside the shift register. The NSS signal is software
controlled. It must be driven by the SPI master device by writing to the bit NotSlaveSelect in RegSpiControl. NSS
should remain low during the byte transmission.
Shift register
MISO
MISO
MOSI
MOSI
SCK
SCK
NSS
NSS
Shift register
Baud Rate
Generator
Slave
Master
Figure
16-1: Connection of master and slave device
The next figure shows the timing diagrams for a SPI transmission with ClockPhase equal to 0. This means the
active state of the serial clock SCK signal occurs on the 2nd half of the SCK cycle.
1
2
3
4
5
6
7
8
MOSI
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
MISO
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
SCK cycle
SCK
(CPOL=0)
SCK
(CPOL=1)
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
NSS
Figure 16-2: SPI transmission format with ClockPhase=0
The next figure shows the timing diagrams for a SPI transmission with ClockPhase equal to 1. This means the
st
active state of the serial clock SCK signal occurs on the 1 half of the SCK cycle.
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16-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
1
2
3
4
5
6
7
8
MOSI
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
MISO
MSB
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
LSB
SCK cycle
SCK
(CPOL=0)
SCK
(CPOL=1)
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
Shift
Samp le
NSS
Figure 16-3: SPI transmission format with ClockPhase=1
Note: for both cases, it is not required to toggle the NSS signal back to high and back to low between each byte
transmitted.
The SPI interface can be operated by polling the RegSpiStatus register or interrupt driven. The interrupt is active
on reception of a new byte.
In case of a multi-slave configuration, any digital output pin of any parallel port can be used to select the different
slaves. In some cases, it might be easier to have DC signals on these pins and to derive the timing from the single
NSS pin independently from the selected slave. This can be realized by combining the NSS wire from the master
device with signals coming from an output port as shown in Figure 16-4.
Pull-up resistors can be added on the input pads (MISO in master mode, MOSI, NSS and SCK in slave mode) by
setting the corresponding bits in RegSpiPullup. Use Table 16-2 for the correspondence between the pads and
register bits.
16.5.1.2 Master/Slave synchronization
In the master mode, a transmission is started by writing a 1 to the bit SpiTxEmpty. This automatically loads the
data of the register RegSpiDataOut to the shift register and starts the clock and shifting. At the end of the
transmission, the clock stops and the received data are copied to RegSpiDataIn. The bit SpiTxEmpty should not
be asserted while the previous transmission is still running, otherwise, the transmitted and received data will be
corrupted.
In slave mode, the fastest clock in the circuit should be at least 4 times faster than the baud rate of the
transmission. The transmission is synchronized by the NSS input signal. While the NSS signal is high, the counters
controlling the transmission are reset. The reception starts at the first clock cycle after the falling edge of NSS. At
the end of the transmission, the received data are copied to RegSpiDataIn and the contents of the register
RegSpiDataOut are copied automatically to the shift register. The data in the shift register can be overwritten by
writing 1 to SpiTxEmpty. This should not be done while a transmission is running, otherwise, the transmitted and
received data will be corrupted.
The counters controlling the timing of the transmission can be reset by writing a 1 to the ClearCounters bit in the
RegSpiControl register. In master mode, it restarts a complete transmission cycle. In slave mode, it has the same
effect as a rising edge of NSS. This bit should be used with caution.
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16-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Shift register
MISO
MISO
MOSI
MOSI
SCK
SCK
NSS
Shift register
NSS
Baud Rate
Generator
Slave 1
digital output pad 1
MISO
digital output pad 2
Shift register
MOSI
digital output pad 3
SCK
NSS
Master
Slave 2
MISO
Shift register
MOSI
SCK
NSS
Slave N
Figure 16-4: Connection of master and slaves in the case of a multi slave configuration
16.6 Software hints
16.6.1 Master mode
The following routine must be executed by the CoolRISC in order to run properly the SPI interface in master mode:
INITIALIZATION
1- Write RegSpiControl to enable the SPI interface and to configure the master mode (configured by default) and
communication settings.
2- Write the data to send in the RegSpiDataOut register. The SpiTxEmpty flag toggles low.
3- Write 1 to the SpiTxEmpty bit to load the shift register with the value inside the RegSpiDataOut register and to
start the byte transmission. The SpiTxEmpty flag toggles back high.
4- Write the next data to send to the RegSpiDataOut register. The SpiTxEmpty flag toggles low.
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16-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
NORMAL OPERATION
5- Wait for the end of transmission, i.e. SpiRxFull flag is one or the interrupt of the receiver is asserted.
6- Write 1 to the SpiTxEmpty bit to load the shift register with the value inside the RegSpiDataOut register and to
start the byte transmission. The SPI SpiTxEmpty flag toggles back high.
7- Read RegSpiDataIn. The SpiRxFull flag returns to 0.
8- Write the next data to send in the RegSpiDataOut register. The SpiTxEmpty flag toggles low.
9- Jump to 5.
16.6.2 Slave mode
The following routine must be executed by the CoolRISC in order to run properly the SPI interface in slave mode:
INITIALIZATION
1- Write RegSpiControl to enable the SPI interface and to configure the slave mode and communication settings
(as configured in the master device).
2- Write the data to send in the RegSpiDataOut register. The SpiTxEmpty flag toggles low.
3- Write 1 to SpiTxEmpty bit to load the shift register with the value of the RegSpiDataOut register. The
SpiTxEmpty flag toggles back high. This load is only required for the first byte to transmit after nresetglobal. It is
automatic for the following bytes.
4- Write the next data to send in the RegSpiDataOut register. The SpiTxEmpty flag toggles low.
NORMAL OPERATION
5- Wait for the end of transmission, i.e. the SpiRxFull flag is one or the interrupt of the receiver asserted. The shift
register is automatically loaded with the value inside the RegSpiDataOut register and the SpiTxEmpty flag toggles
back high.
6- Read RegSpiDataIn. The SpiRxFull flag returns to 0.
7- Write the next data to send in the RegSpiDataOut register. The SpiTxEmpty flag toggles low.
8- Jump to 5.
16.6.3 General purpose port.
This mode is enabled when SpiEnable value is 0 (default value).
The SPI dedicated pads are used as a general purpose 4 bit input/output digital port. Next figure shows the
structure of the SPI in this mode.
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16-8
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
vdd
SPI
spi_pullup[3:0]
spi_out[3:0]
RegSpiPullup
RegSpiDataOut
spi_dir[3:0]
RegSpiDir
spi_in[3:0]
RegSpiDataIn
Figure 16-5: Structure of the SPI general purpose port
The direction of each bit within the SPI (input or input/output) can be individually set by using the RegSpiDir
register. If RegSpiDir[x] = 1, the corresponding SPI pad becomes an output. After reset (nresetpconf), the SPI
pads are in input configuration (RegSpiDir[x] are reset to 0).
In output configuration, the data are stored in RegSpiDataOut prior to output at SPI pads.
In input configuration, the status of SPI pads is available in RegSpiIn (read only). Reading is always direct –there is
no digital debounce function associated with SPI pads. In case of possible noise on input signals, a software
debouncer or an external filter must be realized.
If a bit in RegSpiPullup is set, the pull-up of the corresponding input pad is active. The pull-ups are disabled in
output configuration independently of the RegSpiPullup content. By default after reset, the SPI pads are
configured as input ports with all pull-ups active. Note that the pull-up resistors can be used for the input pads in
SPI mode also.
Next table shows the link between SPI pads and SPI data bits.
SPI pad names
NSS
MOSI
MISO
SCK
SPI data bits
SpiDataOut[3] or SpiDataIn[3]
SpiDataOut[2] or SpiDataIn[2]
SpiDataOut[1] or SpiDataIn[1]
SpiDataOut[0] or SpiDataIn[0]
Table 16-10: SPI pad/bit relationship
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16-9
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
17.
Acquisition
17.1
17.2
17.3
17.4
17.4.1
17.4.2
17.4.3
17.5
17.6
17.6.1
17.6.2
17.6.3
17.6.4
17.7
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
17.7.7
17.7.8
17.8
17.8.1
17.8.2
17.8.3
Chain
ZOOMINGADC™ FEATURES ....................................................................................................... 17-2
OVERVIEW ................................................................................................................................. 17-2
REGISTER MAP ........................................................................................................................... 17-2
ZOOMINGADC™ DESCRIPTION ................................................................................................... 17-4
Acquisition Chain ..................................................................................................................... 17-4
Peripheral Registers................................................................................................................. 17-5
Continuous-Time vs. On-Request ............................................................................................ 17-7
INPUT MULTIPLEXERS ................................................................................................................. 17-7
PROGRAMMABLE GAIN AMPLIFIERS.............................................................................................. 17-8
PGA & ADC Enabling............................................................................................................. 17-10
PGA1 ..................................................................................................................................... 17-10
PGA2 ..................................................................................................................................... 17-10
PGA3 ..................................................................................................................................... 17-10
ADC CHARACTERISTICS ........................................................................................................... 17-11
Conversion Sequence............................................................................................................ 17-11
Sampling Frequency .............................................................................................................. 17-12
Over-Sampling Ratio.............................................................................................................. 17-12
Elementary Conversions ........................................................................................................ 17-13
Resolution .............................................................................................................................. 17-13
Conversion Time & Throughput ............................................................................................. 17-14
Output Code Format .............................................................................................................. 17-14
Power Saving Modes ............................................................................................................. 17-16
SPECIFICATIONS AND MEASURED CURVES ................................................................................. 17-16
Default Settings...................................................................................................................... 17-16
Specifications......................................................................................................................... 17-17
Linearity ................................................................................................................................. 17-18
17.8.3.1 Integral non-linearity.................................................................................................................................... 17-18
17.8.3.2 Differential non-linearity .............................................................................................................................. 17-22
17.8.4
17.8.5
17.8.6
17.8.7
17.9
17.9.1
17.9.2
17.9.3
17.9.4
17.9.5
Noise...................................................................................................................................... 17-23
Gain Error and Offset Error .................................................................................................... 17-24
Power Consumption............................................................................................................... 17-25
Power Supply Rejection Ratio................................................................................................ 17-27
APPLICATION HINTS .................................................................................................................. 17-28
Input Impedance .................................................................................................................... 17-28
PGA Settling or Input Channel Modifications.......................................................................... 17-28
PGA Gain & Offset, Linearity and Noise................................................................................. 17-28
Frequency Response ............................................................................................................. 17-29
Power Reduction.................................................................................................................... 17-29
© Semtech 2006
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17-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
17.1 ZoomingADC™ Features
The ZoomingADC™ is a complete and versatile low-power analog front-end interface typically intended for sensing
applications. The key features of the ZoomingADC™ are:
Programmable 6 to 16-bit dynamic range oversampled ADC
• Flexible gain programming between 0.5 and 1000
• Flexible and large range offset compensation
• 4-channel differential or 8-channel single-ended input multiplexer
• 2-channel differential reference inputs
• Power saving modes
• Direct interfacing to CoolRisc™ microcontroller
17.2 Overview
Analog
Inputs
MUX
fS
0
1
2
3
4
5
6
7
VIN
fS
PGA1
PGA2
VD1
GD1
Input
Selection
MUX
0
Reference 1
Inputs 2
PGA3
VIN,ADC
VD2
GD2
GD3
OFF2
OFF3
Offset2
Offset3
ADC
16
VREF
3
Reference
Selection
Gain1 Gain2
Gain3
ZOOM
Figure 17-1. ZoomingADC™ general functional block diagram
The total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an
oversampled A/D converter. The reference voltage can be selected on two different channels. Two offset
compensation amplifiers allow for a wide offset compensation range. The programmable gain and offset give the
ability to zoom in on a small portion of the reference voltage defined input range.
17.3 Register map
There are eight registers in the acquisition chain (AC), namely RegAcOutLsb, RegAcOutMsb, RegAcCfg0,
RegAcCfg1, RegAcCfg2, RegAcCfg3, RegAcCfg4 and RegAcCfg5. Table 17-2 to Table 17-9 show the mapping
of control bits and functionality of these registers while Table 17-1 gives an overview of these eight.
The register map only gives a short description of the different configuration bits. More detailed information is found
in subsequent sections.
© Semtech 2006
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17-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
register name
RegAcOutLsb
RegAcOutMsb
RegAcCfg0
RegAcCfg1
RegAcCfg2
RegAcCfg3
RegAcCfg4
RegAcCfg5
Table 17-1: AC registers
pos.
7:0
RegAcOutLsb
Out[7:0]
rw
r
reset
00000000
nresetglobal
description
LSB of the output code
Table 17-2: RegAcOutLsb
pos.
7:0
RegAcOutMsb
Out[15:8]
rw
r
reset
00000000
nresetglobal
description
MSB of the output code
Table 17-3: RegAcOutMsb
pos.
7
6:5
RegAcCfg0
Start
SET_NELCONV[1:0]
rw
w r0
rw
reset
0 nresetglobal
01 nresetglobal
4:2
SET_OSR[2:0]
rw
010 nresetglobal
1
0
CONT
reserved
rw
rw
0 nresetglobal
0 nresetglobal
description
starts a conversion
sets the number of elementary conversions
sets the oversampling rate of an elementary
conversion
continuous conversion mode
Table 17-4: RegAcCfg0
pos.
7:6
5:4
3:0
RegAcCfg1
IB_AMP_ADC[1:0]
IB_AMP_PGA[1:0]
ENABLE[3:0]
rw
rw
rw
rw
reset
11 nresetglobal
11 nresetglobal
0000
nresetblobal
description
Bias current selection of the ADC converter
Bias current selection of the PGA stages
Enables the different PGA stages and the ADC
Table 17-5: RegAcCfg1
pos.
7:6
5:4
3:0
RegAcCfg2
FIN[1:0]
PGA2_GAIN[1:0]
PGA2_OFFSET[3:0]
rw
rw
rw
rw
reset
00 nresetglobal
00 nresetglobal
0000
nresetglobal
description
Sampling frequency selection
PGA2 stage gain selection
PGA2 stage offset selection
Table 17-6: RegAcCfg2
pos.
7
6:0
RegAcCfg3
PGA1_GAIN
PGA3_GAIN[6:0]
rw
rw
rw
reset
0 nresetglobal
0000000
nresetglobal
description
PGA1 stage gain selection
PGA3 stage gain selection
Table 17-7: RegAcCfg3
© Semtech 2006
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17-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7
6:0
RegAcCfg4
reserved
PGA3_OFFSET[6:0]
rw
r
rw
reset
0
0000000
nresetglobal
description
Unused
PGA3 stage offset selection
Table 17-8: RegAcCfg4
pos.
7
6
5:1
0
RegAcCfg5
BUSY
DEF
AMUX[4:0]
VMUX
rw
r
w r0
rw
rw
reset
0 nresetglobal
0
00000
nresetglobal
0 nresetglobal
description
Activity flag
Selects default configuration
Input channel configuration selector
Reference channel selector
Table 17-9: RegAcCfg5
17.4 ZoomingADC™Description
Figure 17-2 gives a more detailed description of the acquisition chain.
17.4.1
Acquisition Chain
Figure 17-1 shows the general block diagram of the acquisition chain (AC). A control block (not shown in Figure
17-1) manages all communications with the CoolRisc™ microcontroller.
Analog inputs can be selected among eight input channels, while reference input is selected between two
differential channels.
The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of a
combination of input and reference signals VIN and VREF, the input voltage is modulated and amplified through
stages 1 to 3. Fine gain programming up to 1'000V/V is possible. In addition, the last two stages provide
programmable offset. Each amplifier can be bypassed if needed.
The output of the PGA stages is directly fed to the analog-to-digital converter (ADC), which converts the signal
VIN,ADC into digital.
Like most ADCs intended for instrumentation or sensing applications, the ZoomingADC™ is an over-sampled
converter (See Note1). The ADC is a so-called incremental converter, with bipolar operation (the ADC accepts both
positive and negative input voltages). In first approximation, the ADC output result relative to full-scale (FS) delivers
the quantity:
OUT ADC V IN , ADC
≅
FS / 2
V REF / 2
(Eq. 1)
in two's complement (see Sections 17.4 and 17.7 for details). The output code OUTADC is -FS/2 to +FS/2 for VIN,ADC
≅ -VREF/2 to +VREF/2 respectively. As will be shown in section 17.6, VIN,ADC is related to input voltage VIN by the
relationship:
V IN , ADC = GDTOT ⋅ V IN − GDoff TOT ⋅ V REF (V)
(Eq. 2)
where GDTOT is the total PGA gain, and GDoffTOT is the total PGA offset.
1 Note: Over-sampled converters are operated with a sampling frequency f much higher than the input signal's Nyquist rate (typically f is 20S
S
1'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include digital
decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications.
© Semtech 2006
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17-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
0
1
2
3
AC_A 4
5
6
7
fS
MUX
Inputs
PGA2
PGA3
GD1
GD2
GD3
OFF2
OFF3
VIN,ADC
VIN
ADC
VREF
MUX
0
1
AC_R 2
fS
PGA1
3
5
2
4
7
Acquisition Chain
7
Register Bank
RegACCfg5
RegACCfg4
8
RegACCfg3
RegACOutLSB
RegACCfg2
RegACOutMSB
RegACCfg1
RegACCfg0
Power Saving Modes
PGA Enabling
8
ADC Busy Flag
Default Settings
Conversion Start
Nbr of Elementary Cycles
Over-Sampling Ratio
Continuous vs. On-Request
Sampling Frequency fS
Figure 17-2. ZoomingADC™ detailed functional block diagram
17.4.2
Peripheral Registers
Figure 17-2 shows a detailed functional diagram of the ZoomingADC™.
In Table 17-10 the configuration of the peripheral registers is detailed. The system has a bank of eight 8-bit
registers: six registers are used to configure the acquisition chain (RegAcCfg0 to 5), and two registers are used
to store the output code of the analog-to-digital conversion (RegAcOutMsb & Lsb). The register coding of the
ADC parameters and performance characteristics are detailed in Section 17.7.
Table 17-10. Peripheral registers to configure the acquisition chain (AC)
and to store the analog-to-digital conversion (ADC) result
Register
Name
Bit Position
7
6
5
4
RegAcOutLsb
2
1
0
OUT[7:0]
RegAcOutMsb
RegAcCfg0
Default values:
RegAcCfg1
Default values:
3
OUT[15:8]
START
0
SET_NELC[1:0]
01
SET_OSR[2:0]
010
IB_AMP_ADC[1:0]
IB_AMP_PGA[1:0]
11
11
© Semtech 2006
CONT
0
ENABLE[3:0]
0001
TEST
0
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17-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Cont’
Register
Name
RegAcCfg2
Default values:
RegAcCfg3
Default values:
RegAcCfg4
Default values:
RegAcCfg5
Default values:
Bit Position
7
6
FIN[1:0]
00
PGA1_G
0
0
BUSY
0
DEF
0
5
4
3
2
1
PGA2_GAIN[1:0]
PGA2_OFFSET[3:0]
00
0000
PGA3_GAIN[6:0]
0000000
PGA3_OFFSET[6:0]
0000000
AMUX[4:0]
00000
0
VMUX
0
With:
•
OUT: (r) digital output code of the analog-to-digital converter. (MSB = OUT[15])
•
START: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0.
SET_NELC[1:0]
•
SET_NELC: (rw) sets the number of elementary conversions to 2
. To compensate for offsets, the input signal
is chopped between elementary conversions (1,2,4,8).
(3+SET_OSR[2:0])
. OSR = 8, 16, 32, ...,
•
SET_OSR: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2
512, 1024.
•
CONT: (rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit remains at 1.
•
TEST: bit only used for test purposes. In normal mode, this bit is forced to 0 and cannot be overwritten.
•
IB_AMP_ADC: (rw) sets the bias current in the ADC to 0.25*(1+ IB_AMP_ADC[1:0]) of the normal operation current (25,
50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
•
IB_AMP_PGA: (rw) sets the bias current in the PGAs to 0.25*(1+IB_AMP_PGA[1:0]) of the normal operation current (25,
50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
•
ENABLE: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages
that are disabled are bypassed.
•
FIN: (rw) These bits set the sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency,
the sampling frequency is given as: 00 Æ 1/4 fRC, 01 Æ 1/8 fRC, 10 Æ 1/32 fRC, 11Æ ~8kHz.
•
PGA1_GAIN: (rw) sets the gain of the first stage: 0 Æ 1, 1 Æ 10.
•
PGA2_GAIN: (rw) sets the gain of the second stage: 00 Æ 1, 01 Æ 2, 10 Æ 5, 11 Æ 10.
•
PGA3_GAIN: (rw) sets the gain of the third stage to PGA3_GAIN[6:0]⋅1/12.
•
PGA2_OFFSET: (rw) sets the offset of the second stage between –1 and +1, with increments of 0.2. The MSB gives the sign
(0 → positive, 1 → negative); amplitude is coded with the bits PGA2_OFFSET[5:0].
•
PGA3_OFFSET: (rw) sets the offset of the third stage between –5.25 and +5.25, with increments of 1/12. The MSB gives the
sign (0 → positive, 1 → negative); amplitude is coded with the bits PGA3_OFFSET[5:0].
•
BUSY: (r) set to 1 if a conversion is running.
•
DEF: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary
conversions, over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one.
•
AMUX(4:0): (rw) AMUX[4] sets the mode (0 Æ 4 differential inputs, 1 Æ 7 inputs with A(0) = common reference)
AMUX(3) sets the sign (0 Æ straight, 1Æ cross) AMUX[2:0] sets the channel.
•
VMUX: (rw) sets the differential reference channel (0 Æ R(1) and R(0), 1 Æ R(3) and R(2)).
(r = read; w = write; rw = read & write)
© Semtech 2006
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17-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
17.4.3
Continuous-Time vs. On-Request
The ADC can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit
CONT).
In "continuous-time" mode, the input signal is repeatedly converted into digital. After a conversion is finished, a new
one is automatically initiated. The new value is then written in the result register, and the corresponding internal
trigger pulse is generated. This operation is sketched in Figure 17-3. The conversion time in this case is defined as
TCONV.
TCONV
Internal Trig
Ouput Code
RegACOut[15:0]
BUSY
IRQ
Figure 17-3. ADC "continuous-time" operation
TCONV
Internal Trig
Request
START
Ouput Code
RegACOut[15:0]
BUSY
IRQ
Figure 17-4. ADC "on-request" operation
In the "on-request" mode, the internal behavior of the converter is the same as in the "continuous-time" mode, but
the conversion is initiated on user request (with the START bit). As shown in Figure 17-4, the conversion time is
also TCONV.
17.5 Input Multiplexers
The ZoomingADC™ has eight analog inputs AC_A(0) to AC_A(7) and four reference inputs AC_R(0) to
AC_R(3). Let us first define the differential input voltage VIN and reference voltage VREF respectively as:
VIN = VINP − VINN
(V)
(Eq. 3)
VREF = VREFP − VREFN
(V)
(Eq. 4)
and:
As shown in Table 17-11 the inputs can be configured in two ways: either as 4 differential channels (VIN1 =
AC_A(1) - AC_A(0),..., VIN4 = AC_A(7) - AC_A(6)), or AC_A(0) can be used as a common reference, providing
7 signal paths all referenced to AC_A(0). The control word for the analog input selection is AMUX[4:0]. Notice
that the bit AMUX[3] controls the sign of the input voltage.
© Semtech 2006
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17-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
AMUX[4:0]
(RegAcCfg5[5:1])
VINP
VINN
AMUX[4:0]
(RegAcCfg5[5:1])
VINP
VINN
00x00
00x01
00x10
00x11
AC_A(1)
AC_A(3)
AC_A(5)
AC_A(7)
AC_A(0)
AC_A(2)
AC_A(4)
AC_A(6)
01x00
01x01
01x10
01x11
AC_A(0)
AC_A(2)
AC_A(4)
AC_A(6)
AC_A(1)
AC_A(3)
AC_A(5)
AC_A(7)
10000
10001
10010
10011
10100
10101
10110
10111
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
AC_A(0)
11000
11001
11010
11011
11100
11101
11110
11111
AC_A(0)
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
Table 17-11. Analog input selection
Similarly, the reference voltage is chosen among two differential channels (VREF1 = AC_R(1)-AC_R(0) or VREF2 =
AC_R(3)-AC_R(2)) as shown in Table 17-12. The selection bit is VMUX. The reference inputs VREFP and VREFN
(common-mode) can be up to the power supply range.
VMUX
(RegAcCfg5[0])
0
1
VREFP
VREFN
AC_R(1)
AC_R(3)
AC_R(0)
AC_R(2)
Table 17-12. Analog Reference input selection
17.6
Programmable Gain Amplifiers
As seen in Figure 17-1, the zooming function is implemented with three programmable gain amplifiers (PGA).
These are:
•
PGA1: coarse gain tuning
•
PGA2: medium gain and offset tuning
•
PGA3: fine gain and offset tuning
All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation
and gain, as well as the offset of stages 2 and 3. These functions are examined hereafter.
ENABLE[3:0]
Block
xxx0
xxx1
xx0x
xx1x
x0xx
x1xx
0xxx
1xxx
ADC disabled
ADC enabled
PGA1 disabled
PGA1 enabled
PGA2 disabled
PGA2 enabled
PGA3 disabled
PGA3 enabled
Table 17-13. ADC & PGA enabling
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17-8
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
PGA1 Gain
GD1 (V/V)
1
10
PGA1_GAIN
0
1
Table 17-14. PGA1 Gain Settings
PGA2 Gain
GD2 (V/V)
1
2
5
10
PGA2_GAIN[1:0]
00
01
10
11
Table 17-15. PGA2 gain settings
PGA2_OFFSET[3:0]
0000
0001
0010
0011
0100
0101
1001
1010
1011
1100
1101
PGA2 Offset
GDoff2 (V/V)
0
+0.2
+0.4
+0.6
+0.8
+1
-0.2
-0.4
-0.6
-0.8
-1
Table 17-16. PGA2 offset settings
PGA3 Gain
GD3 (V/V)
0
1/12(=0.083)
...
6/12
...
12/12
16/12
PGA3_GAIN[6:0]
0000000
0000001
...
0000110
...
0001100
0010000
...
0100000
...
1000000
...
1111111
32/12
64/12
127/12(=10.58)
Table 17-17. PGA3 gain settings
© Semtech 2006
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17-9
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
PGA3_OFFSET[6:0]
0000000
0000001
0000010
...
0010000
...
0100000
...
0111111
1000000
1000001
1000010
...
1010000
...
1100000
...
1111111
PGA3 Offset
GDoff3 (V/V)
0
+1/12(=+0.083)
+2/12
...
+16/12
...
+32/12
...
+63/12(=+5.25)
0
-1/12(=-0.083)
-2/12
...
-16/12
...
-32/12
...
-63/12(=-5.25)
Table 17-18. PGA3 offset settings
17.6.1
PGA & ADC Enabling
Depending on the application objectives, the user may enable or bypass each PGA stage. This is done using the
word ENABLE and the coding given in Table 17-13. To reduce power dissipation, the ADC can also be inactivated
while idle.
17.6.2
PGA1
The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 17-14). The voltage VD1 at
the output of PGA1 is:
V D1 = GD1 ⋅ V IN
(V)
(Eq. 5)
where GD1 is the gain of PGA1 (in V/V) controlled with the bit PGA1_GAIN.
17.6.3
PGA2
The second PGA has a finer gain and offset tuning capability, as shown in Table 17-15 and Table 17-16. The
voltage VD2 at the output of PGA2 is given by:
V D 2 = GD2 ⋅ V D1 − GDoff 2 ⋅ V REF
(V)
(Eq. 6)
where GD2 and GDoff2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words
PGA2_GAIN[1:0] and PGA2_OFFSET[3:0] .
17.6.4
PGA3
The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table
17-17 and Table 17-18. The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the
voltage entering the ADC is given by:
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17-10
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
V IN , ADC = GD3 ⋅ V D 2 − GDoff 3 ⋅ V REF
(V)
(Eq. 7)
where GD3 and GDoff3 are respectively the gain and offset of PGA3 (in V/V). The control words are
PGA3_GAIN[6:0] and PGA3_OFFSET[6:0] . To remain within the signal compliance of the PGA stages, the
condition:
V D1 , V D 2 < V DD
(V)
(Eq. 8)
must be verified.
Finally, combining equations Eq. 5 to Eq. 7 for the three PGA stages, the input voltage VIN,ADC of the ADC is
related to VIN by:
V IN , ADC = GDTOT ⋅ V IN − GDoff TOT ⋅ V REF (V)
(Eq. 9)
where the total PGA gain is defined as:
GDTOT = GD3 ⋅ GD2 ⋅ GD1
(V/V)
(Eq. 10)
and the total PGA offset is:
GDoff TOT = GDoff 3 + GD3 ⋅ GDoff 2
(V/V)
(Eq. 11)
17.7 ADC Characteristics
The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three
programmable parameters:
ƒ
ƒ
ƒ
sampling frequency fS,
over-sampling ratio OSR, and
number of elementary conversions NELCONV.
The setting of these parameters and the resulting performances are described hereafter.
17.7.1
Conversion Sequence
A conversion is started each time the bit START or the bit DEF is set. As depicted in Figure 17-5, a complete
analog-to-digital conversion sequence is made of a set of NELCONV elementary incremental conversions and a final
quantitative step. Each elementary conversion is made of (OSR+1) sampling periods TS=1/fS, i.e.:
TELCONV = (OSR + 1) / f S
(s)
(Eq. 12)
The result is the mean of the elementary conversion results. An important feature is that the elementary
conversions are alternatively performed with the offset of the internal amplifiers contributing in one direction and the
other to the output code. Thus, converter internal offset is eliminated if at least two elementary sequences are
performed (i.e. if NELCONV ≥ 2). A few additional clock cycles are also required to initiate and end the conversion
properly.
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17-11
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
TELCONV= (OSR+1)/f S
Init
Elementary
Conversion
Conversion index
Offset
Elementary
Conversion
1
+
2
-
TCONV
Elementary
Conversion
Elementary
Conversion
NELCONV- 1
+
N ELCONV
-
End
Conversion
Result
Figure 17-5. Analog-to-digital conversion sequence
17.7.2
Sampling Frequency
The word FIN[1:0] is used to select the sampling frequency fS (Table 17-19). Three sub-multiples of the internal
RC-based frequency fRCEXT can be chosen. For FIN = "11", sampling frequency is about 8kHz. Additional
information on oscillators and their control can be found in the clock block documentation.
FIN[1:0]
00
01
10
11
Sampling Frequency fS (Hz)
XE8802
XE8801/05
1/4⋅fRC
1/8⋅fRCEXT
1/16⋅fRCEXT
1/8⋅fRC
1/64⋅fRCEXT
1/32⋅fRC
∼8kHz
∼4kHz
Table 17-19. Sampling frequency settings (fRC= RC-based frequency)
17.7.3
Over-Sampling Ratio
The over-sampling ratio (OSR) defines the number of integration cycles per elementary conversion. Its value is set
with the word SET_OSR[2:0] in power of 2 steps (see Table 17-20) given by:
3 + SET_OSR[2 : 0]
OSR = 2
(-)
SET_OSR[2:0]
(RegAcCfg0[4:2])
000
001
010
011
100
101
110
111
(Eq. 13)
Over-Sampling Ratio
OSR (-)
8
16
32
64
128
256
512
1024
Table 17-20. Over-sampling ratio settings
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17-12
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
17.7.4
Elementary Conversions
As mentioned previously, the whole conversion sequence is made of a set of NELCONV elementary incremental
conversions. This number is set with the word SET_NELC[1:0] in binary steps (see Table 17-21) given by:
SET_NELC[1: 0]
N ELCONV = 2
(-)
(Eq. 14)
# of Elementary
Conversions
NELCONV (-)
1
2
4
8
SET_NELC[1:0]
(RegAcCfg0[6:5])
00
01
10
11
Table 17-21. Number of elementary conversion settings
As already mentioned, NELCONV must be equal or greater than 2 to reduce internal amplifier offsets.
17.7.5
Resolution
The theoretical resolution of the ADC, without considering thermal noise, is given by:
n = 2 ⋅ log 2 (OSR) + log 2 ( N ELCONV )
(Bits)
(Eq. 15)
17
Resolution - n [Bits]
15
13
11
SET_NELC= 11
10
01
00
9
7
5
000
001
010
011
100
101
110
111
SET_OSR
Figure 17-6. Resolution vs. SET_OSR[2:0] and SET_NELC[2:0]
SET_OSR
[2:0]
00
SET_NELC
01
10
11
000
001
010
011
100
101
110
111
6
8
10
12
14
16
16
16
7
9
11
13
15
16
16
16
9
11
13
15
16
16
16
16
8
10
12
14
16
16
16
16
(shaded area: resolution truncated to 16 bits
due to output register size RegAcOut[15:0])
Table 17-22. Resolution vs. SET_OSR[2:0] and SET_NELC[1:0] settings
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17-13
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Using Table 17-22 or the graph plotted in Figure 17-6, resolution can be set between 6 and 16 bits. Notice that,
because of 16-bit register use for the ADC output, practical resolution is limited to 16 bits, i.e. n ≤ 16. Even if the
resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and NELCONV to higher
values in order to reduce the influence of the thermal noise in the PGA (see section 17.8.4).
17.7.6
Conversion Time & Throughput
As explained using Figure 17-5, conversion time is given by:
TCONV = ( N ELCONV ⋅ (OSR + 1) + 1) / f S (s)
(Eq. 16)
and throughput is then simply 1/TCONV. For example, consider an over-sampling ratio of 256, 2 elementary
conversions, and a sampling frequency of 500kHz (SET_OSR = "101", SET_NELC = "01", fRC = 2MHz, and FIN =
"00"). In this case, using Table 17-23, the conversion time is 515 sampling periods, or 1.03ms. This corresponds to
a throughput of 971Hz in continuous-time mode. The plot of Figure 17-7 illustrates the classic trade-off between
resolution and conversion time.
SET_OSR
[2:0]
000
001
010
011
100
101
110
111
SET_NELC[1:0]
01
10
19
37
35
69
67
133
131
261
259
517
515
1029
1027
2053
2051
4101
00
10
18
34
66
130
258
514
1026
11
73
137
265
521
1033
2057
4105
8201
Table 17-23. Normalized conversion time (TCONV ⋅fS) vs. SET_OSR[2:0] and
SET_NELC[1:0](normalized to sampling period 1/fS)
Resolution - n [Bits]
16.0
14.0
12.0
10.0
8.0
6.0
10
00
4.0
10.0
11
SET_NELC
01
100.0
1000.0
10000.0
Normalized Conversion Time - TCONV*fS [-]
Figure 17-7. Resolution vs. normalized conversion time for different SET_NELC[1:0]
17.7.7
Output Code Format
The ADC output code is a 16-bit word in two's complement format (see Table 17-24). For input voltages outside the
range, the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions smaller
than 16 bits, the non-significant bits are forced to the values shown in Table 17-25. The output code, expressed in
LSBs, corresponds to:
OUTADC = 216 ⋅
VIN , ADC OSR + 1
(LSB)
⋅
VREF
OSR
(Eq.17)
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17-14
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Recalling equation Eq. 9, this can be rewritten as:
OUTADC = 216 ⋅
VIN
VREF
⎛
V
⋅ ⎜⎜ GDTOT − GDoff TOT ⋅ REF
VIN
⎝
⎞ OSR + 1
⎟⎟ ⋅
OSR
⎠
(LSB) (Eq. 18)
where, from Eq. 10 and Eq. 11, the total PGA gain and offset are respectively:
GDTOT = GD3 ⋅ GD2 ⋅ GD1
(V/V)
and:
GDoff TOT = GDoff 3 + GD3 ⋅ GDoff 2
(V/V)
ADC Input
Voltage
VIN,ADC
% of
Full
Scale
(FS)
+2.49505V
+0.5⋅FS
+2.49497V
...
...
+76.145µV
0V
-76.145µV
...
...
...
0
...
...
-2.49505V
...
-2.49513V
-0.5⋅FS
Output in
LSBs
Output
Code
in Hex
15
+2 -1
=+32'767
+215-2
=+32'766
...
+1
0
-1
...
15
-2 -1
=-32'767
-215
=-32'768
7FFF
7FFE
...
0001
0000
FFFF
...
8001
8000
Table 17-24. Basic ADC Relationships (example for: VREF = 5V, OSR = 512, n = 16 bits)
SET_OSR
[2:0]
000
001
010
011
100
101
110
111
SET_NELC = 00
SET_NELC = 01
SET_NELC = 10
SET_NELC = 11
1000000000
10000000
100000
1000
10
-
100000000
1000000
10000
100
1
-
10000000
100000
1000
10
-
1000000
10000
100
1
-
Table 17-25. Last forced LSBs in conversion output registers for resolution settings smaller than 16
bits (n < 16) (RegAcOutMsb[7:0] & RegAcOutLsb[7:0])
The equivalent LSB size at the input of the PGA chain is:
LSB =
1 V REF
OSR
⋅
⋅
n
2 GDTOT OSR + 1
(V)
(Eq. 19)
Notice that the input voltage VIN,ADC of the ADC must satisfy the condition:
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17-15
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
VIN , ADC ≤
1
OSR
⋅ (V REFP − VREFN ) ⋅
2
OSR + 1
(V)
(Eq. 20)
to remain within the ADC input range.
17.7.8
Power Saving Modes
During low-speed operation, the bias current in the PGAs and ADC can be programmed to save power using the
control words IB_AMP_PGA[1:0] and IB_AMP_ADC[1:0] (see Table 17-26). If the system is idle, the PGAs and
ADC can even be disabled, thus, reducing power consumption to its minimum. This can considerably improve
battery lifetime.
ADC
PGA
[1:0]
Bias
Current
Bias
Current
00
01
10
11
x
1/4⋅IADC
1/2⋅IADC
3/4⋅IADC
IADC
x
x
00
01
10
11
x
1/4⋅IPGA
1/2⋅IPGA
3/4⋅IPGA
IPGA
IB_AMP_ADC
[1:0]
IB_AMP_PGA
Max. fS
[kHz]
62.5
125
250
500
62.5
125
250
500
Table 17-26. ADC & PGA power saving modes and maximum sampling frequency
17.8 Specifications and Measured Curves
This section presents measurement results for the acquisition chain. A summary table with circuit specifications
and measured curves are given.
17.8.1
Default Settings
Unless otherwise specified, the measurement conditions are the following:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Temperature TA = +25°C
VDD = +5V, GND = 0V, VREF = +5V, VIN = 0V
RC frequency fRC = 2MHz, sampling frequency fS = 500kHz
Offsets GDOff2 = GDOff3 = 0
Power operation: normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] = '11')
Resolution:
for n = 12 bits: OSR = 32 and NELCONV = 4
o for n = 16 bits: OSR = 512 and NELCONV = 2
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17-16
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
17.8.2
Specifications
Unless otherwise specified: Temperature TA = +25°C, VDD = +5V, GND = 0V, VREF = +5V, VIN = 0V, RC frequency fRC = 2MHz, sampling
frequency fS = 500kHz, Overall PGA gain GDTOT = 1, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IB_AMP_ADC[1:0] =
IB_AMP_PGA[1:0] = '11'). For resolution n = 12 bits: OSR = 32 and NELCONV = 4. For resolution n = 16 bits: OSR = 512 and NELCONV = 2.
VALUE
PARAMETER
UNITS
COMMENTS/CONDITIONS
MIN
TYP
MAX
ANALOG
INPUT
CHARACTERISTICS
+2.42
Gain = 1, OSR = 32 (Note 1)
-2.42
V
Differential Input Voltage Ranges
+24.2
Gain = 100, OSR = 32
-24.2
mV
VIN = (VINP - VINN)
+2.42
Gain = 1000, OSR = 32
-2.42
mV
Reference Voltage Range
VREF = (VREFP – VREFN)
PROGRAMMABLE
GAIN
AMPLIFIERS (PGA)
Total PGA Gain, GDTOT
PGA1 Gain, GD1
PGA2 Gain, GD2
PGA3 Gain, GD3
Gain Setting Precision (each stage)
Gain Temperature Dependence
Offset
PGA2 Offset, GDoff2
PGA3 Offset, GDoff3
Offset Setting Precision (PGA2 or 3)
Offset Temperature Dependence
Input Impedance
PGA1
PGA2, PGA3
Output RMS Noise
PGA1
PGA2
PGA3
ADC STATIC PERFORMANCE
Resolution, n
No Missing Codes
Gain Error
Offset Error
0.5
1
1
0
-3
-1
-127/12
-3
Throughput Rate (Continuous Mode),
1/TCONV
Nbr of Initialization Cycles, NINIT
Nbr of End Conversion Cycles, NEND
PGA Stabilization Delay
DIGITAL OUTPUT
ADC Output Data Coding
±0.5
±5
V
1000
10
10
127/12
+3
V/V
V/V
V/V
V/V
%
ppm/°C
+1
+127/12
+3
V/V
V/V
%
ppm/°C
1500
150
150
205
340
365
6
Integral Non-Linearity, INL
Resolution n = 16 Bits
Differential Non-Linearity, DNL
Resolution n = 16 Bits
Power Supply Rejection Ratio, PSRR
DYNAMIC PERFORMANCE
Sampling Frequency, fS
Conversion Time, TCONV
±0.5
±5
VDD
16
See Table 17-14
See Table 17-15
Step=1/12 V/V, See Table 17-17
Step=0.2 V/V, See Table 17-16
Step=1/12 V/V, See Table 17-18
(Note 2)
kΩ
kΩ
kΩ
PGA1 Gain = 1 (Note 3)
PGA1 Gain = 10 (Note 3)
Maximal gain (Note 3)
µV
µV
µV
(Note 4)
(Note 5)
(Note 6)
Bits
(Note 7)
(Note 8)
(Note 9)
n = 16 bits (Note 10)
±0.15
±1
% of FS
LSB
±1.0
LSB
(Note 11)
±0.5
78
72
LSB
dB
dB
(Note 12)
VDD = 5V ± 0.3V (Note 13)
VDD = 3V ± 0.3V (Note 13)
3
133
1027
3.76
0.49
0
0
2
5
OSR
kHz
cycles/fS
cycles/fS
kSps
kSps
cycles
cycles
cycles
n = 12 bits (Note 14)
n = 16 bits (Note 14)
n = 12 bits, fS = 500kHz
n = 16 bits, fS = 500kHz
(Note 15)
Binary Two’s Complement
See Table 17-24 and Table 17-25
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17-17
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Specifications (Cont’d)
PARAMETER
POWER SUPPLY
Voltage Supply Range, VDD
Analog
Quiescent
Current
Consumption, Total (IQ)
ADC Only
PGA1
PGA2
PGA3
Analog Power Dissipation
Normal Power Mode
3/4 Power Reduction Mode
1/2 Power Reduction Mode
1/4 Power Reduction Mode
TEMPERATURE
Specified Range
Operating Range
MIN
VALUE
TYP
MAX
+2.4
+5
+5.5
-40
-40
UNITS
V
720/620
250/190
165/150
130/120
175/160
µA
µA
µA
µA
µA
3.6/1.9
2.7/1.4
1.8/0.9
0.9/0.5
mW
mW
mW
mW
+85
+125
COMMENTS/CONDITIONS
Only Acquisition Chain
VDD = 5V/3V
VDD = 5V/3V
VDD = 5V/3V
VDD = 5V/3V
VDD = 5V/3V
All PGAs & ADC Active
VDD = 5V/3V (Note 16)
VDD = 5V/3V (Note 17)
VDD = 5V/3V (Note 18)
VDD = 5V/3V (Note 19)
°C
°C
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
=
GD1⋅GD2⋅GD3.
Maximum
input
voltage
is
given
by:
Gain
defined
as
overall
PGA
gain
GDTOT
VIN,MAX = ±(VREF/2)⋅(OSR/OSR+1).
Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1.
Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is fS =
512kHz. This figure must be multiplied by 2 for fS = 256kHz, 4 for fS = 128kHz. Input impedance is proportional to 1/fS.
See
model
of
Figure
17-18(a).
Figure
independent
from
PGA1
gain
and
sampling
frequency
fS.
See equation Eq. 21 to calculate equivalent input noise.
Figure independent on PGA2 gain and sampling frequency fS. See model of Figure 17-18(a). See equation Eq. 21 to calculate
equivalent input noise.
Figure independent on PGA3 gain and sampling frequency fS. See model of Figure 17-18(a) and equation Eq. 21 to calculate
equivalent input noise.
Resolution is given by n = 2⋅log2(OSR) + log2(NELCONV). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to
1, 2, 4 or 8.
If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data.
Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function
(with the offset error removed). (See Figure 17-19)
Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For ± 1 LSB offset, NELCONV must be ≥2.
INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds
over the full scale.
DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes.
Figures for Gains = 1 to 100. PSRR is defined as the amount of change in the ADC output value as the power supply voltage
changes.
Conversion time is given by: TCONV = (NELCONV ⋅ (OSR + 1) + 1) / fS. OSR can be set between 8 and 1024, in powers of 2. NELCONV can
be set to 1, 2, 4 or 8.
PGAs are reset after each writing operation to registers RegAcCfg1-5. The ADC must be started after a PGA or inputs commonmode stabilisation delay. This is done by writing bit Start several cycles after PGA settings modification or channel switching.
Delay between PGA start or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of
cycles. This delay does not apply to conversions made without the PGAs.
Nominal (maximum) bias currents in PGAs and ADC, i.e. IB_AMP_PGA[1:0] = ‘11’ and IB_AMP_ADC[1:0] = ‘11’.
Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘10’, IB_AMP_ADC[1:0] = ‘10’.
Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘01’, IB_AMP_ADC[1:0] = ‘01’.
Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘00’, IB_AMP_ADC[1:0] = ‘00’.
17.8.3
Linearity
17.8.3.1
Integral non-linearity
The integral non-linearity depends on the selected gain configuration. First of all, the non-linearity of the ADC (all
PGA stages bypassed) is shown in Figure 17-8.
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XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Figure 17-8. Integral non-linearity of the ADC (PGA disabled, reference voltage of 4.8V)
The different PGA stages have been designed to find the best compromise between the noise performance, the
integral non-linearity and the power consumption. To obtain this, the first stage has the best noise performance and
the third stage the best linearity performance. For large input signals (small PGA gains, i.e. up to about 50), the
noise added by the PGA is very small with respect to the input signal and the second and third stage of the PGA
should be used to get the best linearity. For small input signals (large gains, i.e. above 50), the noise level in the
PGA is important and the first stage of the PGA should be used.
The following figures give the non-linearity for different gain settings of the PGA, selecting the appropriate stage to
get the best noise and linearity performance. Figure 17-9 shows the non-linearity when the third stage is used with
a gain of 1. It is of course not very useful to use the PGA with a gain of 1 unless it is used to compensate offset. By
increasing the gain, the integral non-linearity becomes even smaller since the signal in the amplifiers reduces.
Figure 17-10 shows the non-linearity for a gain of 2. Figure 17-11 shows the non-linearity for a gain of 5. Figure
17-12 shows the non-linearity for a gain of 10. By comparing these figures to Figure 17-8, it can be seen that the
third stage of the PGA does not add significant integral non-linearity.
Figure 17-13 shows the non-linearity for a gain of 20 and Figure 17-14 shows the non-linearity for a gain of 50. In
both cases the PGA2 is used at a gain of 10 and the remaining gain is realized by the third stage. It can be seen
again that the second stage of the PGA does not add significant non-linearity.
For gains above 50, the first stage PGA1 should be selected instead of PGA2. Although the non-linearity in the first
stage of the PGA is larger than in stage 2 and 3, the gain in stage 3 is now sufficiently high so that the non-linearity
of the first stage does become negligible as is shown in Figure 17-15 for a gain of 100. Therefore, the first stage is
preferred over the second stage since it has less noise.
Increasing the gain further up to 1000 will further increase the linearity since the signal becomes very small in the
first two stages. The signal is full scale at the output of stage 3 and as shown in Figure 17-9 to Figure 17-12, this
stage has very good linearity.
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17-19
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Figure 17-9. Integral non-linearity of the ADC and with gain of 1 (PGA1 and PGA2 disabled, PGA3=1,
reference voltage of 5V)
Figure 17-10. Integral non-linearity of the ADC and gain of 2 (PGA1 and PGA2 disabled, PGA3=2
reference voltage of 5V)
Figure 17-11. Integral non-linearity of the ADC and gain of 5 (PGA1 and PGA2 disabled, PGA3=5,
reference voltage of 5V)
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17-20
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Figure 17-12. Integral non-linearity of the ADC and gain of 10 (PGA1 and PGA2 disabled, PGA3=10,
reference voltage of 5V)
Figure 17-13. Integral non-linearity of the ADC and gain of 20 (PGA1 and PGA2=10, PGA3=2,
reference voltage of 5V)
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17-21
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Figure 17-14. Integral non-linearity of the ADC and gain of 50 (PGA1 disabled, PGA2=10, PGA3=5,
reference voltage of 5V)
Figure 17-15. Integral non-linearity of the ADC and gain of 100 (PGA1=10 and PGA3=10, PGA2
disabled, reference voltage of 5V)
17.8.3.2
Differential non-linearity
The differential non-linearity is generated by the ADC. The PGA does not add differential non-linearity. Figure
17-16 shows the differential non-linearity.
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17-22
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Figure 17-16. Differential non-linearity of the ADC converter.
17.8.4
Noise
Ideally, a constant input voltage VIN should result in a constant output code. However, because of circuit noise, the
output code may vary for a fixed input voltage. Thus, a statistical analysis on the output code of 1200 conversions
for a constant input voltage was performed to derive the equivalent noise levels of PGA1, PGA2, and PGA3. The
extracted rms output noise of PGA1, 2, and 3 are given in Table 17-27: standard output deviation and output rms
noise voltage. Figure 17-17 shows the distribution for the ADC alone (PGA1, 2, and 3 bypassed). Quantitative
noise is dominant in this case, and, thus, the ADC thermal noise is below 16 bits.
The simple noise model of Figure 17-18(a) is used to estimate the equivalent input referred rms noise VN,IN of the
acquisition chain in the model of Figure 17-18(b). This is given by the relationship:
V N , IN =
2
(V N 1 / GD1 ) 2 + (V N 2 /(GD1 ⋅ GD2 )) 2 + (V N 3 /(GD1 ⋅ GD2 ⋅ GD3 )) 2
(OSR ⋅ N ELCONV )
(V2rms)
(Eq. 21)
where VN1, VN2, and VN3 are the output rms noise figures of Table 17-27, GD1, GD2, and GD3 are the PGA gains of
stages 1 to 3 respectively. As shown in this equation, noise can be reduced by increasing OSR and NELCONV
(increases the ADC averaging effect, but reduces noise).
Parameter
Standard deviation at
ADC output (LSB)
Output rms noise (µV)
1
PGA1
PGA2
PGA3
0.85
1.4
1.5
205 (VN1)
340 (VN2)
365 (VN3)
Note: see noise model of Figure 17-18 and equation Eq. 21.
Table 17-27. PGA noise measurements (n = 16 bits, OSR = 512, NELCONV = 2, VREF = 5V)
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XE8802 Sensing Machine Data Acquisition MCU
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Occurences
[% of total samples]
80
60
40
20
0
-5
-4
-3
-2
-1
0
1
2
3
4
5
Output Code Deviation From Mean Value [LSB]
Figure 17-17. ADC noise (PGA1, 2 & 3 bypassed, OSR=512,NELCONV=2)
fS
PGA1
VN1
GD1
PGA2
VN2
GD2
PGA3
VN3
GD3
ADC
(a)
fS
PGA1
PGA2
PGA3
GD1
GD2
GD3
VN,IN
ADC
(b)
Figure 17-18. (a) Simple noise model for PGAs and ADC
and (b) total input referred noise
As an example, consider the system where: GD2 = 10 (GD1 = 1; PGA3 bypassed), OSR = 512, NELCONV = 2, VREF =
5V. In this case, the noise contribution VN1 of PGA1 is dominant over that of PGA2. Using equation Eq. 21, we get:
VN,IN = 6.4µV (rms) at the input of the acquisition chain, or, equivalently, 0.85 LSB at the output of the ADC.
Considering a 0.2V (rms) maximum signal amplitude, the signal-to-noise ratio is 90dB.
Implementing a software filter can also reduce noise. By taking an average on a number of subsequent
measurements, the apparent noise is reduced by the square root of the number of measurement used to make the
average.
17.8.5
Gain Error and Offset Error
Gain error is defined as the amount of deviation between the ideal transfer function (theoretical equation Eq. 18)
and the measured transfer function (with the offset error removed).
The actual gain of the different stages can vary relating to the fabrication tolerances of the different elements.
Although these tolerances are specified to a maximum of ±3%, most of the time they will be around ±0.5%.
Moreover, the tolerances between the different stages are not correlated and the probability of getting the maximal
error in the same direction in all stages is very low. Finally, the software can calibrate these gain errors at the same
time as the gain errors of the sensor for instance.
Figure 17-19 shows gain error drift vs. temperature for different PGA gains. The curves are expressed in % of FullScale Range (FSR) normalized to 25°C.
© Semtech 2006
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17-24
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The offset of the ADC
and the PGA1 stage are completely suppressed if NELCONV > 1.
The measured offset drift vs. temperature curves for different PGA gains are depicted in Figure 17-20. The output
offset error, expressed in LSB for 16-bit setting, is normalized to 25°C. Notice that if the ADC is used alone, the
output offset error is below ±1 LSB and has no drift.
NORMALIZED TO 25°C
Gain Error [% of FSR]
0.2
0.1
0.0
-0.1
1
5
20
100
-0.2
-0.3
-0.4
-50
-25
0
25
50
75
100
Temperature [°C]
Figure 17-19. Gain error vs. temperature for different PGA gains
Output Offset Error [LSB]
NORMALIZED TO 25°C
100
1
5
20
100
80
60
40
20
0
-20
-40
-50
-25
0
25
50
75
100
Temperature [°C]
Figure 17-20. Offset error vs. temperature for different PGA gains
17.8.6
Power Consumption
Figure 17-21 plots the variation of quiescent current consumption with supply voltage VDD, as well as the
distribution between the 3 PGA stages and the ADC (see Table 17-28). As shown in Figure 17-22, if lower
sampling frequency is used, the quiescent current consumption can be lowered by reducing the bias currents of the
PGAs and the ADC with registers IB_AMP_PGA [1:0] and IB_AMP_ADC [1:0]. (In Figure 17-22,
IB_AMP_PGA/ADC[1:0] = '11', '10', '00' for fS = 500, 250, 62.5kHz respectively.)
Quiescent current consumption vs. temperature is depicted in Figure 17-23, showing a relative increase of nearly
40% between -45 and +85°C. Figure 17-24 shows the variation of quiescent current consumption for different
frequency settings of the internal RC oscillator. It can be seen that the quiescent current varies by about 20%
between 100kHz and 2MHz.
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17-25
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
800
Quiescent Current - IQ [µ A]
700
PGA1, 2 & 3 + ADC
600
500
PGA1 & 2 + ADC
400
PGA1 + ADC
300
200
No PGAs, ADC only
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage - VDDA [V]
Figure 17-21. Quiescent current consumption vs. supply voltage
800
Sampling Frequency fS : 500kHz
Quiescent Current - IQ [µ A]
700
600
250kHz
500
400
300
62.5kHz
200
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage - VDDA [V]
Figure 17-22. Quiescent current consumption vs. supply voltage for different sampling frequencies
20
Relative Quiescent Current Change
IQ / IQ,25°C [%]
Quiescent Current - IQ [µ A]
900
850
800
750
700
650
600
550
15
10
5
0
-5
-10
-15
-20
-25
500
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature [°C]
Temperature [°C]
(a)
(b)
Figure 17-23. (a) Absolute and (b) relative change inquiescent current consumption vs. temperature
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17-26
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Supply
VDD = 5V
VDD = 3V
ADC
PGA1
PGA2
PGA3
TOTAL
Unit
250
190
165
150
130
120
175
160
720
620
µA
µA
Table 17-28. Typical quiescent current distributions in acquisition chain
15
850
10
800
Quiescent Current - IQ [µ A]
Relative Quiescent Current Change
∆ IQ / IQ,2MHz [%]
(n = 16 bits, fS = 500kHz)
5
0
-5
-10
-15
750
700
650
600
550
500
-20
0
500
1000
1500
2000
2500
3000
0
3500
500
1000
1500
2000
2500
3000
3500
Frequency - fRC [kHz]
Frequency - fRC [kHz]
(a)
(b)
Figure 17-24. (a) Absolute and (b) relative change in quiescent curent consumption vs. RC oscillator
frequency (all PGAs active, VDD = 5V)
17.8.7
Power Supply Rejection Ratio
Figure 17-25 shows power supply rejection ratio (PSRR) at a 3V and a 5V supply voltage, and for various PGA
gains. PSRR is defined as the ratio (in dB) of voltage supply change (in V) to the change in the converter output (in
V). PSRR depends on both PGA gain and supply voltage VDD.
105
VDD=3V
VDD=5V
100
PSRR [dB]
95
90
85
80
75
70
65
60
1
5
10
20
100
PGA Gain [V/V]
Figure 17-25. Power supply rejection ratio (PSRR)
Supply
VDD = 5V
VDD = 3V
GAIN = 1
GAIN =5
GAIN = 10
GAIN = 20
GAIN =100
Unit
79
72
78
79
100
90
99
90
97
86
dB
dB
Table 17-29. PSRR (n = 16 bits, VIN = VREF = 2.5V, fS = 500kHz)
© Semtech 2006
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17-27
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
17.9 Application Hints
17.9.1
Input Impedance
The PGAs of the acquisition chain employ switched-capacitor techniques. For this reason, while a conversion is
done, the input impedance on the selected channel of the PGAs is inversely proportional to the sampling frequency
fS and to stage gain as given in equation 22.
Z in ≥
768 ⋅ 10 9 ΩHz
f s ⋅ gain
(Eq. 22)
The input impedance observed is the input impedance of the first PGA stage that is enabled or the input
impedance of the ADC if all three stages are disabled.
PGA1 (with a gain of 10), PGA2 (with a gain of 10) and PGA3 (with a gain of 10) each have a minimum input
impedance of 150kΩ at fS = 512kHz (see Specification Table). Larger input impedance can be obtained by
reducing the gain and/or by reducing the sampling frequency. Therefore, with a gain of 1 and a sampling frequency
of 100kHz, Zin > 7.6MΩ.
The input impedance on channels that are not selected is very high (>100MΩ).
17.9.2
PGA Settling or Input Channel Modifications
PGAs are reset after each writing operation to registers RegAcCfg1-5. Similarly, input channels are switched after
modifications of AMUX[4:0] or VMUX. To ensure precise conversion, the ADC must be started after a PGA or
inputs common-mode stabilization delay. This is done by writing bit START several cycles after modification of PGA
settings or channel switching. Delay between PGA start or input channel switching and ADC start should be
equivalent to OSR (between 8 and 1024) number of cycles. This delay does not apply to conversions made without
the PGAs.
If the ADC is not settled within the specified period, there is probably an input impedance problem (see previous
section).
17.9.3
PGA Gain & Offset, Linearity and Noise
Hereafter are a few design guidelines that should be taken into account when using the ZoomingADC™:
1)
2)
3)
4)
4)
5)
6)
Keep in mind that increasing the overall PGA gain, or "zooming" coefficient, improves linearity but
degrades noise performance.
Use the minimum number of PGA stages necessary to produce the desired gain ("zooming") and offset.
Bypass unnecessary PGAs.
For high gains (>50), use PGA stage 1. For low gains (<50) use stages 2 and 3.
For the lowest noise, set the highest possible gain on the first (front) PGA stage used in the chain. For
example, in an application where a gain of 20 is needed, set the gain of PGA2 to 10, set the gain of PGA3
to 2.
For highest linearity and lowest noise performance, bypass all PGAs and use the ADC alone (applications
where no "zooming" is needed); i.e. set ENABLE[3:0] = '0001'.
For low-noise applications where power consumption is not a primary concern, maintain the largest bias
currents in the PGAs and in the ADC; i.e. set IB_AMP_PGA[1:0] = IB_AMP_ADC[1:0] = '11'.
For lowest output offset error at the output of the ADC, bypass PGA2 and PGA3. Indeed, PGA2 and
PGA3 typically introduce an offset of about 5 to 10 LSB (16 bit) at their output. Note, however, that the
ADC output offset is easily calibrated out by software.
© Semtech 2006
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17-28
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
17.9.4
Frequency Response
The incremental ADC is an over-sampled converter with two main blocks: an analog modulator and a low-pass
digital filter. The main function of the digital filter is to remove the quantitative noise introduced by the modulator. As
shown in Figure 17-26, this filter determines the frequency response of the transfer function between the output of
the ADC and the analog input VIN. Notice that the frequency axes are normalized to one elementary conversion
period OSR/fS. The plots of Figure 17-26 also show that the frequency response changes with the number of
elementary conversions NELCONV performed. In particular, notches appear for NELCONV ≥ 2. These notches occur at:
f NOTCH (i) =
i ⋅ fS
OSR ⋅ N ELCONV
for i = 1,2,..., ( N ELCONV − 1)
(Hz)
(Eq. 23)
and are repeated every fS/OSR.
1.2
1
Normalized Magnitude [-]
Normalized Magnitude [-]
Information on the location of these notches is particularly useful when specific frequencies must be filtered out by
the acquisition system. For example, consider a 5Hz-bandwidth, 16-bit sensing system where 50Hz line rejection is
needed. Using the above equation and the plots below, we set the 4th notch for NELCONV = 4 to 50Hz, i.e.
1.25⋅fS/OSR = 50Hz. The sampling frequency is then calculated as fS = 20.48kHz for OSR = 512. Notice that this
choice yields also good attenuation of 50Hz harmonics.
NELCONV = 1
0.8
0.6
0.4
0.2
0
1.2
1
N ELCONV = 2
0.8
0.6
0.4
0.2
0
0
1
2
3
4
0
1.2
1
NELCONV = 4
0.8
0.6
0.4
0.2
0
0
1
2
3
1
2
3
4
Normalized Frequency - f *(OSR/fS) [-]
Normalized Magnitude [-]
Normalized Magnitude [-]
Normalized Frequency - f *(OSR/fS) [-]
4
1.2
N ELCONV = 8
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
Normalized Frequency - f *(OSR/fS) [-]
Normalized Frequency - f *(OSR/fS) [-]
Figure 17-26. Frequency response: normalized magnitude vs. frequency for different NELCONV
17.9.5
Power Reduction
The ZoominADC™ is particularly well suited for low-power applications. When very low power consumption is of
primary concern, such as in battery operated systems, several parameters can be used to reduce power
consumption as follows:
1)
2)
3)
Operate the acquisition chain with a reduced supply voltage VDD.
Disable the PGAs which are not used during analog-to-digital conversion with ENABLE[3:0].
Disable all PGAs and the ADC when the system is idle and no conversion is performed.
© Semtech 2006
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17-29
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
4)
5)
Use lower bias currents in the PGAs and the ADC using the control words IB_AMP_PGA[1:0] and
IB_AMP_ADC[1:0]. (This reduces the maximum sampling frequency according to Table 17-26.)
Reduce internal RC oscillator frequency and/or sampling frequency.
Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower
maximum sampling speed.
© Semtech 2006
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17-30
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
18.
18.1
18.2
18.3
Voltage
Multiplier
FEATURES
OVERVIEW
CONTROL PART REGISTERS
18-2
18-2
18-2
© Semtech 2006
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18-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
18.1 Features
•
•
Generates a voltage that is higher or equal to the supply voltage, but at maximum 4.8 V
Can be easily enabled or disabled
18.2 Overview
en_vmult
switch power
regs
switched
analog
(other blocks)
VMULT
ck_vmult
(analog)
prescaler
Vmult
(capacitor only required
when enabled)
Vmult_dl
Figure 17-1 : Structure of the Vmult peripheral
The Vmult block generates a voltage (called “Vmult”) that is higher or equal to the supply voltage. This output
voltage is intended for use in analog switch drivers, for example in the ADC and PGA block.
• In normal use its value is 4.8 V, this voltage is available on the pad Vmult.
• When the main voltage is below 2.6 V, Vmult is twice the main voltage minus 0.4 V.
• When the main voltage is above 4.8 V, Vmult remains 4.8 V but the internal voltage intended for the analog
switch drivers equal the main voltage.
The voltage multiplier should be on (bit Enable in RegVmultCfg0) when using switched analog blocks, like ADC,
DAC or analog properties of Port B when Vbat is below 3V. The source clock of Vmult is selected from Fin[1:0] in
RegVmultCfg0. It is strongly recommended to use the same Fin bit code as in the ADC.
The external capacitor on the pin VMULT has to be connected if the block is enabled. The size of the capacitor
has to be 2nF ± 50%.
18.3 Control part Registers
There is only one register in the Vmult. Table 18-1 describes the bits in the register.
Pos.
2
RegVmultCfg0
Enable
rw
rw
Reset
0
1-0
Fin
rw
0
Function
enable of the vmult
‘1’ : enabled
‘0’ : disabled
system clock division factor
‘00’ : 1/2,
‘01’ : 1/4,
‘10’ : 1/16,
‘11’ : 1/64
Table 18-1. RegVmultCfg0
© Semtech 2006
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18-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
19.
19.1
19.2
19.3
19.4
19.4.1
19.4.2
19.4.3
19.4.4
19.5
19.5.1
19.5.2
19.5.3
19.5.4
19.6
19.6.1
19.6.2
19.7
19.7.1
19.7.2
19.8
19.8.1
19.8.2
19.8.3
19.8.4
LCD
Driver
FEATURES ......................................................................................................................................... 19-2
OVERVIEW......................................................................................................................................... 19-2
REGISTER MAP .................................................................................................................................. 19-3
BASIC LCD CAPABILITIES .................................................................................................................... 19-6
Direct Drive Mode ............................................................................................................................ 19-7
1:2 Multiplex scheme ....................................................................................................................... 19-9
1:3 Multiplex scheme ..................................................................................................................... 19-11
1:4 Multiplex scheme ..................................................................................................................... 19-13
ADVANCED LCD FEATURES .............................................................................................................. 19-15
Register usage .............................................................................................................................. 19-15
Sleep mode or blinking mode ........................................................................................................ 19-15
LCD frame frequency selection...................................................................................................... 19-16
Voltage generation......................................................................................................................... 19-17
PARALLEL I/O PORT CAPABILITIES...................................................................................................... 19-21
Parallel port function ...................................................................................................................... 19-21
parallel port voltage ....................................................................................................................... 19-22
PARTIAL LCD DRIVER / PARTIAL PARALLEL I/O PORT............................................................................ 19-24
Single low impedance voltage for V3 of LCD and digital I/O .......................................................... 19-24
Different voltage for V3 of LCD and digital I/O ............................................................................... 19-26
SPECIFICATIONS .............................................................................................................................. 19-27
pad_lcd_io used in LCD mode....................................................................................................... 19-27
pad_lcd_io used in digital I/O mode ............................................................................................... 19-27
voltage reference ........................................................................................................................... 19-28
LCD multiplier/divider..................................................................................................................... 19-28
© Semtech 2006
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19-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
19.1 Features
•
•
•
•
•
•
•
•
•
Supports direct drive for 32 segments.
Supports multiplexed drive for up to 120 segments
Multiplex 1/2, 1/3 and 1/4.
Possibility to use pads as an input/output port or as LCD driver pin.
Multiple frame frequencies.
Sleep mode.
On chip low-power voltage generation.
LCD driver voltage is independent from the circuit supply voltage.
Parallel IO with voltage different from the circuit supply voltage.
19.2 Overview
S E G ME N TS
W AV E F O R M
G E N E R AT O R
L C D P E R IP H
D IS P L AY
MEMORY
1 6 x 8 b it s
COMS
W AV E F O R M
G E N E R AT O R
LC D PAD S
ts
I/ O P O R T
I/ O p o rt c o n t r o l
r e g is t e rs
LCD C O N TRO L
AN D M O D E
R E G IS T E R
V1
VG E N
CO NTR O L
R E G IS T E R
V2
V3
VG E N PA D S
Figure 19-1: General Structure
The LCD driver generates all waveforms to drive the display. The user has only to set a 0 (segment off) or a 1
(segment on) in the bit location corresponding to the segment. The LCD driver supports the wave form generation
for different multiplexing schemes: direct drive (no multiplexing), multiplexing by 2, by 3 and by 4. The frame
frequency is software programmable. Low power on-chip voltage generation is provided for each of the different
multiplexing schemes. The LCD driver voltage is completely independent from the circuit supply voltage: the LCD
driver voltage can be below or above the circuit supply voltage. All or part of the driver can be configured as a
© Semtech 2006
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19-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
general-purpose parallel IO-port. When used as a parallel port, it can be connected to circuits with a different
supply voltage.
Section 19.4 describes the basic functions of the LCD driver using the on-chip voltage generator. Section 19.5
describes more advanced the features of the LCD driver and especially different ways of generating the voltage for
the LCD. Section 19.6 describes how to use the peripheral as a general-purpose parallel IO-port. Section 19.7
shows how to partition when used as a partial LCD driver and partial IO port. Finally, the electrical specifications of
the driver are given in section 19.8.
19.3 Register map
There are thirty-six registers in the LCD driver, namely RegVgenCfg0, RegLcdOn, RegLcdSe, RegLcdClkFrame,
RegLcdDataN (0≤N≤15), RegPLcdInN (0≤N≤3), RegPLcdOutN (0≤N≤3), RegPLcdDirN (0≤N≤3) and
RegPLcdPullupN (0≤N≤3). Table 19-2 to Table 19-11 show the mapping of control bits and functionality of these
registers while Table 19-1 gives the default address of these thirty-six registers.
Register name
Vgen registers
RegVgenCfg0
Control registers
RegLcdOn
RegLcdSe
RegLcdClkFrame
LCD registers
RegLcdData0
RegLcdData1
RegLcdData2
RegLcdData3
RegLcdData4
RegLcdData5
RegLcdData6
RegLcdData7
RegLcdData8
RegLcdData9
RegLcdData10
RegLcdData11
RegLcdData12
RegLcdData13
RegLcdData14
RegLcdData15
Port Registers
RegPLcdOut0
RegPLcdOut1
RegPLcdOut2
RegPLcdOut3
RegPLcdDir0
RegPLcdDir1
RegPLcdDir2
RegPLcdDir3
RegPLcdPull0
RegPLcdPull1
RegPLcdPull2
RegPLcdPull3
RegPLcdIn0
RegPLcdIn1
RegPLcdIn2
RegPLcdIn3
Table 19-1: LCD registers default addresses
© Semtech 2006
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19-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
RegVgenCfg0
RW
reset
7-6
5-4
-VgenClkSel
r
rw
00
10
nresetglobal
3
VgenOff
rw
1 nresetglobal
2
VgenMode
rw
0 nresetglobal
1
0
VgenStdb
VgenRefEn
rw
rw
0 nresetglobal
0 nresetglobal
function
Unused
Voltage generator frequency selection.
00 – 256 Hz
01 – 512 Hz
10 – 1 kHz
11 – 2 kHz
Voltage generator disable signal.
0 – enabled
1 – disabled
Mode selection.
0 – 1/3 bias
1 – 1/2 bias
Stand-by mode
Internal 1.2V voltage reference enable.
0 – disabled
1 – enabled
Table 19-2: RegVgenCfg0
pos.
7-3
2
RegLcdOn
LcdSleep
Rw
rw
Reset
00000
1 nresetglobal
1-0
Function
LcdMux
rw
00 nresetglobal
1 = stop operating
0 = continue operating
00 = direct drive
01 = 1:2 mux drive
10 = 1:3 mux drive
11 = 1:4 mux drive
Table 19-3: RegLcdOn
pos.
7
RegLcdSe
LcdSe3
rw
rw
Reset
1 nresetglobal
6
LcdSe7
rw
1 nresetglobal
5
LcdSe11
rw
1 nresetglobal
4
LcdSe15
rw
1 nresetglobal
3
LcdSe19
rw
1 nresetglobal
2
LcdSe23
rw
1 nresetglobal
1
LcdSe27
rw
1 nresetglobal
0
LcdSe31
rw
1 nresetglobal
Function
1 = pins pad_lcd_io(0-3) have LCD drive function
0 = pins pad_lcd_io(0-3) have digital function
1 = pins pad_lcd_io(4-7) have LCD drive function
0 = pins pad_lcd_io(4-7) have digital function
1 = pins pad_lcd_io(8-11) have LCD drive function
0 = pins pad_lcd_io(8-11) have digital function
1 = pins pad_lcd_io(12-15) have LCD drive function
0 = pins pad_lcd_io(12-15)have digital function
1 = pins pad_lcd_io(16-19) have LCD drive function
0 = pins pad_lcd_io(16-19) have digital function
1 = pins pad_lcd_io(20-23) have LCD drive function
0 = pins pad_lcd_io(20-23) have digital function
1 = pins pad_lcd_io(24-27) have LCD drive function
0 = pins pad_lcd_io(24-27) have digital function
1 = pins pad_lcd_io(28-31) have LCD drive function
0 = pins pad_lcd_io(28-31) have digital function
Table 19-4: RegLcdSe
© Semtech 2006
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19-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7-5
RegLcdClkFrame
LcdDivFreq
rw
rw
reset
000
nresetglobal
4-2
1-0
Reserved
LcdFreq
rw
000
00
nresetglobal
Function
000 = LcdFreq
001 = LcdFreq / 2
010 = LcdFreq / 3
011 = LcdFreq / 4
100 = LcdFreq / 5
101 = LcdFreq / 6
110 = LcdFreq / 7
111 = LcdFreq / 8
00 = 512 Hz
01 = 1024 Hz
10 = 2048 Hz
11 = 4096 Hz
Table 19-5: RegLcdClkFrame
Pos.
7
6
5
4
3
2
1
0
RegLcdDataN
LcdDataN[7]
LcdDataN[6]
LcdDataN[5]
LcdDataN[4]
LcdDataN[3]
LcdDataN[2]
LcdDataN[1]
LcdDataN[0]
Rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
Description
Segment[3] value in 1:4 MUX
Segment[2] value in 1:3 MUX
Segment[1] value in 1:2 MUX
Segment[0] value in DD
Segment[3] value in 1:4 MUX
Segment[2] value in 1:3 MUX
Segment[1] value in 1:2 MUX
Segment[0] value in DD
Map Pin
pad_lcd_io[2N+1]
pad_lcd_io[2N]
Table 19-6: RegLcdDataN with 0≤N≤14
Pos.
7
6
5
4
3
2
1
0
RegLcdData15
LcdData15[7]
LcdData15[6]
LcdData15[5]
LcdData15[4]
LcdData15[3]
LcdData15[2]
LcdData15[1]
LcdData15[0]
Rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
Description
Map Pin
--Segment[1] value in 1:2 MUX
Segment[0] value in DD
-Segment[2] value in 1:3 MUX
Segment[1] value in 1:2 MUX
Segment[0] value in DD
pad_lcd_io[31]
pad_lcd_io[30]
Table 19-7: RegLcdData15
Pos.
7
6
5
4
3
2
1
0
RegPLcdInN
PLcdInN[7]
PLcdInN[6]
PLcdInN[5]
PLcdInN[4]
PLcdInN[3]
PLcdInN[2]
PLcdInN[1]
PLcdInN[0]
Rw
r
r
r
r
r
r
r
r
Reset
Description
x
x
x
x
x
x
x
x
pad_lcd_io[8N+7] input value
pad_lcd_io[8N+6] input value
pad_lcd_io[8N+5] input value
pad_lcd_io[8N+4] input value
pad_lcd_io[8N+3] input value
pad_lcd_io[8N+2] input value
pad_lcd_io[8N+1] input value
pad_lcd_io[8N+0] input value
Table 19-8: RegPLcdInN with 0≤N≤3
© Semtech 2006
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19-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Pos.
7
6
5
4
3
2
1
0
RegPLcdOutN
PLcdOuN[7]
PLcdOutN[6]
PLcdOutN[5]
PLcdOutN[4]
PLcdOutN[3]
PLcdOutN[2]
PLcdOutN[1]
PLcdOutN[0]
Rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
Description
pad_lcd_io[8N+7] output value
pad_lcd_io[8N+6] output value
pad_lcd_io[8N+5] output value
pad_lcd_io[8N+4] output value
pad_lcd_io[8N+3] output value
pad_lcd_io[8N+2] output value
pad_lcd_io[8N+1] output value
pad_lcd_io[8N+0] output value
Table 19-9: RegPLcdOutN with 0≤N≤3
Pos.
7
6
5
4
3
2
1
0
RegPLcdDirN
PLcdDirN[7]
PLcdDirN[6]
PLcdDirN[5]
PLcdDirN[4]
PLcdDirN[3]
PLcdDirN[2]
PLcdDirN[1]
PLcdDirN[0]
Rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
Description
pad_lcd_io[8N+7] direction (0=input)
pad_lcd_io[8N+6] direction (0=input)
pad_lcd_io[8N+5] direction (0=input)
pad_lcd_io[8N+4] direction (0=input)
pad_lcd_io[8N+3] direction (0=input)
pad_lcd_io[8N+2] direction (0=input)
pad_lcd_io[8N+1] direction (0=input)
pad_lcd_io[8N+0] direction (0=input)
Table 19-10: RegPLcdDirN with 0≤N≤3
Pos.
7
6
5
4
3
2
1
0
RegPLcdPullupN
PLcdPullupN[7]
PLcdPullupN[6]
PLcdPullupN[5]
PLcdPullupN[4]
PLcdPullupN[3]
PLcdPullupN[2]
PLcdPullupN[1]
PLcdPullupN[0]
Rw
rw
rw
rw
rw
rw
rw
rw
rw
Reset
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
0 nresetpconf
Description
pullup for pad_lcd_io[8N+7] (1=active)
pullup for pad_lcd_io[8N+6] (1=active)
pullup for pad_lcd_io[8N+5] (1=active)
pullup for pad_lcd_io[8N+4] (1=active)
pullup for pad_lcd_io[8N+3] (1=active)
pullup for pad_lcd_io[8N+2] (1=active)
pullup for pad_lcd_io[8N+1] (1=active)
pullup for pad_lcd_io[8N+0] (1=active)
Table 19-11: RegPLcdPullupN with 0≤N≤3
19.4 Basic LCD capabilities
This section shows how to use the LCD driver. For each multiplexing configuration it gives a basic example
explaining how to set-up the driver, the generated waveforms, how to connect the display and how to use the onchip voltage generator. Other connection schemes and more advanced control functions will be given in the next
section.
The LCD module generates the timing control to drive a static or multiplexed LCD panel, with support for up to 32
segment lines multiplexed with up to four common lines. The table below summarises the multiplexing scheme for
LCD operation.
Multiplex scheme
direct drive (DD)
1:2
1:3
1:4
Max #segments
32
32 x 2
31 x 3
30 x 4
Table 19-12: Multiplexing Scheme
© Semtech 2006
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19-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
19.4.1
Direct Drive Mode
With direct drive mode, each pad_lcd_io pin drives one segment of the display. In this mode, up to 32 segments of
the display can be connected directly to the pad_lcd_io[31:0] pins. The common (or backplane) node is to be
connected to pad_lcd_com[0]. This connection is shown in Figure 19-2.
pad_vgen_vb
pad_lcd_vr1
pad_lcd_vr2
pad_vgen_v3
pad_vgen_v2
1.2V voltage
reference
pad_vgen_v1
C aux
Clcd1
VGEN
Clcd2
Clcd3
pad_vgen_va
pad_lcd_io[31:0]
SEGMENTS
LCD DISPLAY
pad_lcd_com1
pad_lcd_com0
COM0
Figure
19-2: LCD with direct drive and on-chip voltage generation.
Lots of different configurations for the voltage generation can be used. Figure 19-2 shows the connections and
external elements that are required if the display is to be driven from V3=3.6V independently from the circuit supply
voltage. Other possible configurations are given in section 19.5.4. The recommended value for the external
elements is 470nF (see also section 19.5.4.1).
To operate the driver in this configuration, the registers should be loaded with the values in Table 19-13.
Register
RegVgenCfg0
RegLcdOn
RegLcdSe
RegLcdClkFrame
Contents[7:0]
xx110001
xxxxx000
11111111
100xxx00
Table 19-13. Register contents for direct drive example
© Semtech 2006
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19-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
V3
pad_lcd_com0
pad_lcd_com0 - pad_lcd_io[0] (off)
V0
V3
V0
pad_lcd_io[1]
pad_lcd_com0 - pad_lcd_io[1] (on)
V0
V3
V3
V0
pad_lcd_io[0]
-V3
V0
Figure 19-3: Direct Drive mode waveforms
The voltage generator has to be configured for the use of the internal reference (VgenRefEn=1 in RegVgenCfg0).
The generator has to run (VgenOff=0 and VgenStdb=0 in RegVgenCfg0). It has to multiply by 3 (VgenMode=0 in
RegVgenCfg0) and the generator output impedance is set to minimum (VgenClkSel=11 in RegVgenCfg0).
The LCD driver is set to direct drive (LcdMux=00 in RegLcdOn) and the waveform generator is enabled
(LcdSleep=0 in RegLcdOn). All pads are set into the LCD driver mode by setting all bits of register RegLcdSe to
1. To select a frame rate of about 50Hz, set the bits LcdFreq=00 and LcdDivFreq=100 in RegLcdClkFrame. Note
that the precision of the frame frequency depends on the selected clock source (see clock block documentation).
The 32 segments are on or off depending on the bits set in the registers RegLcdDataN. Only the bits 0 and 4 of
these registers are used in direct drive. All other bits are don’t care. Figure 19-3 shows the generated waveforms
for two segments. Segment0 is off (LcdData0[0]=0 in RegLcdData0) and segment1 is on (LcdData0[4]=1 in
RegLcdData0). The figure shows on the left side the waveforms on the circuit pins, in the middle the segment
status and on the right the voltage on the segment (difference between the pad_lcd_io pin and pad_lcd_com0 pin).
© Semtech 2006
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19-8
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
19.4.2
1:2 Multiplex scheme
With the 1:2 multiplex scheme, each pad_lcd_io pin drives two segments of the display. The segments of the
display are connected to the pad_lcd_io[31:0] pins. The common (or backplane) nodes are to be connected to
pad_lcd_com0 and pad_lcd_com1. This connection is shown in Figure 19-4.
pad_vgen_vb
pad_lcd_vr1
pad_lcd_vr2
pad_vgen_v3
pad_vgen_v2
1.2V voltage
reference
pad_vgen_v1
C aux
Clcd1
VGEN
Clcd2
pad_vgen_va
pad_lcd_io[31:0]
pad_lcd_com1
pad_lcd_com0
LCD DISPLAY
SEGMENTS
COM1
COM0
Figure 19-4. LCD with 1:2 multiplexing and on-chip 1/2 bias voltage generation.
Lots of different configurations for the voltage generation can be used. Figure 19-4 shows the connections and
external elements that are required if the display is to be driven from V2=1.2V and V3=2.4V independently from the
circuit supply voltage. Other possible configurations are given in section 19.5.4. Recommended values for the
external capacitors are 470nF.
To operate the driver in this configuration, the registers should be loaded with the values in Table 19-14.
Register
RegVgenCfg0
RegLcdOn
RegLcdSe
RegLcdClkFrame
Contents[7:0]
xx110101
xxxxx001
11111111
100xxx01
Table 19-14. Register contents for 1:2 mux example
The voltage generator has to be configured for the use of the internal reference (VgenRefEn=1 in RegVgenCfg0).
The generator has to run (VgenOff=0 and VgenStdb=0 in RegVgenCfg0). It has to be in 1/2 bias (VgenMode=1
in RegVgenCfg0) and the generator output impedance is set to minimum (VgenClkSel=11 in RegVgenCfg0).
© Semtech 2006
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19-9
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
V3
pad_lcd_com0
V2
V0
V3
pad_lcd_com1
pad_lcd_com0 - pad_lcd_io[0] (on)
V2
V3
V0
V2
V0
-V2
-V3
V3
pad_lcd_io[0]
pad_lcd_com1 - pad_lcd_io[1] (off)
V2
V3
V0
V2
V0
-V2
-V3
V3
pad_lcd_io[1]
V2
V0
Figure 19-5. 1:2 MUX mode waveforms
The LCD driver is set to 1:2 multiplexing (LcdMux=01 in RegLcdOn) and the waveform generator is enabled
(LcdSleep=0 in RegLcdOn). All pads are set into the LCD driver mode by setting all bits of register RegLcdSe to
1. To select a frame rate of about 50Hz, set the bits LcdFreq=01 and LcdDivFreq=100 in RegLcdClkFrame. Note
that the precision of the frame frequency depends on the selected clock source (see clock block documentation).
The 64 segments are on or off depending on the bits set in the registers RegLcdDataN. Only the bits 0,1 and 4,5 of
these registers are used in 1:2 multiplexing. Figure 19-5 shows the generated waveforms for four segments.
Segments connected to pad_lcd_io[0] are on (LcdData0[1:0]=11 in RegLcdData0) and segments connected to
pad_lcd_io[1] are off (LcdData0[5:4]=00 in RegLcdData0). The figure shows on the left side the waveforms on the
circuit pins, in the middle the segment status and on the right the voltage on the segment (difference between the
segment pin pad_lcd_io and common signal pad_lcd_com0 or pad_lcd_com1).
© Semtech 2006
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19-10
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
19.4.3
1:3 Multiplex scheme
With 1:3 multiplexing, each pad_lcd_io pin can drive three segments of the display. In this mode, up to 93
segments of the display can be driven by the pad_lcd_io[30:0] pins. The common nodes are to be connected to the
pad_lcd_com0, pad_lcd_com1 and pad_lcd_io[31]. These connections are shown in Figure 19-6.
pad_vgen_vb
pad_lcd_vr1
pad_lcd_vr2
pad_vgen_v3
pad_vgen_v2
1.2V voltage
reference
pad_vgen_v1
C aux
Clcd1
VGEN
Clcd2
Clcd3
pad_vgen_va
pad_lcd_io[30:0]
pad_lcd_io[31]
pad_lcd_com1
pad_lcd_com0
SEGMENTS
LCD DISPLAY
COM2
COM1
COM0
Figure 19-6: LCD with 1:3 multiplexing and on-chip 1/3 bias voltage generation.
Lots of different configurations for the voltage generation can be used. Figure 19-6 shows the connections and
external elements that are required if the display is to be driven from 3.6V independently from the circuit supply
voltage. Other possible configurations are given in section 19.5.4. The recommended value for the external
capacitors is 470nF.
To operate the driver in this configuration, the registers should be loaded with the values in Table 19-15.
Register
RegVgenCfg0
RegLcdOn
RegLcdSe
RegLcdClkFrame
Contents[7:0]
xx110001
xxxxx010
11111111
110xxx10
Table 19-15. Register contents for 1:3 mux example
© Semtech 2006
www.semtech.com
19-11
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
V3
pad_lcd_com0
V2
V1
V0
pad_lcd_com0 - pad_lcd_io[0] (on)
V3
V3
V2
V2
pad_lcd_com1
V1
V1
V0
V0
-V1
pad_lcd_io[31]
V3
-V2
V2
-V3
V1
pad_lcd_com1 - pad_lcd_io[1] (off)
V0
V3
V2
V1
V3
pad_lcd_io[0]
V0
V2
-V1
V1
-V2
V0
-V3
V3
pad_lcd_io[1]
pad_lcd_io[31] - pad_lcd_io[2] (on)
V2
V3
V1
V2
V0
V1
V0
V3
pad_lcd_io[2]
-V1
V2
-V2
V1
-V3
V0
Figure 19-7. 1:3 MUX mode waveforms
The voltage generator has to be configured for the use of the internal reference (VgenRefEn=1 in RegVgenCfg0).
The generator has to run (VgenOff=0 and VgenStdb=0 in RegVgenCfg0). It has to generate 1/3 bias
(VgenMode=0 in RegVgenCfg0) and the generator output impedance is set to minimum (VgenClkSel=11 in
RegVgenCfg0).
The LCD driver is set to 1:3 multiplexing (LcdMux=10 in RegLcdOn) and the waveform generator is enabled
(LcdSleep=0 in RegLcdOn). All pads are set into the LCD driver mode by setting all bits of register RegLcdSe to
1. To select a frame rate of about 50Hz, set the bits LcdFreq=10 and LcdDivFreq=110 in RegLcdClkFrame. Note
that the precision of the frame frequency depends on the selected clock source (see clock block documentation).
The 93 segments are on or off depending on the bits set in the registers RegLcdDataN. Only the bits 0,1,2 and
4,5,6 of these registers are used in 1:3 multiplexing. The bits 3 and 7 are not important. Figure 19-7 shows the
generated waveforms for nine segments. The segments connected to pad_lcd_io[0] are all on (LcdData0[2:0]=111
in RegLcdData0), the segments connected to pad_lcd_io[1] are all off (LcdData0[6:4]=000 in RegLcdData0) and
the segments connected to pad_lcd_io[2] are partially on, partially off (LcdData1[2:0]=101 in RegLcdData1). The
© Semtech 2006
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19-12
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
figure shows on the left side the waveforms on the circuit pins, in the middle the segment status and on the right
the voltage on some segments (difference between the segment pin pad_lcd_io and common signals:
pad_lcd_com0, pad_lcd_com1 or pad_lcd_io[31]).
19.4.4
1:4 Multiplex scheme
pad_vgen_vb
pad_lcd_vr1
pad_lcd_vr2
pad_vgen_v3
pad_vgen_v2
1.2V voltage
reference
pad_vgen_v1
Caux
Clcd1
VGEN
Clcd2
Clcd3
pad_vgen_va
pad_lcd_io[29:0]
pad_lcd_io[30]
pad_lcd_io[31]
pad_lcd_com1
pad_lcd_com0
LCD DISPLAY
SEGMENTS
COM3
COM2
COM1
COM0
Figure 19-8: LCD with 1:4 multiplexing and on-chip 1/3 bias voltage generation.
With 1:4 multiplexing, each pin pad_lcd_io can drive four segments of the display. In this mode, up to 120
segments of the display can be driven by the pad_lcd_io[29:0] pins. The common nodes are to be connected to the
pad_lcd_com0, pad_lcd_com1, pad_lcd_io[31] and pad_lcd_io[30]. These connections are shown in Figure 19-8.
Lots of different configurations for the voltage generation can be used. Figure 19-8 shows the connections and
external elements that are required if the display is to be driven from V3=3.6V, V2=2.4V and V1=1.2V
independently from the circuit supply voltage. Other possible configurations are given in section 19.5.4. The
recommended value for the external capacitors is 470nF.
© Semtech 2006
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19-13
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
V3
p a d _ lc d _ c o m 0
V2
V1
V0
p a d _ lc d _ c o m 0 - p a d _ lc d _ io [ 0 ] (o n )
V3
V3
V2
p a d _ lc d _ c o m 1
V2
V1
V1
V0
V0
-V1
-V2
V3
p a d _ lc d _ io [3 1 ]
-V3
V2
V1
p a d _ lc d _ c o m 1 - p a d _ lc d _ io [ 1 ] (o f f)
V0
V3
V2
V3
p a d _ lc d _ io [3 0 ]
V1
V2
V0
V1
-V1
V0
-V2
-V3
p a d _ lc d _ io [3 0 ] - p a d _ lc d _ io [2 ] ( o n )
V3
p a d _ lc d _ io [0 ]
V3
V2
V2
V1
V1
V0
V0
-V1
V3
-V2
p a d _ lc d _ io [1 ]
V2
-V3
V1
V0
V3
p a d _ lc d _ io [2 ]
V2
V1
V0
Fr a me f r e q u e n cy
Figure 19-9. 1:4 MUX mode waveforms
To operate the driver in this configuration, the registers should be loaded with the values in Table 19-16.
The voltage generator has to be configured for the use of the internal reference (VgenRefEn=1 in RegVgenCfg0).
The generator has to run (VgenOff=0 and VgenStdb=0 in RegVgenCfg0). It has to generate 1/3 bias
(VgenMode=0 in RegVgenCfg0) and the generator output impedance is set to minimum (VgenClkSel=11 in
RegVgenCfg0).
Register
RegVgenCfg0
RegLcdOn
RegLcdSe
RegLcdClkFrame
Contents[7:0]
xx110001
xxxxx011
11111111
100xxx10
Table 19-16. Register contents for 1:4 mux example
The LCD driver is set to 1:4 multiplexing (LcdMux=11 in RegLcdOn) and the waveform generator is enabled
(LcdSleep=0 in RegLcdOn). All pads are set into the LCD driver mode by setting all bits of register RegLcdSe to
© Semtech 2006
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19-14
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
1. To select a frame rate of about 50Hz, set the bits LcdFreq=10 and LcdDivFreq=100 in RegLcdClkFrame. Note
that the precision of the frame frequency depends on the selected clock source (see clock block documentation).
The 120 segments are on or off depending on the bits set in the registers RegLcdDataN. All bits of these registers
are used in 1:4 multiplexing. Figure 19-9 shows the generated waveforms for twelve segments. The segments
connected to pad_lcd_io[0] are all on (LcdData0[3:0]=1111 in RegLcdData0), the segments connected to
pad_lcd_io[1] are all off (LcdData0[7:4]=0000 in RegLcdData0) and the segments connected to pad_lcd_io[2] are
partially on, partially off (LcdData1[2:0]=1101 in RegLcdData1). The figure shows on the left side the waveforms
on the circuit pins, in the middle the segment status and on the right the voltage on some segments (difference
between the pad_lcd_io pin and common signal: pad_lcd_com0, pad_lcd_com1, pad_lcd_io[31] or pad_lcd_io[30]).
19.5 Advanced LCD features
19.5.1
Register usage
To set the peripheral in LCD mode, all bits in RegLcdSe have to be set to 1.
The status of the segments has to be written to the registers RegLcdDataN (with 0<N<15). Each register drives the
segments connected to the pins pad_lcd_io[2N] (bits 0 to 3) and pad_lcd_io[2N+1] (bits 4 to 7). Depending on the
selected multiplexing (LcdMux in RegLcdOn), not all bits in the data registers RegLcdDataN are used as shown
in Table 19-17. The unused locations will always read back ‘0’. When reading back these registers, it will give the
actual value on the display. When writing to these registers, the modifications will be taken into account only at the
start of a new frame.
Note that in the 1:3 multiplexing, the pad_lcd_io[31] pin is used as the third common signal and the data
LcdData15[7:4] are not used. In the 1:4 multiplexing, the pad_lcd_io[31:30] are used as common signals and the
data LcdData15[7:0] are not used.
RegLcdDataN[x]
3, 7
2, 6
1, 5
0, 4
DD
x
x
x
used
1:2
x
x
used
used
1:3
x
used
used
used
1:4
used
used
used
used
Table 19-17. Useful data.
In the LCD mode, all pads have LCD driver capabilities. The parallel port configuration registers
(RegPLcdPullupN, RegPLcdDirN and RegPLcdOutN ) are unused. Writing to these registers will have no
influence on the peripheral activity. These registers and RegPLcdInN will read back ‘0’.
19.5.2
Sleep mode or blinking mode
When putting the LCD driver in sleep mode (LcdSleep = 1 in RegLcdOn), the peripheral will stop the waveform
generation at the end of a frame. Entering sleep mode does not modify the LCD set-up but during sleep mode, the
user is still allowed to write data into the RegLcdDataN registers. Figure 19-10 shows an example of the sleep
mode synchronisation. The sleep signal can be used to blink the display.
© Semtech 2006
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19-15
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
V3
V2
V1
V0
V3
V2
V1
V0
LcdSleep
Frame 1
Frame 0
Sleep
Frame 2
Figure 19-10. Sleep mode synchronisation
19.5.3
LCD frame frequency selection
512 Hz
1024 Hz
2048 Hz
4096 Hz
00
01
10
Frame rate frequency
3-bit Programmable divider
Internal State generator
11
Lcdfreq(1:0)
Lcddivfreq(2:0)
LcdMux(1:0)
Figure 19-11: Frame Rate generation
The LCD driver frame frequency depends on three parameters: the selected clock source frequency, the selected
division factor and the multiplexing scheme. As shown in Figure 19-11, four different clock source frequencies can
be selected by setting the bits LcdFreq in RegLcdClkFrame. This frequency is further divided by a factor between
1 and 8 depending on the bits LcdDivFreq in RegLcdClkFrame. It further depends on the selected multiplexing
scheme (bits LcdMux in RegLcdOn). The selections are defined in Table 19-18 to Table 19-20. The frame rate
FR is then given by:
FR =
f LCD
2 ⋅ div ⋅ mux
Finally, Table 19-21 shows the minimal and maximal frame rate for each multiplexing. The source frequency should
be chosen as low as possible to reduce the power consumption. Note that the precision of the frame rate depends
on the precision of the selected clock source (see clock block documentation).
© Semtech 2006
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19-16
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
LcdFreq
f LCD [Hz]
00
01
10
11
512
1048
2048
4096
Table 19-18. LCD driver source frequency selection
LcdDivFreq
000
001
010
011
100
101
110
111
div
1
2
3
4
5
6
7
8
Table 19-19. LCD driver frequency division
LcdMux
00
01
10
11
multiplexing scheme
direct drive
1:2
1:3
1:4
mux
1
2
3
4
Table 19-20. LCD multiplexing
LcdMux
00
00
01
01
10
10
11
11
LcdFreq
00
11
00
11
00
11
00
11
LcdDivFreq
111
000
111
000
111
000
111
000
FR [Hz]
32
2048
16
1024
10.6
682.7
8
512
Table 19-21. Minimal and maximal Frame Rate
19.5.4
Voltage generation
The different voltages used in the LCD driver can be generated in several ways. Depending on the selected
multiplexing scheme, the LCD display driver needs 2, 3 or 4 different voltages.
The reference voltage can be derived from an internal 1.2V band gap reference or from an externally supplied
voltage. The circuit also contains a voltage multiplier/divider that can be configured to generate a 1/2 bias or a 1/3
bias. This multiplier/divider needs external capacitors. Instead of the internal multiplier/divider, an external resistive
ladder can be used. The use of the internal circuitry will in most applications give the lowest power solution.
The voltages V0, V1 and V2 are connected internally in the circuit. The voltage V3 is not connected internally but
externally by short-circuiting the pins pad_lcd_vr1 and pad_lcd_vr2 to pad_vgen_v3.
The voltages used in the LCD driver for the different multiplexing schemes are given in Table 19-22.
© Semtech 2006
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19-17
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
multpilexing
direct drive
1:2
1:3
1:4
V0
used
used
used
used
V1
used
used
V2
used
used
used
V3
used
used
used
used
Table 19-22. V0, V1, V2, V3 usage in the LCD driver
19.5.4.1
Generating LCD voltage with the internal multiplier/divider.
To generate LCD voltage with the internal multiplier/divider, some external capacitors have to be connected to the
circuit. The value of the capacitor C aux can be calculated depending on the output impedance that is required on
the V3 voltage:
C aux ≅
with
6
f vgen ⋅ Z outV 3
f vgen the operating frequency of the multiplier/divider (set by the bits VgenClkSel in RegVgenCfg0, see Table
19-23) and Z outV 3 the required output impedance of V3. The equation is valid for C aux <5µF.
Note that the operating frequency depends on the selected clock source (see clock block documen-tation).
For a capacitor C aux of 470nF and a frequency of 1024Hz (default value), an output impedance of 12kΩ is
obtained. The capacitors CLCD1, CLCD2 and CLCD3 can be chosen equal to C aux .
VgenClkSel
f vgen (Hz)
00
01
10
11
256
512
1024
2048
Table 19-23. multplier/divider operating frequency
To enable the voltage multiplier/divider, the bits VgenOff and VgenStdb in RegVgenCfg0 are set to 0. The
difference between the two bits is that VgenOff stops the generator and forces the nodes pad_vgen_v1,
pad_vgen_v2, pad_vgen_v3, pad_vgen_va and pad_vgen_vb to predefined values and therefor discharges the
capacitors CLCD1, CLCD2 and CLCD3. The bit VgenStdb only stops the operating clock without changing the voltage
on CLCD1, CLCD2 and CLCD3. The capacitors will be discharged by leakage and by the switching of the LCD if the bit
LcdSleep is not set.
The multiplier/divider can generate 1/2 bias (VgenMode=1 in RegVgenCfg0) or 1/3 bias (VgenMode=0 in
RegVgenCfg0).
Finally, the multiplier/divider can use the internal 1.2V bandgap reference (VgenRefEn=1 in RegVgenCfg0) or an
external reference (VgenRefEn=0 in RegVgenCfg0). The internal voltage reference can not be used in case the
circuit voltage supply is below 1.5V.
Figure 19-12 shows the external connections to be made in 1/3 bias mode.
Part (a) of the figure shows the use
of the internal voltage reference. In this case, V1=1.2V, V2=2.4V and V3=3.6V. Part (b) of the figure shows the use
of an external voltage reference. The external reference can be connected to one of the pins pad_vgen_v1,
pad_vgen_v2, pad_vgen_v3. Table 19-24 shows the voltage generated on V1, V2, V3 depending on the
connection of the external reference voltage Vext. The external voltage may or may not be identical to the circuit
© Semtech 2006
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19-18
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
supply voltage VBAT. The voltage on V3 should not exceed 5.5V. The voltage on pad_vgen_v1 should not exceed
VBAT.
VgenOff = 0
VgenRefEn = 1
VgenMode = 0
VgenOff = 0
VgenRefEn = 0
VgenMode = 0
LCD driv er
LCD driv er
pad_v gen_v b
pad_v gen_v b
pad_v gen_v 3
pad_v gen_v 3
Clcd3
Clcd3
pad_v gen_v 2
pad_v gen_v 2
Clcd2
pad_v gen_v 1
1.2V v oltage
ref erence
Clcd2
Caux
Clcd1
Caux
Clcd1
VGEN
pad_v gen_v a
VGEN
1.2V v oltage
ref erence
pad_v gen_v 1
pad_v gen_v a
(b)
(a)
v oltage
Vext
Figure 19-12: Generation of LCD voltage with external capacitors for 1/3 bias mode.
Vext connection
V1 (V)
V2 (V)
V3 (V)
pad_vgen_v1
pad_vgen_v2
pad_vgen_v3
Vext
(1/2)⋅Vext
(1/3) ⋅Vext
2⋅Vext
Vext
(2/3) ⋅Vext
3⋅Vext
(3/2)⋅Vext
Vext
Table 19-24. V1, V2 and V3 as a function of the external reference connection in 1/3 bias mode
Figure 19-13 shows the external connections to be made in 1/2 bias mode. Part (a) of the figure shows the use of
the internal voltage reference. In this case, V1=V2=1.2V and V3=2.4V. Part (b) of the figure shows the use of an
external voltage reference. The external reference can be connected to one of the pins pad_vgen_v1 or
pad_vgen_v3. Table 19-25 shows the voltage generated on V1 and V3 depending on the connection of the
external reference voltage Vext. The external voltage may or may not be identical to the circuit supply voltage
VBAT. The voltage on V3 should not exceed 5.5V.
Vext connection
V1 (V)
V3 (V)
pad_vgen_v1
pad_vgen_v3
Vext
(1/2) ⋅Vext
2⋅Vext
Vext
Table 19-25. V1 and V3 as a function of the external reference connection in 1/2 bias mode
© Semtech 2006
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19-19
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
VgenOff = 0
VgenRefEn = 1
VgenMode = 1
VgenOff = 0
VgenRefEn = 0
VgenMode = 1
LCD driv er
LCD driv er
pad_v gen_v b
pad_v gen_v b
pad_v gen_v 3
pad_v gen_v 3
Clcd3
Clcd3
pad_v gen_v 2
pad_v gen_v 2
pad_v gen_v 1
Caux
pad_v gen_v 1
Caux
1.2V v oltage
ref erence
1.2V v oltage
ref erence
Clcd1
Clcd1
pad_v gen_v a
VGEN
VGEN
pad_gen_v a
(b)
(a)
v oltage
Vext
Figure 19-13: Generation of LCD voltage with external capacitors for 1/2 bias mode.
Finally, in direct drive, there is no need for intermediate voltages. The configurations of Figure 19-12(a) or Figure
19-13(a) can still be used (depending on the required voltage: 2.4V or 3.6V) but the configurations in Figure
19-12(b) or Figure 19-13(b) can be replaced by the simple schematic of Figure 19-14. The external voltage Vext
may or may not be identical to the circuit supply voltage VBAT.
VgenOff = 1
VgenRefEn = 0
LCD driver
pad_gen_v b
pad_gen_v 3
pad_gen_v 2
pad_v gen_v 1
1.2V voltage
reference
voltage
Vext
pad_gen_v a
VGEN
Figure 19-14. Generation of LCD voltage for direct drive using external voltage.
19.5.4.2
Generating LCD voltages with an external resistor ladder
To generate the LCD voltages with an external R-ladder (Figure 19-15), the internal voltage reference and
multiplier/divider block are not used (VgenOff=1 and VgenRefEn=0 in RegVgenCfg0). All other bits in the register
RegVgenCfg0 are unused.
All resistor values are equal and sufficiently small in order to have small LCD voltage impedance. For direct drive,
no resistors are required as shown in Figure 19-14. The voltage Vext can be connected to the circuit supply voltage
VBAT or any other external voltage.
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19-20
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
VgenOff = 1
VgenRefEn = 0
LCD driver
VgenOff = 1
VgenRefEn = 0
LCD driver
Vext
Vext
pad_gen_v b
pad_gen_v b
pad_v gen_v 3
pad_v gen_v 3
pad_v gen_v 2
R3
pad_v gen_v 1
R2
1.2V voltage
reference
R3
pad_v gen_v 2
pad_v gen_v 1
1.2V voltage
reference
R1
VGEN
R1
VGEN
pad_v gen_v a
pad_v gen_v a
(b)
(a)
Figure 19-15. Generation of LCD voltages with external resistors ladder in 1/3 (a) and 1/2 (b) bias
mode.
19.6 Parallel I/O port capabilities
19.6.1
Parallel port function
All pins pad_lcd_io[31:0] can be used as a general input/output digital port. The peripheral is set to this mode by
writing all bits of the register RegLcdSe to ‘0’. Figure 19-16 shows the structure for one pin and the registers used
in this mode. Since the peripheral has 32 pins, 4 of each of the registers in Figure 19-16 exist. They are labelled
with the suffix 0 to 3. The mapping of the register bits to the I/O pins is given in Table 19-26. As an example, the bit
PLcdPullup2[6] in RegPLcdPullup2 controls the pull up resistor of the pin pad_lcd_io[22].
suffix of the register
0≤N≤3
N
bit in the register
0≤n≤7
n
pin
pad_lcd_io[8N+n]
Table 19-26. Register bit to pin mapping
The direction of each pin pad_lcd_io[31:0] (input or output) can be individually set by using the RegPLcdDirN
registers. If PLcdDirN[n] = 1, the output buffer of the corresponding pad_lcd_io[8N+n] is enabled.
Output mode:
The data to be output is stored in RegPLcdOutN. In output mode, the pull-up resistors should be switched off by
writing ‘0’ to the registers RegPLcdPullupN. If not, current will flow through the pull-up resistors when the output is
forced to ‘0’.
© Semtech 2006
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19-21
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
PORT
R
RegPlcdPullup
RegPlcdOut
RegPlcdDir
RegPlcdIn
Figure 19-16. Structure of the LCD driver used as parallel port
Input mode:
The status of the pins pad_lcd_io is available in RegPLcdInN (read only). Reading is always direct, there is no
digital debounce function. In case of noisy input signals, a software debouncer or an external filter must be realised.
The pull-up resistors are individually controllable for each pin by setting the corresponding bit in the registers
RegPLcdPullN (1=active, 0=inactive).
19.6.2
Parallel Port Voltage
When the peripheral is used as a parallel port, the internal voltage generator is not required (VgenOff=1 and
VgenRefEn=0 in RegVgenCfg0). For normal operation as a standard parallel port, the circuit is connected as
shown in Figure 19-17. In this case, the logical ‘1’ corresponds to the voltage VBAT.
The parallel port can also be driven from another voltage than VBAT. This allows the circuit to be interfaced to
other circuits that have a different supply voltage domain VDD1 that can be either lower or higher than VBAT
without adding any extra hardware as shown in Figure 19-18.
The parallel port can be split in several voltage domains. The pins pad_lcd_io[31:12] are supplied from the
pad_vgen_v3 pin. The pins pad_lcd_io[11:4] are supplied from the pin pad_lcd_vr1 and the pins pad_lcd_io[3:0]
are supplied from the pin pad_lcd_vr2. Each of these can be supplied with a different voltage as shown in Figure
19-19. As an example, VBAT could be supplied at 2.7V, VDD1 at 2.2V, VDD2 at 3.3V and VDD3 at 5V. The only
limitation is that VDD1>VREG, VDD2>VREG, VDD3>VREG.
© Semtech 2006
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19-22
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
VgenOff = 1
VgenRefEn = 0
V1 V2 V3
VBAT
pad_lcd_vr1
pad_lcd_vr2
pad_vgen_vb
pad_vgen_v3
pad_vgen_v2
pad_vgen_v1
1.2V voltage
reference
pad_vgen_va
VGEN
VSS
Figure 19-17. Parallel port voltage connection
VgenOff = 1
VgenRefEn = 0
VDD1 domain
VBAT
pad_lcd_io[31:0]
I/O[31:0]
VDD1
pad_lcd_vr1
pad_lcd_vr2
VDD1
VSS
pad_vgen_vb
pad_vgen_v3
pad_vgen_v2
pad_vgen_v1
1.2V voltage
reference
VGEN
pad_vgen_va
VSS
Figure 19-18. Parallel port voltage connection with I/O levelshifting
© Semtech 2006
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19-23
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
VBAT
vbat
VDD1
VBAT domain
pad_lcd_vr2
VDD1
I/Os
pad_lcd_io[3:0]
VDD1 domain
vgen_off = 1
vgen_ref_en = 0
VDD2
VDD2
I/Os
pad_lcd_vr1
pad_lcd_io[11:4]
VDD2 domain
VDD3
pad_vgen_vb
pad_vgen_v3
pad_lcd_io[31:12]
VDD3
I/Os
VDD3 domain
1.2V voltage
reference
pad_vgen_v2
pad_vgen_v1
VGEN
pad_vgen_va
vss
Figure 19-19. Multi voltage parallel port interface
19.7 Partial LCD Driver / Partial Parallel I/O Port
It is perfectly possible to combine different modes described in the previous sections on different pins. Using the
bits LcdSe in the register RegLcdSe, the pins pad_lcd_io[31:0] can be set as parallel port or as LCD drivers. Each
bit sets the mode for 4 pins (see Table 19-4).
When combining the LCD and digital port functions, care has to be taken with the voltage generation. The logical
‘1’ of the digital I/O is driven from the V3 rail and needs to be low impedance. The V3 of the pins used for digital I/O
can not be supplied by the on-circuit voltage multiplier. The next sections show different possibilities.
19.7.1
Single low impedance voltage for V3 of LCD and digital I/O
If V3 in the LCD driver is supplied from a low impedance voltage supply (as e.g. in Figure 19-12(b) or Figure
19-13(b) with connection of Vext to pad_vgen_v3, or in Figure 19-14 and Figure 19-15), the partitioning of the pins
pad_lcd_io[31:0] between the LCD driver function and the digital parallel port function can be chosen freely by
setting the bits LcdSe. Vext may be equal to the circuit supply voltage VBAT but this is not required. The digital I/O
pins use the voltages V0=VSS and V3=Vext for the logical ‘0’ and logical ‘1’ respectively.
© Semtech 2006
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19-24
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
vdd
vbat
pad_vgen_vb
pad_lcd_vr1
pad_lcd_vr2
External circuit
pad_vgen_v3
pad_vgen_v2
1.2V voltage
reference
pad_vgen_v1
Caux
Clcd1
Clcd3
vss
vss
VGEN
pad_vgen_va
pad_lcd_io[15:0]
IO_1[15:0]
IO_2[7:0]
pad_lcd_io[31:24]
pad_lcd_io[23:16]
pad_lcd_com1
pad_lcd_com0
SEGMENTS[7:0]
LCD DISPLAY
COM1
COM0
Figure 19-20: Sharing LCD (1:2 mux) and digital I/O (low impedance V3)
Figure 19-20 and Table 19-27 show a possible example for such a configuration. In this case, the LCD driver
voltage V3=VBAT and V1=VBAT/2 (1/2 bias mode, VgenMode=1, VgenRefEn=0 and VgenOff=0 in
RegVgenCfg0). The LCD is in 1:2 multplexing (LcdMux=01 in RegLcdOn) and LcdSe19=LcdSe23=1 while all
other bits in RegLcdSe are 0.
Register
RegVgenCfg0
RegLcdOn
RegLcdSe
Contents[7:0]
xx110100
xxxxx001
11110011
Table 19-27. Register contents for configuration of Figure 19-20.
© Semtech 2006
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19-25
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
19.7.2
Different Voltages for V3 of LCD and Digital I/O
When configured as a digital I/O, the logical ‘1’ on the pins pad_lcd_io[31:0] is identical to V3. For a part of the
pad_lcd_io[31:0] pins, the V3 connection is not made inside the circuit but has to be done externally by connecting
the pins pad_vgen_v3, pad_lcd_vr1 and pad_lcd_vr2 together. This feature allows for the use of different voltages
on V3 for the LCD display and for I/O parallel pins. Table 19-28 shows the partitioning of the pins. The voltages that
can be applied on pad_vgen_v3, pad_lcd_vr1, pad_lcd_vr2 and VBAT are completely independent from each
other.
pin
pad_lcd_com0
pad_lcd_com1
pad_lcd_io[31:12]
pad_lcd_io[11:4]
pad_lcd_io[3:0]
V3 connection
pad_vgen_v3
pad_lcd_vr1
pad_lcd_vr2
Table 19-28. V3 connection of the different pad_lcd_io pins
vbat
vbat
vdd1
pad_lcd_vr2
vdd
pad_lcd_io[3:0]
io[3:0]
EXTERNAL
CIRCUIT
vss
vdd1 voltage domain
vdd2
pad_lcd_vr1
vdd
io[7:0]
pad_lcd_io[11:4]
EXTERNAL
CIRCUIT
vss
vdd2 voltage domain
pad_vgen_vb
pad_vgen_v3
pad_vgen_v2
1.2V voltage
reference
pad_vgen_v1
Caux
Clcd1
VGEN
Clcd2
Clcd3
vss
pad_vgen_va
pad_lcd_io[29:12]
pad_lcd_io[30]
pad_lcd_io[31]
pad_lcd_com1
pad_lcd_com0
SEGMENTS[17:0]
LCD DISPLAY
COM3
COM2
COM1
COM0
Figure 19-21. Sharing LCD driver (1:4 mux) and digital I/O with V3 ≠ logic ‘1’
© Semtech 2006
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19-26
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
As can be seen from Table 19-28, the voltage V3 on the pins pad_lcd_io[31:12] can not be dissociated from the
voltage V3 on the pins pad_lcd_com0, pad_lcd_com1 and the internal voltage multiplier/divider. It means that, if V3
is not a low impedance external voltage as in the previous section, they can be used for the LCD driver only and
not for digital I/O.
Figure 19-21 and Table 19-29 show an example. In this case, the pins pad_lcd_io[29:12] are used to drive a
display with 1:4 multiplexing (LcdSe15=LcdSe19=LcdSe23=Lcd27=Lcd31=1 in RegLcdSe and LcdMux=11 in
RegLcdOn). In 1:4 multiplexing, the lines pad_lcd_io[31:30] are used for COM2 and COM3. The voltage V3 for the
display is generated by the internal voltage multiplier/divider using the internal reference (VgenOff=0,
VgenRefEn=1, VgenMode=0 in RegVgenCfg0). The segment status is set by using the RegLcdDataN registers
with 6≤N≤15. Writing in the registers with 0≤N≤5 will have no effect. The pins pad_lcd_io[11:0] are used as digital
I/O (LcdSe3=LcdSe7=LcdSe11=0 in RegLcdSe). The control of the digital I/O is done using the registers
RegPLcdInN, RegPLcdOutN, RegPLcdDirN and RegPLcdPullupN with 0≤N≤1. Writing in the registers with
2≤N≤3 will have no effect. The pins pad_lcd_io[11:4] and pad_lcd_io[3:0] can further be split into two different
voltage domains. The voltage domains VDD1, VDD2, V3 and VBAT are independent. The only limitation is that
VDD1>VREG and VDD2>VREG. In the example V3=3.6V, VBAT could be at 2.7V, VDD1 at 2.4V and VDD2 at 5V.
Register
RegVgenCfg0
RegLcdOn
RegLcdSe
Contents[7:0]
xx110001
xxxxx011
00011111
Table 19-29. Register contents for configuration of Figure 19-21.
19.8 Specifications
19.8.1
pad_lcd_io used in LCD mode
Specification
V1
V2, V3
trise-fall
Min
1.1
1.1
Typ
Max
VBAT
5.5
25
Unit
V
V
µs
Description
Comments
Rise/Fall time (LCD mode)
(1) (2) (3)
(1) rise or fall time from 10% to 90% of the output signal
(2) Cload=5000pF
(3) V1=V2/2=V3/3=1.1V (1/3 bias) or V1=V2=V3/2=1.1V (1/2 bias)
19.8.2
pad_lcd_io used in digital I/O mode
Specification
pad_lcd_vr1
pad_lcd_vr2
pad_vgen_v3
R_pullud
trise-fall
IOD
Min
VREG
VREG
VREG
35
Typ
1
8
Max
5.5
5.5
5.5
100
Unit
V
V
V
kΩ
µs
mA
Description
pad supply voltage
pad supply voltage
pad supply voltage
Pull up/down resistance
Rise/Fall time
Output current drive
Comments
(1) (2)
(3)
(1) rise or fall time from 10% to 90% of the output signal
(2) with Cload=5nF, pad_vgen_v3=pad_lcd_vr1=pad_lcd_vr2=2.4V
(3) pad_vgen_v3=pad_lcd_vr1=pad_lcd_vr2=4.5V, voltage on pad_lcd_io=0.4V for sink current and 4.1V for
source current.
© Semtech 2006
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19-27
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
19.8.3
Voltage Reference
Specification
Vref
∆Vref/∆T
Power supply VBAT
I_load on V1
Zout on V1
19.8.4
(5)
Typ
1.17
0.2
1.5
Max
1.34
5.5
2
1000
Unit
V
mV/°C
V
mA
Ω
Comment
@20°C, VBAT>2.4V
LCD multiplier/divider
Specification
Settling time to 90%
Zout,v2 on V2
Zout,v3 on V3
pad_vgen_v3
(1)
(2)
(3)
(4)
Min
1.0
Min
Typ
3 (1)
7 (1)
6 (2)
14 (2)
Max
30
25 (3)
60 (3)
5.5
Unit
ms
kΩ
kΩ
V
Comments
(2), (4), (5)
(4), (5)
(4), (5)
f(vgen_clk) = 2 kHz.
f(vgen_clk) = 1 kHz.
f(vgen_clk) = 0.25 kHz.
1/3 bias mode.
with 0.47µF external capacitors.
© Semtech 2006
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19-28
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
20.
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
20.10
20.11
20.12
Counters/PWM
FEATURES ..........................................................................................................................20-2
OVERVIEW ..........................................................................................................................20-2
REGISTER MAP ...................................................................................................................20-2
INTERRUPTS AND EVENTS MAP .............................................................................................20-4
BLOCK SCHEMATIC ..............................................................................................................20-4
GENERAL COUNTER REGISTERS OPERATION ..........................................................................20-5
CLOCK SELECTION ..............................................................................................................20-5
COUNTER MODE SELECTION .................................................................................................20-6
COUNTER / TIMER MODE ......................................................................................................20-7
PWM MODE .......................................................................................................................20-8
CAPTURE FUNCTION ..........................................................................................................20-10
SPECIFICATIONS ...............................................................................................................20-11
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20-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
20.1 Features
-
4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules
Each with 4 possible clock sources
Up/down counter modes
Interrupt and event generation
Capture function (internal or external source)
Rising, falling or both edge of capture signal (except for xtal 32 kHz, only rising edge)
PA[3:0] can be used as clock inputs (debounced or direct, frequency divided by 2 or not)
2 x 8 bits PWM or 2 x 16 bits PWM
PWM resolution of 8, 10, 12, 14 or 16 bits
Complex mode combinations are possible
20.2 Overview
Counter A and Counter B are 8-bits counters and can be combined to form a 16-bit counter. Counter C and
Counter D exhibit the same feature.
The counters can also be used to generate two PWM outputs on PB[0] and PB[1]. In PWM mode one can generate
PWM functions with 8, 10, 12, 14 or 16 bits wide counters.
The counters A and B can be captured by events on an internal or an external signal. The capture can be
performed on both 8-bit counters running individually on two different clock sources or on both counters chained to
form a 16-bit counter. In any case, the same capture signal is used for both counters.
When the counters A and B are not chained, they can be used in several configurations: A and B as counters, A
and B as captured counters, A as PWM and B as counter, A as PWM and B as captured counter.
When the counters C and D are not chained, they can be used either both as counters or counter C as PWM and
counter D as counter.
20.3 Register map
register name
RegCntA
RegCntB
RegCntC
RegCntD
RegCntCtrlCk
RegCntConfig1
RegCntConfig2
RegCntOn
Table 20-1. Counter registers
bit
7-0
7-0
RegCntA
CounterA
CounterA
rw
R
W
reset
00000000 nresetglobal
00000000 nresetglobal
function
8-bits counter value
8-bits comparison value
Table 20-2. RegCntA
© Semtech 2006
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20-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
bit
7-0
7-0
RegCntB
CounterB
CounterB
rw
R
W
reset
00000000 nresetglobal
00000000 nresetglobal
function
8-bits counter value
8-bits comparison value
Table 20-3. RegCntB
Note: When writing to RegCntA or RegCntB, the processor writes the counter comparison values. When reading
these locations, the processor reads back either the actual counter value or the last captured value if the capture
mode is active.
bit
7-0
7-0
RegCntC
CounterC
CounterC
rw
R
W
reset
00000000 nresetglobal
00000000 nresetglobal
function
8-bits counter value
8-bits comparison value
Table 20-4. RegCntC
bit
7-0
7-0
RegCntD
CounterD
CounterD
rw
R
W
reset
00000000 nresetglobal
00000000 nresetglobal
function
8-bits counter value
8-bits comparison value
Table 20-5. RegCntD
Note: When writing RegCntC or RegCntD, the processor writes the counter comparison values. When reading
these locations, the processor reads back the actual counter value.
bit
7-6
5-4
3-2
1-0
RegCntCtrlCk
CntDCkSel(1:0)
CntCCkSel(1:0)
CntBCkSel(1:0)
CntACkSel(1:0)
rw
R/W
R/W
R/W
R/W
reset
00 nresetglobal
00 nresetglobal
00 nresetglobal
00 nresetglobal
function
Counter d clock selection
Counter c clock selection
Counter b clock selection
Counter a clock selection
Table 20-6. RegCntCtrlCk
bit
7
6
5
4
3
2
1
0
RegCntConfig1
CntDDownUp
CntCDownUp
CntBDownUp
CntADownUp
CascadeCD
CascadeAB
CntPWM1
CntPWM0
rw
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
reset
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
function
Counter d up or down counting (0=down)
Counter c up or down counting (0=down)
Counter b up or down counting (0=down)
Counter a up or down counting (0=down)
Cascade counter c & d (1=cascade)
Cascade counter a & b (1=cascade)
Activate pwm1 on counter c or c+d (PB(1))
Activate pwm0 on counter a or a+b (PB(0))
Table 20-7. RegCntConfig1
bit
7-6
5-4
3-2
1-0
RegCntConfig2
CapSel(1:0)
CapFunc(1:0)
Pwm1Size(1:0)
Pwm0Size(1:0)
rw
R/W
R/W
R/W
R/W
reset
00 nresetglobal
00 nresetglobal
00 nresetglobal
00 nresetglobal
function
Capture source selection
Capture function
Pwm1 size selection
Pwm0 size selection
Table 20-8. RegCntConfig2
© Semtech 2006
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20-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
bit
7
6
5
4
3
2
1
0
RegCntOn
rw
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CntDExtDiv
CntCExtDiv
CntBExtDiv
CntAExtDiv
CntDEnable
CntCEnable
CntBEnable
CntAEnable
reset
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
function
Divide PA(3) frequency by 2 (1=divide)
Divide PA(2) frequency by 2 (1=divide)
Divide PA(1) frequency by 2 (1=divide)
Divide PA(0) frequency by 2 (1=divide)
Enable counter d
Enable counter c
Enable counter b
Enable counter a
Table 20-9. RegCntOn
20.4 Interrupts and events map
Interrupt source
IrqA
IrqB
IrqC
IrqD
Default mapping in
the interrupt manager
RegIrqHigh(4)
RegIrqLow(5)
RegIrqHigh(3)
RegIrqLow(4)
Default mapping in the
event manager
RegEvn(7)
RegEvn(3)
RegEvn(6)
RegEvn(2)
Table 20-10. Default interrupt and event mapping.
20.5 Block schematic
ck1k
ck16k
ck128
ckrcext/4
ckrcext
RegCntA (write)
RegCntA (read)
Counter A
PA(0)
Capture
RegCntB (write)
RegCntB (read)
Counter B
PA(1)
RegCntC (write)
ck1k
ck32k
RegCntC (read)
Counter C
PA(2)
RegCntD (write)
RegCntD (read)
Counter D
PA(3)
PB(0)
PWM
PB(1)
Figure 20-1: Counters/timers block schematic
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20-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
20.6 General counter registers operation
Counters are enabled by CntAEnable, CntBEnable, CntCEnable, and CntDEnable in RegCntOn.
To stop the counter X, CntXEnable must be reset. To start the counter X, CntXEnable must be set. When
counters are cascaded, CntAEnable and CntCEnable also control respectively the counters B and D.
WARNING: THERE SHOULD BE AT LEAST ONE CPU INSTRUCTION BETWEEN THE CONFIGURATION OF
THE COUNTERS AND THE ENABLING.
All counters have a corresponding 8-bit read/write register: RegCntA, RegCntB, RegCntC, and RegCntD. When
read, these registers contain the counter value (or the captured counter value). When written, they modify the
counter comparison values.
It is possible to read any counter at any time, even when the counter is running. The value is guaranteed to be
correct when the counter is running on an internal clock source. For a correct acquisition of the counter value when
running on an external clock source, use one of the three following methods:
1) For slow operating counters (typically at least 8 times slower than the CPU clock), oversample the counter
content and perform a majority operation on the consecutive read results to select the correct actual
content of the counter.
2) Stop the concerned counter, perform the read operation and restart the counter. While stopped, the
counter content is frozen and the counter does not take into account the clock edges delivered on the
external pin.
3) Use the capture mechanism.
When a value is written into the counter register while the counter is in counter mode, both the comparison value is
updated and the counter value is modified. In upcount mode, the register value is reset to zero. In downcount
mode, the comparison value is loaded into the counter. Due to the synchronization mechanism between the
processor clock domain and the external clock source domain, this modification of the counter value can be
postponed until the counter is enabled and that it receives it’s first valid clock edge.
In the PWM mode or in the capture mode, the counter value is not modified by the write operation in the counter
register. Changing to the counter mode, does not update the counter value (no reset in upcount, no load in
downcount mode).
20.7 Clock selection
The clock source for each counter can be individually selected by writing the appropriate value in the register
RegCntCtrlCk.
Clock source for
CntXCkSel(1:0)
11
10
01
00
CounterA
CounterB
CounterC
CounterD
Ck128
CkRcExt/4
CkRcExt
PA(0)
PA(1)
Ck1k
Ck32k
PA(2)
PA(3)
Table 20-11: Clock sources for counters A, B, C and D
Table 20-11 gives the correspondence between the binary codes used for the configuration bits CntACkSel(1:0),
CntBCkSel(1:0), CntCCkSel(1:0) or CntDCkSel(1:0) and the clock source selected respectively for the counters
A, B, C or D.
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20-5
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
The CkRcExt clock is the RC oscillator or external clock. The clocks below 32kHz can be derived from the RC
oscillator, the external clock source or the crystal oscillator (see the documentation of the clock block). A separate
external clock source can be delivered on PortA for each individula counter.
The external clock sources can be debounced or not by properly setting the PortA configuration registers.
Additionally, the external clock sources can be divided by two in the counter block, thus enabling higher external
clock frequencies, by setting the CntXExtDiv bits in the RegCntOn register.
Switching between an internal and an external clock source can only be performed while the counter is stopped.
The enabling or disabling of the external clock frequency division can only be performed while the counter using
this clock is stopped, or when this counter is running on an internal clock source.
20.8 Counter mode selection
Each counter can work in one of the following modes:
1) Counter, downcount & upcount
2) Captured counter, downcount & upcount (only counters A&B)
3) PWM, downcount & upcount
4) Captured PWM, downcount and upcount
The counters A and B or C and D can be cascaded or not. In cascaded mode, A and C are the LSB counters while
B and D are the MSB counters.
Table 20-12 shows the different operation modes of the counters A and B as a function of the mode control bits.
For all counter modes, the source of the down or upcount selection is given (either the bit CntADownUp or the bit
CntBDownUp). Also, the mapping of the interrupt sources IrqA and IrqB and the PWM output on PB(0) in these
different modes is shown.
CascadeAB
CountPWM0
CapFunc(1:0)
0
0
00
1
0
00
0
1
00
1
1
00
0
0
1
0
0
1
1
1
1x
or
x1
1x
or
x1
1x
or
x1
1x
or
x1
Counter A
mode
Counter B
mode
IrqA
source
IrqB
source
PB(0)
function
Counter 8b
Downup: A
Counter 8b
Downup: B
Counter
A
Counter
B
PB(0)
Counter 16b AB
Downup: A
PWM 8b
Counter 8b
Downup: A Downup: B
PWM 10 – 16b AB
Downup A
Captured
Captured
counter 8b
counter 8b
Downup: A Downup: B
Counter
AB
-
PB(0)
-
Counter
B
PWM A
-
-
PWM AB
Capture
A
Capture
B
PB(0)
Captured counter 16b AB
Downup: A
Capture
AB
Capture
AB
PB(0)
Capture
A
Capture
B
PWM A
Capture
AB
Capture
AB
PWM AB
Captured
Captured
PWM 8b
counter 8b
Downup: A Downup: B
Captured 10 – 16b PWM
(captured value on 16b)
Downup: A
Table 20-12: Operating modes of the counters A and B
Table 20-13 shows the different operation modes of the counters C and D as a function of the mode control bits.
For all counter modes, the source of the down or upcount selection is given (either the bit CntCDownUp or the bit
© Semtech 2006
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20-6
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
CntDDownUp). The mapping of the interrupt sources IrqC and IrqD and the PWM output on PB(1) in these
different modes is also shown.
The switching between different modes must be done while the concerned counters are stopped. While switching
capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode
change.
CascadeCD
CountPWM1
0
0
1
0
0
1
1
1
Counter C
mode
Counter D
mode
IrqC
source
IrqD
source
PB(1)
function
Counter 8b
Counter 8b
Downup: C
Downup: D
Counter 16b CD
Downup: C
PWM 8b
Counter 8b
Downup: C
Downup: D
PWM 10 – 16b CD
Downup: C
Counter
C
Counter
CD
-
Counter
D
-
PB(1)
Counter
D
-
PWM C
-
PB(1)
PWM CD
Table 20-13: Operating modes of the counters C and D
20.9 Counter / Timer mode
The counters in counter / timer mode are generally used to generate interrupts after a predefined number of clock
periods applied on the counter clock input.
Each counter can be set individually either in upcount mode by setting CntXDownUp in the register
RegCntConfig1 or in downcount mode by resetting this bit. Counters A and B can be cascaded to behave as a 16
bit counter by setting CascadeAB in the RegCntConfig1 register. Counters C and D can be cascaded by setting
CascadeCD. When cascaded, the up/down count modes of the counters B and D are defined respectively by the
up/down count modes set for the counters A and C.
When in upcount mode, the counter will start incrementing from zero up to the target value which has been written
in the corresponding RegCntX register(s). When the counter content is equal to the target value, an interrupt is
generated at the next counter clock pulse and the counter is loaded again with the zero value (Figure 20-2).
When in downcount mode, the counter will start decrementing from the initial load value which has been written in
the corresponding RegCntX register(s) down to the zero value. Once the counter content is equal to zero, an
interrupt is generated at the next counter clock pulse and the counter is loaded again with the load value (Figure
20-2).
Be careful to select the counter mode (no capture, not PWM, specify cascaded or not and up or down counting
mode) before writing any target or load value to the RegCntX register(s). This ensures that the counter will start
from the correct initial value. When counters are cascaded, both counter registers must be written to ensure that
both cascaded counters will start from the correct initial values.
The stopping and consecutive starting of a counter in counter mode without a target or load value write operation in
between can generate an interrupt if this counter has been stopped at the zero value (downcount) or at it’s target
value (upcount). This interrupt is additional to the interrupt which has already been generated when the counter
reached the zero or the target value.
Due to the synchronization between the CPU clock and the counter clock source, it may take up to 1 CPU clock
cycle before the configuration changes written in the RegCntConfigX or RegCntX registers are becoming
effective. In order to get correct operation of the counters, there should be at least 1 software instruction between
the modification of RegCntConfigX or RegCntX and the enabling of the counters.
© Semtech 2006
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20-7
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
dow n counting
clock counter X
RegcntX_r
XX
RegCntX_w
XX
3
2
1
0
3
2
1
0
3
2
1
0
3
write RegCntX
CntXDownUp
IrqX
CntXEnable
up counting
clock counter X
RegCntX_r
RegCntX_w
XX
XX
0
1
2
3
0
1
2
3
0
1
2
3
3
write RegCntX
CntXDownUp
IrqX
CntXEnable
Figure 20-2. Up and down count interrupt generation.
20.10 PWM mode
The counters can generate PWM signals (Pulse Width Modulation) on the PortB outputs PB(0) and PB(1).
The PWM mode is selected by setting CntPWM1 and CntPWM0 in the RegCntConfig1 register. See Table 20-12
and Table 20-13 for an exact description of how the setting of CntPWM1 and CntPWM0 affects the operating
mode of the counters A, B, C and D according to the other configuration settings.
When CntPWM0 is enabled, the PWMA or PWMAB output value overrides the value set in bit 0 of RegPBOut in
the Port B peripheral. When CntPWM1 is enabled, the PWMC or PWMCD output value overrides the value set in
bit 1 of RegPBOut. The corresponding ports (0 and/or 1) of Port B must be set in digital mode and as output and
either open drain or not and pull up or not through a proper setting of the control registers of the Port B.
Counters in PWM mode count down or up, according to the CntXDownUp bit setting. No interrupts and events are
generated by the counters that are in PWM mode. Counters do count circularly: they restart at zero or at the
maximal value (either 0xFF when not cascaded or 0xFFFF when cascaded) when respectively an overflow or an
underflow condition occurs in the counting.
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20-8
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
The internal PWM signals are low as long as the counter contents are higher than the PWM code values written in
the RegCntX registers. They are high when the counter contents are smaller or equal to these PWM code values.
In order to have glitch free outputs, the PWM outputs on PB(0) and PB(1) are sampled versions of these internal
PWM signals, therefore delayed by one counter clock cycle.
The PWM resolution is always 8 bits when the counters used for the PWM signal generation are not cascaded.
PWM0Size(1:0) and PWM1Size(1:0) in the RegCntConfig2 register are used to set the PWM resolution for the
counters A and B or C and D respectively when they are in cascaded mode. The different possible resolutions in
cascaded mode are shown in Table 20-14. Choosing a 16 bit PWM code which is higher than the maximum value
that can be represented by the number of bits chosen for the resolution results in a PWM output which is always
tied to 1.
PwmXsize(1:0)
11
10
01
00
Resolution
16 bits
14 bits
12 bits
10 bits
Table 20-14: Resolution selection in cascaded PWM mode
Small PWM code
Tlsmall
Thsmall
Large PWM code
Tllarge
Thlarge
Tper
Figure 20-3: PWM modulation examples
The period of the PWM signal is given by the formula:
Tper =
2 resolution
f ckcnt
The duty cycle ratio DCR of the PWM signal is defined as:
DCR =
DCR can be selected between
100
2
resolution
Th
Tper
% and 100 %.
DCR in % in function of the RegCntX content(s) is given by the relation:
⎛ 100(1 + RegCntX )
⎞
,100 ⎟
DCR = MIN ⎜
resolution
2
⎝
⎠
© Semtech 2006
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20-9
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
20.11 Capture function
The 16-bit capture register is provided to facilitate frequency measurements. It provides a safe reading mechanism
for the counters A and B when they are running. When the capture function is active, the processor does not read
anymore the counters A and B directly, but instead reads shadow registers located in the capture block. An
interrupt is generated after a capture condition has been met when the shadow register content is updated. The
capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or
from the external PA(2) or PA(3) ports. Both counters use the same capture condition.
When the capture function is active, the A and B counters can either upcount or downcount. They do not count
circularly: they restart at zero or at the maximal value (either 0xFF when not cascaded or 0xFFFF when cascaded)
when respectively an overflow or an underflow condition occurs in the counting. The capture function is also active
on the counters when used to generate PWM signals.
CapFunc(1:0) in register RegCntConfig2 determines if the capture function is enabled or not and selects which
edges of the capture signal source are valid for the capture operation. The source of the capture signal can be
selected by setting CapSel(1:0) in the RegCntConfig2 register. For all sources, rising, falling or both edge
sensitivity can be selected. Table 20-15 shows the capture condition as a function of the setting of these
configuration bits.
CapSel(1:0)
Selected capture signal
11
1K
10
16 K
01
PA3
00
PA2
CapFunc
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Selected condition
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture condition
1 K rising edge
1 K falling edge
2K
16 K rising edge
16 K falling edge
32 K
PA3 rising edge
PA3 falling edge
PA3 both edges
PA2 rising edge
PA2 falling edge
PA2 both edges
Table 20-15: Capture condition selection
CapFunc(1:0) and CapSel(1:0) can be modified only when the counters are stopped otherwise data may be
corrupted during one counter clock cycle.
Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the
capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the effective
capture condition occurred. When the counters A and B are not cascaded and do not operate on the same clock,
the interruptions on IrqA and IrqB which inform that the capture condition was met, may appear at different
moments. In this case, the processor should read the shadow register associated to a counter only if the
interruption related to this counter has been detected.
An edge is detected on the capture signals only if the minimal pulse widths of these signals in the low and high
states are higher than a period of the counter clock source.
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20-10
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
20.12 Specifications
Parameter
Min
Pulse width in the low and high states for
an external clock source, frequency
division by 2 disabled
Pulse width in the low and high states for
an external clock source, frequency
division by 2 enabled
Pulse width of external capture signals
Typ
Max
Unit
Conditions
500
ns
@ 1.2V
125
ns
@ 2.4V
100
ns
@ 1.2V
25
ns
@ 2.4V
1
fckcnt
s
Table 20-16: Timing specifications for the counters
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20-11
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
21.
The Voltage Level Detector
21.1
21.2
21.3
21.4
21.5
FEATURES ...................................................................................................................................... 21-2
OVERVIEW ...................................................................................................................................... 21-2
REGISTER MAP ................................................................................................................................ 21-2
INTERRUPT MAP .............................................................................................................................. 21-2
VLD OPERATION ............................................................................................................................. 21-3
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21-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
21.1 Features
ƒ
ƒ
can be switched off, on or simultaneously with CPU activities
generates an interrupt if power supply is below a pre-determined level
21.2 Overview
The Voltage Level Detector monitors the state of the system battery. It returns a logical high value (an interrupt) in
the status register if the supplied voltage drops below the user defined level (Vsb).
21.3 Register map
There are two registers in the VLD, namely RegVldCtrl and RegVldStat. Table 21-2 shows the mapping of control
bits and functionality of RegVldCtrl while Table 21-3 describes that for RegVldStat.
register name
RegVldCtrl
RegVldStat
Table 21-1: Vld registers
pos.
7-4
3
RegVldCtrl
-VldRange
rw
r
rw
reset
0000
0
nresetglobal
2-0
VldTune[2:0]
rw
000
nresetglobal
function
reserved
VLD detection voltage range for VldTune = “011”:
0 : 1.3V
1 : 2.55V
VLD tuning:
000 : +19 %
111 : -18 %
Table 21-2: RegVldCtrl
pos.
7-3
2
RegVldStat
-VldResult
rw
r
r
reset
00000
0 nresetglobal
1
0
VldValid
VldEn
r
rw
0 nresetglobal
0 nresetglobal
function
reserved
is 1 when battery voltage is below the detection
voltage
Indicates when VldResult can be read
VLD enable
Table 21-3: RegVldStat
21.4 Interrupt map
interrupt source
IrqVld
default mapping in the interrupt manager
RegIrqMid(2)
Table 21-4: Interrupt map
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21-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
21.5 VLD operation
The VLD is controlled by VldRange, VldTune and VldEn. VldRange selects the voltage range to be detected,
while VldTune is used to fine-tune this voltage level in 8 steps. VldEn is used to enable (disable) the VLD with a
1(0) value respectively. Disabled, the block will dissipate no power.
symbol
description
min
typ
max
unit
Note 1
Vth
TEOM
TPW
Threshold voltage
VldRange
0
VldTune
1.53
1.44
0
001
1.36
0
010
1.29
0
011
1.22
0
100
1.16
0
101
1.11
0
110
0
111
3.06
1
000
2.88
1
001
2.72
1
010
2.57
1
011
2.44
1
100
2.33
1
101
2.22
1
110
2.13
1
111
V
1.06
duration of
measurement
Minimum pulse width
detected
comments
trimming values:
2.0
2.5
ms
Note 2
875
1350
us
Note 2
000
Table 21-5: Voltage level detector operation
Note 1: absolute precision of the threshold voltage is ±10%.
Note 2: this timing is respected in case the internal RC or crystal oscillators are selected. Refer to the clock block
documentation in case the external clock is used.
To start the voltage level detection, the user sets bit VldEn. The measurement is started. After 2ms, the bit
VldValid is set to indicate that the measurement results are valid. From that time on, as long as the VLD is
enabled, a maskable interrupt request is sent if the voltage level falls below the threshold. One can also poll the
VLD and monitor the actual measurement result by reading the VldResult bit of the RegVldStat. This result is only
valid as long as the VldValid bit is ‘1’.
© Semtech 2006
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21-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
Figure 21-1 shows the timing of the VLD. An interrupt is generated on each rising edge of VldResult.
vbat
Vth
vld_en
vld_valid
vld_result
T EOM Τ PW
Τ PW
Figure 21-1: VLD timing
The threshold value should not be changed during the measurement.
© Semtech 2006
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21-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
22.
Low Power Comparators
22.1
22.2
22.3
22.4
FEATURES ............................................................................................................................22-2
OVERVIEW ............................................................................................................................22-2
REGISTER MAP ......................................................................................................................22-3
INTERRUPT MAP ....................................................................................................................22-4
© Semtech 2006
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22-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
22.1 Features
The cmpd peripheral implements four low power comparators.
ƒ Quiescent current consumption of 1.5µA
ƒ Very low switching current
ƒ Per channel configurable interrupt
ƒ Hysteresis
ƒ 1 MHz operation
22.2 Overview
Figure 22-1 gives an overview of this block:
Cmpd
3
RegCmpdCtrl(7:5)
4
RegCmpdStat(7:4)
IrqOnRisingCh
(edge selection)
4
4
comparator output
PB[7:4]
comparators (analog)
interrrupt
enable
EnIrqCh
(channel enable)
5
RegCmpdCtrl(4:0)
4
RegCmpdStat(3:0)
4x
Figure 22-1: Structure of Cmpd
© Semtech 2006
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22-2
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
The cmpd peripheral is a 4-channel low power comparator. It is intended to compare analog input signals with an
internally set threshold voltage. The comparator maintains low current consumption even if the input signal is very
close to the threshold. The comparison result of each channel can be used to generate an interrupt and/or is
available for polling.
The comparator can be enabled or disabled by programming the Enable bit in the RegCmpdCtrl register. When
disabled, the block consumes no current.
The peripheral has a single interrupt output which is a combination of the four channels. The combination can be
chosen by programming the RegCmpdCtrl register. The EnIrqCh[3:0] bits select the channel that can activate the
interrupt. The IrqOnRisingCh[2:0] bits indicate if the interrupt is generated on detection of the rising or falling edge
of the channel.
The comparison results of the peripheral can be read in the RegCmpdStat register. The bits CmpdOut[3:0] are
the value of the comparisons at the moment the register is read. The CmpdStat[3:0] indicates which channel
generated an interrupt since the register was last read.
Comparator specifications:
Sym
tpulse
IDDq
IDDstat
Vth
∆Vth/∆T
Vhyst
description
min
typ
max
Required input pulse width
500
Quiescent current
0.8
1.5
Maximal static current
1.5
Threshold voltage
0.7
1.1
Threshold temperature drift
-0.9
Threshold hysteresis
13
Table 22-1: Comparator specifications
unit
ns
µA
µA
V
mV/°C
mV
comments
VBAT≥1.2V
1
2
3
Comments:
1. The quiescent current is defined for a static input voltage <0.5V or >1.3V. The specified consumption is the
sum for all 4 channels.
2. The maximal static current is defined for any static input voltage between VDD and VSS. The specified
consumption is the sum for all 4 channels.
3. Defined with respect to VSS.
How to start the cmpd:
To avoid unwanted irqs one has first to configure the rising / falling edge of the detection (bit IrqOnRisingCh[2:0])
and to enable the comparator (bit Enable). Only after that may the user enable the channel interrupts with bit
EnIrqCh[3:0].
22.3 Register map
There are two registers in the Cmpd, namely RegCmpdStat and RegCmpdCtrl. Table 22-3 and Table 22-4 show
the mapping of the control bits and the functionality of these registers.
register name
RegCmpdStat
RegCmpdCtrl
Table 22-2: Cmpd registers
© Semtech 2006
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22-3
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
pos.
7
RegCmpdStat
CmpdStat[3]
rw
rc
reset
0 nresetglobal
6
CmpdStat[2]
rc
0 nresetglobal
5
CmpdStat[1]
rc
0 nresetglobal
4
CmpdStat[0]
rc
0 nresetglobal
3
2
1
0
CmpdOut[3]
CmpdOut[2]
CmpdOut[1]
CmpdOut[0]
r
r
r
r
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
function
1: if the channel 3 generated an interrupt
last read of this register
1: if the channel 2 generated an interrupt
last read of this register
1: if the channel 1 generated an interrupt
last read of this register
1: if the channel 0 generated an interrupt
last read of this register
Channel 3 comparator output
Channel 2 comparator output
Channel 1 comparator output
Channel 0 comparator output
since
since
since
since
Table 22-3: RegCmpdStat
pos.
7
6
5
4
3
2
1
0
RegCmpdCtrl
IrqOnRisingCh[2]
IrqOnRisingCh[1]
IrqOnRisingCh[0]
EnIrqCh[3]
EnIrqCh[2]
EnIrqCh[1]
EnIrqCh[0]
Enable
rw
rw
rw
rw
rw
rw
rw
rw
rw
reset
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
0 nresetglobal
function
1: an interrupt is generated on the rising edge
channels 2 and 3.
0: an interrupt is generated on the falling edge
channels 2 and 3.
1: an interrupt is generated on the rising edge
channel 1.
0: an interrupt is generated on the falling edge
channel 1.
1: an interrupt is generated on the rising edge
channel 0.
0: an interrupt is generated on the falling edge
channel 0.
1 enables interrupt on channel 3
1 enables interrupt on channel 2
1 enables interrupt on channel 1
1 enables interrupt on channel 0
Enables the comparator
of
of
of
of
of
of
Table 22-4: RegCmpdCtrl
22.4 Interrupt map
interrupt source
cmpd_irq
default mapping in the interrupt manager
RegIrqHigh[2]
Table 22-5: Interrupt map
© Semtech 2006
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22-4
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
23 Physical Dimensions
23.1 QFP type package
The QFP package dimensions are given in Figure 23-1 and Table 23-1
Figure 23-1. QFP type package
package
LQFP-80
LQFP-100
A
B
C
D
E
F
mm
14.0
mm
14.0
mm
1.4
mm
0.10
mm
0.32
mm
0.65
14.0
14.0
1.4
0.10
0.22
0.5
Table 23-1. QFP package dimensions
© Semtech 2006
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23-1
XE8802 Sensing Machine Data Acquisition MCU
with ZoomingADC™ and LCD driver
© Semtech 2005
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Contact Information
Semtech Corporation
Wireless and Sensing Products Division
200 Flynn Road, Camarillo, CA 93012
Phone (805) 498-2111 Fax : (805) 498-3804
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23-2