SEMTECH SX8724CWLTDT

SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DESCRIPTION
DATASHEET
FEATURES
The SX8724C is a data acquisition system based on
Semtech's low power ZoomingADC™ technology. It
directly connects most types of miniature sensors
with a general purpose microcontroller.
Up to 16-bit differential data acquisition
Programmable gain: (1/12 to 1000)
Sensor offset compensation up to 15 times full scale
of input signal
3 differential or 6 single-ended signal inputs
Programmable Resolution versus Speed versus
Supply current
Digital outputs to bias Sensors
Internal or external voltage reference
Internal time base
Low-power (250 uA for 16b @ 250 S/s)
Fast I2C interface with external address option, no
clock stretching required
With 3 differential inputs, it can adapt to multiple
sensor systems. Its digital outputs are used to bias or
reset the sensing elements.
APPLICATIONS
ORDERING INFORMATION
Industrial pressure sensing
Industrial temperature sensing
Industrial chemical sensing
Barometer
Compass
DEVICE
PACKAGE
REEL QUANTITY
SX8724CWLTDT
MLPQ-W-16 4x4
1000
- Available in tape and reel only
- WEEE/RoHS compliant, Pb-Free and Halogen Free.
FUNCTIONAL BLOC DIAGRAM
SX8724C
VBATT
TM
-
VREF
+
+
-
-
ZoomingADC
REF MUX
+
AC2
AC3
AC4
AC5
SIGNAL MUX
AC0
AC1
PGA
ADC
READY
MCU
AC6
AC7
CONTROL LOGIC
D0
D1
D2
GPIO
CHARGE
PUMP
4MHz
OSC
I2C
SCL
SDA
D3
VPUMP
VSS
Revision 1.01
© Semtech
January 2011
Page 1
www.semtech.com/products/
SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
TABLE OF CONTENT
Section
Page
ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1
2
2.1
2.1.1
2.1.2
2.1.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
POR Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
4
5
6
6.1
6.2
6.3
6.3.1
6.4
6.5
6.5.1
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.3
7.4
7.5
7.6
7.6.1
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
8
8.1
8.2
9
9.1
9.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bloc diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional Operating Mode: External Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up from sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZoomingADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acquisition Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Gain Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGA & ADC Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZoomingADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Multiplexers (AMUX and VMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
First Stage Programmable Gain Amplifier (PGA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Second Stage Programmable Gain Amplifier (PGA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Third Stage Programmable Gain Amplifier (PGA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGA Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Sampling Frequency (fs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Sampling Ratio (OSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Number of Elementary Conversions (Nelconv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Time & Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous-Time vs. On-Request Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Code Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain Configuration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 1.01
© Semtech
January 2011
Page 2
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www.semtech.com/products/
SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
TABLE OF CONTENT
Section
9.2.1
9.3
9.4
9.4.1
9.4.2
9.4.3
9.4.4
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
11
11.1
11.1.1
11.2
11.3
11.3.1
11.3.2
11.4
11.5
11.6
Page
Address Set Externally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C General Call Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writing a Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading in a Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Writing in Several Consecutive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading from Several Consecutive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Memory Map and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Performances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switched Capacitor Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integral Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain Error and Offset Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
40
40
40
40
41
42
42
42
43
43
44
46
47
47
48
49
50
50
54
54
57
58
FAMILY OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12
13
Comparizon table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Comparizon by package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14
15
16
17
18
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to Evaluate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline Drawing: MLPQ-W16-4x4-EP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Land Pattern Drawing: 4x4MLPQ-W16-EP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tape and Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 1.01
© Semtech
January 2011
Page 3
63
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www.semtech.com/products/
SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
ELECTRICAL SPECIFICATIONS
1 Absolute Maximum Ratings
Note
Table 1.
The Absolute Maximum Ratings, in table below, are stress ratings only.
Functional operation of the device at conditions other than those indicated in
the Operating Conditions sections of this specification is not implied.
Exposure to the absolute maximum ratings, where different to the operating
conditions, for an extended period may reduce the reliability or useful lifetime
of the product.
Absolute Maximum Ratings
Parameter
Symbol
Condition
Min
Max
Units
Power supply
VBATT
VSS - 0.3
6.5
V
Storage temperature
TSTORE
-55
150
°C
Temperature under bias
TBIAS
-40
140
°C
Input voltage
VINABS
All inputs
VSS - 300
VBATT + 300
mV
260
°C
Human Body Model ESD
2000
V
100
mA
Peak reflow temperature
ESD conditions
TPKG
ESDHBM
Latchup
Revision 1.01
© Semtech
January 2011
Page 4
www.semtech.com/products/
SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
2 Operating Conditions
Unless otherwise specified: VREF,ADC = VBATT, VIN = 0V, Over-sampling frequency fS = 250 kHz, PGA3 on with Gain = 1,
PGA1&PGA2 off, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IbAmpAdc[1:0] = IbAmpPga[1:0] = '01').
For resolution n = 12 bits: OSR = 32 and NELCONV = 4.
For resolution n = 16 bits: OSR = 256 and NELCONV = 2.
Bandgap chopped at NELCONV rate. If VBATT < 4.2V, Charge Pump is forced on. If VBATT > 4.2V, Charge Pump is forced off.
Table 2.
Operating conditions limits
Parameter
Symbol
Power supply
Comment/Condition
Min
Typ
Max
Unit
VBATT
2.4
5.5
V
TOP
-40
125
°C
Typ
Max
Unit
16 b @ 250 Sample/s
ADC, fs = 125 kHz
250
350
16 b @ 1kSample/s
PGA3 + ADC, fs = 500 kHz
700
900
16 b + gain 1000 @ 1kSample/s
PGA3,2,1 + ADC, fs = 500 kHz
1000
1350
16 b @ 250 Sample/s
ADC, fs = 125 kHz
150
16 b @ 1 kSample/s
PGA3 + ADC, fs = 500 kHz
300
16 b + gain 1000 @ 1kSample/s
PGA3,2,1 + ADC, fs = 500 kHz
850
@25°C
75
up to 85°C
100
@125°C
150
200
500
575
Operating temperature
.
Table 3.
Electrical Characteristics
Parameter
Symbol
Comment/Condition
Min
CURRENT CONSUMPTION1
Active current, 5.5V
IOP55
Active current, 3.3V
IOP33
Sleep current
ISLEEP
μA
μA
nA
TIME BASE
Max ADC Over-Sampling frequency
fSmax
ADC Over-Sampling frequency drift
fST
@25°C
425
0.15
kHz
% / °C
DIGITAL I/O
VBATT
0.7
Input logic high
VIH
Input logic low
VIL
Output logic high
VOH
IOH < 4 mA
Output logic low
VOL
IOL < 4 mA
0.3
VBATT
VBATT-0.4
V
0.4
V
0.7
VBATT
SCL and SDA I/O
VIH
Input logic high
Revision 1.01
© Semtech
January 2011
Page 5
www.semtech.com/products/
SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
Table 3.
DATASHEET
Electrical Characteristics
Parameter
Symbol
Input logic low
Comment/Condition
Min
Typ
VIL
Max
Unit
0.25
VBATT
100
nA
1.25
V
Leakages currents
Digital input mode,
no pull-up or pull-down
-100
VBG
VBATT > 3V
1.19
Variation over Temperature
VBGT
VBATT > 3V, over Temperature
-1.5
Total Output Noise
VBGN
VBATT > 3V
Input leakage current
ILeakIn
VREF: Internal Bandgap Reference
Absolute output voltage
1.
1.22
+1.5
%
1
mVrms
The device can be operated in either active or sleep states. The Sleep state is complete shutdown, but the active state can have a variety of
different current consumptions depending on the settings. Some examples are given here: The Sleep state is the default state after
power-on-reset. The chip can then be placed into an active state after a valid I2C communication is received.
Table 4.
ZoomingADC Specifications
Parameter
Symbol
Condition
Min
Gain=1, OSR=32, VREF=5V. Note 1
-2.42
Typ
Max
Unit
+2.42
V
ANALOG INPUT CHARACTERISTICS
Differential Input Voltage Range
VIN = VINP-VINN
Gain=100, OSR=32, VREF=5V
-24.2
+24.2
mV
Gain=1000, OSR=32, VREF=5V
-2.42
+2.42
mV
Note 1
PROGRAMMABLE GAIN AMPLIFIER
Total PGA Gain
GDTOT
1/12
1000
V/V
PGA1 Gain
GD1
(see Table 11, page 22)
1
10
V/V
PGA2 Gain
GD2
(see Table 12, page 23)
1
10
V/V
PGA3 Gain
GD3
Step = 1/12 V/V
(see Table 13, page 23)
1/12
127/12
V/V
+3
%
Gain Settings Precision (each stage)
Gain ≥ 1
-3
±0.5
±5
Gain Temperature Dependance
ppm / °C
PGA2 Offset
GDOFF2
Step = 0.2 V/V
(see Table 12, page 23)
-1
+1
V/V
PGA3 Offset
GDOFF3
Step = 1/12 V/V
(see Table 13, page 23)
-63/12
+63/12
V/V
+3
%
Offset Settings Precision
(PGA2 or PGA3)
Note 2
-3
Offset Temperature Dependance
Input Impedance on PGA1
(see section 11.1, page 47)
Input Impedance on PGA2,3
Output RMS Noise per over-sample
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±0.5
±5
ppm / °C
Gain = 1. Note 3
1200
1350
kΩ
Gain = 10. Note 3
250
300
kΩ
Gain = 1. Note 3
150
200
kΩ
PGA1. Note 4
205
μV
PGA2. Note 4
340
μV
PGA3. Note 4
365
μV
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ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
Table 4.
DATASHEET
ZoomingADC Specifications
Parameter
Symbol
Condition
Min
Typ
Max
Unit
16
Bits
ADC STATIC PERFORMANCES
Resolution
(No Missing Codes)
n
Note 5
Note 6
6
±0.15
%
±1
LSB
resolution n = 12 bits. Note 9
±0.6
LSB
resolution n = 16 bits. Note 9
±1.5
LSB
resolution n = 12 bits. Note 10
±0.5
LSB
resolution n = 16 bits. Note 10
±0.5
LSB
Gain Error
Note 7
Offset Error
n = 16 bits. Note 8
Integral Non-Linearity
INL
Differential Non-Linearity
DNL
Power Supply Rejection Ratio
DC
PSRR
VBATT = 5V +/- 0.3V. Note 11
78
dB
VBATT = 3V +/- 0.3V. Note 11
72
dB
n = 12 bits. Note 12
133
fs cycles
n = 16 bits. Note 12
517
fs cycles
n = 12 bits, fs = 250 kHz
1.88
kSps
n = 16 bits, fs = 250 kHz
0.483
kSps
Note 13
(see Table 12, page 23)
OSR
fs cycles
VBATT = 5.5V/3.3V
285/210
μA
PGA1 Consumption
VBATT = 5.5V/3.3V
104/80
μA
PGA2 Consumption
VBATT = 5.5V/3.3V
67/59
μA
PGA3 Consumption
VBATT = 5.5V/3.3V
98/91
μA
ADC DYNAMIC PERFORMANCES
Conversion Time
TCONV
Throughput Rate (Continuous Mode)
1/TCONV
PGA Stabilization Delay
ZADC ANALOG QUIESCENT CURRENT
ADC Only Consumption
IQ
ANALOG POWER DISSIPATION : All PGAs & ADC Active
Normal Power Mode
VBATT = 5.5V/3.3V. Note 14
4.0/2.0
mW
3/4 Power Reduction Mode
VBATT = 5.5V/3.3V. Note 15
3.2/1.6
mW
1/2 Power Reduction Mode
VBATT = 5.5V/3.3V. Note 16
2.4/1.1
mW
1/4 Power Reduction Mode
VBATT = 5.5V/3.3V. Note 17
1.5/0.7
mW
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
Gain defined as overall PGA gain GDTOT = GD1 x GD2 x GD3. Maximum input voltage is given by: VIN,MAX = ±(VREF / 2) (OSR / OSR+1).
Offset due to tolerance on GDoff2 or GDoff3 setting. For small intrinsic offset, use only ADC and PGA1.
Measured with block connected to inputs through Amux block. Normalized input sampling frequency for input impedance is fS = 500 kHz
(fS max, worst case). This figure must be multiplied by 2 for fS = 250 kHz, 4 for fS = 125 kHz. Input impedance is proportional to 1/fS.
Figure independent from gain and sampling frequency. fS. The effective output noise is reduced by the over-sampling ratio
Resolution is given by n = 2 log2(OSR) + log2(NELCONV ). OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1, 2, 4 or 8.
If a ramp signal is applied to the input, all digital codes appear in the resulting ADC output data.
Gain error is defined as the amount of deviation between the ideal (theoretical) transfer function and the measured transfer function
(with the offset error removed).
Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). For 1 LSB offset, NELCONV must be at least 2.
INL defined as the deviation of the DC transfer curve of each individual code from the best-fit straight line. This specification holds over
the full scale.
DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes.
Values for Gain = 1. PSRR is defined as the amount of change in the ADC output value as the power supply voltage changes.
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(12)
(13)
(14)
(15)
(16)
(17)
DATASHEET
Conversion time is given by: TCONV = (NELCONV (OSR + 1) + 1) / fS. OSR can be set between 8 and 1024, in powers of 2. NELCONV can be set to 1,
2, 4 or 8.
PGAs are reset after each writing operation to registers RegACCfg1-5, corresponding to change of configuration or input switching. The
ADC should be started only some delay after a change of PGA configuration through these registers. Delay between change of configuration of PGA or input channel switching and ADC start should be equivalent to OSR (between 8 and 1024) number of cycles. This is done by
writing bit Start several cycles after PGA settings modification or channel switching. This delay does not apply to conversions made without the PGAs.
Nominal (maximum) bias currents in PGAs and ADC, i.e. IbAmpPga[1:0] = '11' and IbAmpAdc[1:0] = '11'.
Bias currents in PGAs and ADC set to 3/4 of nominal values, i.e. IbAmpPga[1:0] = '10', IbAmpAdc[1:0] = '10'.
Bias currents in PGAs and ADC set to 1/2 of nominal values, i.e. IbAmpPga[1:0] = '01', IbAmpAdc[1:0] = '01'.
Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IbAmpPga[1:0] = '00', IbAmpAdc[1:0] = '00'.
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2.1 Timing Characteristics
Table 5.
General timings
Parameter
Symbol
Comment/Condition
Min
Typ
Max
Unit
ADC INTERRUPT (READY) TIMING SPECIFICATIONS
READY pulse width
Note 1
tIRQ
1
1/fs
STARTUP TIMES
Startup sequence time at POR
tSTART
800
μs
Time to enable RC from Sleep after an
I2C command
tRCEN
450
μs
(1)
The READY pulse indicates End of Conversion. This is a Positive pulse of duration equal to one cycle of the ADC sampling rate in “continuous mode”.
See also Figure 17, page 33.
2.1.1 POR Waveforms
At device power-on or after a software reset
I2C com
STARTUP
SEQUENCE
POR
RC enabling
tPOR
tRCEN
SLEEP
Self
calibration
RC disabling
WAKE-UP
SEQUENCE
RC enabling
tRCEN
RC stop
Figure 1. Power-On-Reset waveform
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2.1.2 I2C interface timings
Table 6.
Digital interface
STANDARD-MODE
Parameter
FAST-MODE
Symbol
Unit
Min
Typ
Max
Min
Typ
Max
I2C TIMING SPECIFICATIONS Note 1
SCL clock frequency
fSCL
0
tSCLTO
35
35
ms
SCL Low Pulsewidth
tL
4.7
1.3
μs
SCL High Pulsewidth
tH
4.0
0.6
μs
Start Condition Hold Time
tSCH
0.6
0.6
μs
Data Setup Time
tDS
250
100
Note 3
ns
Data Hold Time
tDH
0
Note 4
Setup Time for Repeated Start
tRSU
4.7
0.6
μs
Stop Condition Setup Time
tPSU
4.0
0.6
μs
Bus Free Time between a STOP
Condition and a START Condition
tBF
4.7
1.3
μs
Pulsewidth of Spike Suppressed
tSUP
Capacitive load for each bus line
CB
Noise margin at the LOW level for each
connected device (including
hysteresis)
VnL
0.1VBATT
0.1VBATT
V
Noise margin at the HIGH level for each
connected device (including
hysteresis)
VnH
0.2VBATT
0.2VBATT
V
SCL timeout ( optional mode ) Note 2
(1)
(2)
(3)
(4)
(5)
100
3.45
0
400
0
100
0.9
100
400
kHz
μs
ns
400
pF
All timings specifications are referred to VILmin and VIHmax voltage levels defined for the SCL and SDA pins.
The digital interface is reset if the SCL is low more than tSCLTO duration. This is the default mode at startup. The timeout can be disabled by
register setting.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system.
The device internally provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according to Table 6 are allowed.
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2.1.3 I2C timing Waveforms
tPSU
tSCH
SCL
tDS
tH
tDH
1
2-7
tDS
tDH tRSU
tR
tF
8
9
1
LSB
ACK
MSB
tBF
tL
SDA
MSB
tSUP
Stop
Start
tR
tF
RepStart
Figure 2. Definition of timing for F/S-mode on the I2C-bus.
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CIRCUIT DESCRIPTION
2
AC7
3
AC4
4
VPUMP
SCL
SDA
14
13
SX8724C
(Top view)
AC5
5
6
7
8
READY
AC6
15
VSS
1
16
VBATT
AC3
AC2
3 Pin Configuration
12
D0
11
D2
10
D3
9
D1
4 Marking Information
8724C
YYWW
XXXXX
XXXXX
nnnnn
yyww
xxxxx
xxxxx
= Part Number
= Date Code1
= Semtech Lot Number
1.Date codes and Lot numbers starting with the ‘E’ character are used for Engineering samples
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5 Pin Description
Note
The bottom pin is internally connected to VSS. It should also be connected to
VSS on PCB to reduce noise and improve thermal behavior.
Pin
Name
Type
Function
1
AC3
Analog Input
Differential sensor input in conjunction with AC2
2
AC6
Analog Input
Differential sensor input in conjunction with AC7
3
AC7
Analog Input
Differential sensor input in conjunction with AC6
4
AC4
Analog Input
Differential sensor input in conjunction with AC5
5
AC5
Analog Input
Differential sensor input in conjunction with AC4
6
VBATT
Power Input
2.4V to 5.5V power supply
7
VSS
Power Input
Chip ground
8
READY
Digital Output
Conversion complete flag.
Digital output sensor drive (VBATT or VSS)
9
D1
Digital IO + analog input
VREF input in optional operating mode
10
D3
Digital IO
Digital output sensor drive (VBATT or VSS)
11
D2
Digital IO
Digital output sensor drive (VBATT or VSS)
I2C address bit 1. Msb address bits are fuse programmed.
Digital output sensor drive (VBATT or VSS)
12
D0
Digital IO + analog output
VREF output in optional operating mode
I2C address bit 0. MSB address bits are fuse programmed.
13
SDA
Digital IO
I2C data line
14
SCL
Digital IO
I2C clock line. Up to 400 kHz.
15
VPUMP
Power IO
Charge pump output. Raises analog switch supply above VBATT if VBATT supply is
too low. Recommended range for capacitor is 1nF to 10 nF. Connect the
capacitor to ground.
16
AC2
Analog Input
Differential sensor input in conjunction with AC3
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6 General Description
The SX8724C is a complete low-power acquisition path with programmable gain, acquisition speed and resolution.
6.1 Bloc diagram
SX8724C
VBATT
-
VREF
+
+
-
-
ZoomingADC
REF MUX
+
TM
SIGNAL MUX
AC0
AC1
AC2
AC3
AC4
AC5
PGA
ADC
READY
AC6
AC7
CONTROL LOGIC
D0
D1
GPIO
D2
CHARGE
PUMP
4MHz
OSC
I2C
SCL
SDA
D3
VPUMP
VSS
Figure 3. SX8724C bloc diagram
6.2 VREF
The internally generated VREF is a trimmed bandgap reference with a nominal value of 1.22V that provides a stable
voltage reference for the ZoomingADC.
This reference voltage is directly connected to one of the ZoomingADC reference multiplexer inputs.
The bandgap voltage stability is only guaranteed for VBATT voltages of 3V and above. As VBATT drops down to 2.4V, the
bandgap voltage could reduce by up to 50mV.
The bandgap has relatively weak output drive so it is recommended that if the bandgap is required as a signal input
then PGA1 must be enabled with gain = 1.
6.3 GPIO
The GPIO block is a multipurpose 4 bit input/output port. In addition to digital behavior, D0 and D1 pins can be
programmed as analog pins in order to be used as output (reference voltage monitoring) and input for an external
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reference voltage (For further details see Figure 6, Figure 7, Figure 8 and Figure 9). Each port terminal can be
individually selected as digital input or output.
RegOut[4]
RegOut[0]
0
D0/VREFOUT
1
RegIn[0]
RegMode[1]
Internal +
Bandgap
reference -
V BG
1.22V
0
VREF
1
RegMode [0]
ZoomingADC
RegOut[5]
RegOut [1]
1
D1/VREFIN
0
RegIn [1]
Figure 4. GPIO bloc diagram
RegOut [6]
RegOut [2]
D2
RegIn [2]
RegOut [7]
RegOut [3]
D3
RegIn [3]
Figure 5. Digital IO bloc diagram
The direction of each bit within the GPIO block (input only or input/output) can be individually set using the bits of the
RegOut (address 0x40) register. If D[x]Dir = 1, both the input and output buffer are active on the corresponding GPIO
block pin. If D[x]Dir= 0, the corresponding GPIO block pin is an input only and the output buffer is in high impedance.
After power on reset the GPIO block pins are in input/output mode (D[x]Dir are reset to 1).
The input values of GPIO block are available in RegIn (address 0x41) register (read only). Reading is always direct - there
is no debounce function in the GPIO block. In case of possible noise on input signals, an external hardware filter has to
be realized. The input buffer is also active when the GPIO block is defined as output and the effective value on the pin
can be read back.
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Data stored in the LSB bits of RegOut register are outputted at GPIO block if D[x]Dir= 1. The default values after power
on reset is low (0).
The digital pins are able to deliver a driving current up to 8 mA.
When the bits VrefD0Out and VrefD1In in the RegMode (address 0x70) register are set to 1 the D0 and D1 pins digital
behavior are automatically bypassed in order to either input or output the voltage reference signals.
6.3.1 Optional Operating Mode: External Vref
D0 and D1 are multi-functional pins with the following functions in different operating modes (see RegMode register
for control settings):
0
D0/VREFOUT
0
GPIO
D0/VREFOUT
1
RegMode[1] = 0
Internal +
Bandgap
reference -
GPIO
1
RegMode[1] = 0
VBG
0
VREF
1
Internal +
Bandgap
reference -
ZoomingADC
0
RegMode[0] = 0
1
GPIO
0
D1/VREFIN
Figure 6. D0 and D1 are Digital Inputs / Outputs
0
D0/VREFOUT
0
GPIO
D0/VREFOUT
GPIO
1
RegMode[1] = 1
RegMode[1] = 1
VBG
VBG
0
VREF
1
Internal +
Bandgap
reference -
ZoomingADC
RegMode[0] = 0
0
0
VREF
1
ZoomingADC
RegMode[0] = 1
1
D1/VREFIN
GPIO
0
Figure 7. D1 is Reference Voltage Input and D0 is Digital
Input / Output
1
Internal +
Bandgap
reference -
ZoomingADC
RegMode[0] = 1
1
D1/VREFIN
VREF
1
1
GPIO
D1/VREFIN
Figure 8. D1 is Digital Input / Output and D0 Reference
Voltage Output
0
GPIO
Figure 9. D0 is Reference Voltage Output and D1 is Reference
Voltage Input
This allows external monitoring of the internal bandgap reference or the ability to use an external reference input for
the ADC, or the option to filter the internal VREF output before feeding back as VREF,ADC input. The internally generated
VREF is a trimmed as ADC reference with a nominal value of 1.22V. When using an external VREF,ADC input, it may have
any value between 0V and VBATT. Simply substitute the external value for 1.22 V in the ADC conversion calculations.
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6.4 Charge Pump
This block generates a supply voltage able to power the analog switch drive levels on the chip higher than VBATT if
necessary.
If VBATT voltage drops below 4.2V then the block should be activated. If VBATT voltage is greater than 4.2V then VBATT
may be switched straight through to the VPUMP output. If the charge pump is not activated then VPUMP = VBATT.
If control input bit MultForceOff = 1 in RegMode (address 0x70) register then the charge pump is disabled and VBATT is
permanently connected to VPUMP output.
If control input bit MultForceOn = 1 in RegMode register then the charge pump is permanently enabled. This overrides
MultForceOff bit in RegMode register.
An external capacitor is required on VPUMP pin. This capacitor should be large enough to ensure that generated
voltage is smooth enough to avoid affecting conversion accuracy but not so large that it gives an unacceptable settling
time. A recommended value is around 2.2nF.
6.5 RC Oscillator
This block provides the master clock reference for the chip. It produces a clock at 4 MHz which is divided internally in
order to generate the clock sources needed by the other blocks.
The oscillator technique is a low power relaxation design and it is designed to vary as little as possible over
temperature and supply voltage.
This oscillator is trimmed at manufacture chip test.
The RC oscillator will start up after a chip reset to allow the trimming values to be read and calibration registers and I2C
address set to their default fused values. Once this has been done, the oscillator will be shut down and the chip will
enter a sleep state while waiting for an I2C communication.
The worst case duration from reset ( or POR ) to the sleep state is 800us.
6.5.1 Wake-up from sleep
When the device is in sleep state, the RC oscillator will start up after a communication. The start up sequence for the RC
oscillator is 450us in worst case.
During this time, the internal blocs using the RC can not be used: no ADC conversion can be started.
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7 ZoomingADC
7.1 Overview
The ZoomingADC is a complete and versatile low-power analog front-end interface typically intended for sensing
applications. In the following text the ZoomingADC will be referred as ZADC.
The key features of the ZADC are:
Programmable 6 to 16-bit dynamic range over-sampled ADC
Flexible gain programming between 1/12 and 1000
Flexible and large range offset compensation
Differential or single-ended input
2-channel differential reference inputs
Power saving modes
AMUX
Analog
Inputs
Reference
Inputs
VSS
VREF
AC2
AC3
AC4
AC5
AC6
AC7
VIN
VD1
±Vin
S
PGA1
VD2
VIN,ADC
±Vin
±Vin
±Vin
±Voff PGA2
±Voff PGA3
±Vref
ADC
VREF,ADC
VBATT
VSS
VREF
VSS
VMUX
ANALOG ZOOM
Figure 10. ZADC General Functional Block Diagram
The total acquisition chain consists of an input multiplexer, 3 programmable gain amplifier stages and an over sampled
A/D converter. The reference voltage can be selected on two different channels. Two offset compensation amplifiers
allow for a wide offset compensation range. The programmable gain and offset allow the application to zoom in on a
small portion of the reference voltage defined input range.
7.1.1 Acquisition Chain
Figure 10, page 18 shows the general block diagram of the acquisition chain (AC). A control block (not shown in
Figure 10) manages all communications with the I2C peripheral. The clocking is derived from the internal 4 MHz
Oscillator.
Analog inputs can be selected through an 8 input multiplexer, while reference input is selected between two
differential channels. It should however be noted that only 7 acquisition channels (including the VREF) are available
when configured as single ended since the input amplifier is always operating in differential mode with both positive
and negative input selected through the multiplexer.
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The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of an
input and reference signals VIN and VREF,ADC combination, the input voltage is modulated and amplified through
stages 1 to 3. Fine gain programming up to 1'000 V/V is possible. In addition, the last two stages provide
programmable offset. Each amplifier can be bypassed if needed.
The output of the cascade of PGA is directly fed to the analog-to-digital converter (ADC), which converts the signal
VIN,ADC into digital.
Like most ADCs intended for instrumentation or sensing applications, the ZoomingADCTM is an over-sampled
converter 1. The ADC is a so-called incremental converter; with bipolar operation (the ADC accepts both positive and
negative differential input voltages). In first approximation, the ADC output result relative to full-scale (FS) delivers the
quantity:
OUTADC VIN , ADC
≅
FS / 2
VREF / 2
Equation 1
in two's complement (see Equation 18 and Equation 19, page 33 for details). The output code OUTADC is -FS / 2 to +
FS / 2 for VIN,ADC = -VREF,ADC / 2 to + VREF,ADC / 2 respectively. As will be shown, VIN,ADC is related to input voltage VIN by
the relationship:
VIN , ADC = GDTOT ⋅VIN − GDoffTOT ⋅ S ⋅VREF [V ]
Equation 2
where GDTOT is the total PGA gain, GDOFFTOT is the total magnitude of PGA offset and S is the sign of the offset (see
Table 9, page 21).
7.1.2 Programmable Gain Amplifiers
As seen in Figure 10, page 18, the zooming function is implemented with three programmable gain amplifiers (PGA).
These are:
PGA1: coarse gain tuning
PGA2: medium gain and offset tuning
PGA3: fine gain and offset tuning. Should be set ON for high linearity data acquisition
All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation and
gain, as well as the offset of stages 2 and 3. These functions are examined hereafter.
1.
Over-sampled converters are operated with a sampling frequency fS much higher than the input signal's Nyquist rate (typically fS is 201'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include
digital decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications.
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7.1.3 PGA & ADC Enabling
Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to the
word Enable and the coding given in Table 7. To reduce power dissipation, the ADC can also be inactivated while idle.
Table 7. ADC and PGA Enabling
Enable
(RegACCfg1[3:0])
Block
XXX0
XXX1
ADC disabled
ADC enabled
XX0X
XX1X
PGA1 disabled
PGA1 enabled
X0XX
X1XX
PGA2 disabled
PGA2 enabled
0XXX
1XXX
PGA3 disabled
PGA3 enabled
7.2 ZoomingADC Registers
The system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain (RegAcCfg0 to
RegAcCfg5), and two registers are used to store the output code of the analog-to-digital conversion (RegAcOutMsb &
Lsb).
Table 8. Periferal Registers to Configure the Acquisition Chain (AC) and to Store the Analog-to-Digital
Conversion (ADC) Result
Bit position
Register Name
7
6
5
4
2
1
0
Out[7:0]
Note 1
RegACOutLsb
Out[15:8]
RegACOutMsb
RegACCfg0
Default values:
3
Start
0, Note 2
SetNelconv
01, Note 3
SetOsr
010, Note 4
Continuous
0, Note 5
RegACCfg1
Default value:
IbAmpAdc
11, Note 7
IbAmpPga
11, Note 8
Enable
0000, Note 9
RegACCfg2
Default value:
SetFs
00, Note 10
Pga2Gain
00, Note 12
Pga2Offset
0000, Note 14
RegACCfg3
Default value:
Pga1Gain
0, Note 11
Pga3Gain
0001100, Note 13
RegACCfg4
Default value:
0
Pga3Offset
0000000, Note 15
RegACCfg5
Default value:
Busy
0, Note 16
Def
0, Note 17
Amux
00000, Note 18
0, Note 6
Vmux
0, Note 19
(r = read; w = write; rw = read & write)
(1)
(2)
Out: (r) digital output code of the analog-to-digital converter. (MSB = Out[15])
Start: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0.
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(3)
SetNelconv: (rw) sets the number of elementary conversions to 2(SetNelconv[1:0]). To compensate for offsets, the input signal is chopped
between elementary conversions (1,2,4,8).
(4)
(5)
SetOsr: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SetOsr[2:0]). OSR = 8, 16, 32, ..., 512, 1024.
Continuous: (rw) setting this bit starts a conversion. When this bis is 1, A new conversion will automatically begin directly when the previous one is finished.
Reserved
IbAmpAdc: (rw) sets the bias current in the ADC to 0.25 x (1+ IbAmpAdc[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
IbAmpPga: (rw) sets the bias current in the PGAs to 0.25 x (1+IbAmpPga[1:0]) of the normal operation current (25, 50, 75 or 100% of nominal current). To be used for low-power, low-speed operation.
Enable: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that are disabled are
bypassed.
SetFs: (rw) These bits set the over sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency, the
sampling frequency is given as: 11 ' 500 kHz, 10 ' 250 kHz, 01 ' 125 kHz, 00 ' 62.5 kHz.
Pga1Gain: (rw) sets the gain of the first stage: 0 ' 1, 1 ' 10.
Pga2Gain: (rw) sets the gain of the second stage: 00 ' 1, 01 ' 2, 10 ' 5, 11 ' 10.
Pga3Gain: (rw) sets the gain of the third stage to Pga3Gain[6:0] 1/12.
Pga2Offset: (rw) sets the offset of the second stage between -1 and +1, with increments of 0.2. The MSB gives the sign (0 positive, 1 negative); amplitude is coded with the bits Pga2Offset[5:0].
Pga3Offset: (rw) sets the offset of the third stage between -5.25 and +5.25, with increments of 1/12. The MSB gives the sign (0 positive, 1
negative); amplitude is coded with the bits Pga3Offset[5:0].
Busy: (r) set to 1 if a conversion is running.
Def: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary conversions, over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one.
Amux(4:0): (rw) Amux[4] sets the mode (0 ' differential inputs, 1 ' single ended inputs with A0= common reference) Amux[3] sets the sign
(0 ' straight, 1' cross) Amux[2:0] sets the channel.
Vmux: (rw) sets the differential reference channel (0 ' VBATT, 1 ' VREF).
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
7.3 Input Multiplexers (AMUX and VMUX)
The ZoomingADC has analog inputs AC0 to AC7 and reference inputs. Let us first define the differential input voltage
VIN and reference voltage VREF,ADC respectively as:
VIN = VINP −VINN
[V ]
Equation 3
VREF = VREFP − VREFN
[V ]
Equation 4
As shown in Table 9, the inputs can be configured in two ways: either as 4 differential channels (VIN1= AC1 - AC0,... , VIN4
= AC7 - AC6), or AC0 can be used as a common reference, providing 7 signal paths all referred to AC0. The control word
for the analog input selection is Amux. Notice that the Amux bit 4 controls the sign of the input voltage.
Table 9. Analog Input Selection
Amux
(RegACCfg5[5:1])
VINP
Amux
(RegACCfg5[5:1])
VINN
Sign S = 1
00x00
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VINP
VINN
AC1(VSS)
AC0(VREF)
Sign S = -1
AC1(VREF)
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AC0(VSS)
01x00
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Table 9. Analog Input Selection
Amux
(RegACCfg5[5:1])
Amux
(RegACCfg5[5:1])
VINN
VINP
Sign S = 1
VINP
VINN
Sign S = -1
00x01
AC3
AC2
01x01
AC2
AC3
00x10
AC5
AC4
01x10
AC4
AC5
00x11
AC7
AC6
01x11
AC6
AC7
10000
AC0(VSS)
11000
AC0(VSS)
10001
AC1(VREF)
11001
AC1(VREF)
10010
AC2
11010
AC2
10011
AC3
10100
AC4
11100
AC4
10101
AC5
11101
AC5
10110
AC6
11110
AC6
10111
AC7
11111
AC7
11011
AC0(VSS)
AC0(VSS)
AC3
Similarly, the reference voltage is chosen among two differential channels (VREF = VBATT-VSS, VREF = VBG-VSS or VREF =
VREF,IN-VSS) as shown in Table 10. The selection bit is Vmux. The reference inputs VREFP and VREFN (common-mode) can
be up to the power supply range.
Table 10. Analog reference Input Selection
1.
Vmux
(RegACCfg5[0])
VREFP
VREFN
0
VREF = VBATT
VSS
1
VREF = VBG or VREF,IN1
VSS
External voltage reference on D1 GPIO pin. See section 6.3 on page 14 about
GPIO and “RegMode[0x70]” on page 46.
7.4 First Stage Programmable Gain Amplifier (PGA1)
The first stage can have a buffer function (unity gain) or provide a gain of 10 (see Table 11). The voltage VD1 at the
output of PGA1 is:
VD1 = GD1 ⋅ VIN
[V ]
Equation 5
where GD1 is the gain of PGA1 (in V/V) controlled with the Pga1Gain bit.
Table 11. PGA1 gain settings
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Pga1Gain bit
(RegACCfg3[7])
PGA1 gain [V/V]
GD1 [V/V]
0
1
1
10
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7.5 Second Stage Programmable Gain Amplifier (PGA2)
The second PGA has a finer gain and offset tuning capability, as shown in Table 12. The VD2 voltage at the output of
PGA2 is given by:
VD 2 = GD2 ⋅ VD1 − GDoff 2 ⋅ S ⋅ VREF
[V ]
Equation 6
where GD2 and GDOFF2 are respectively the gain and offset of PGA2 (in V/V). These are controlled with the words
Pga2Gain[1:0] and Pga2Offset[3:0].
Table 12. PGA2 gain and offset settings
Pga2Gain bitfield
(RegACCfg2[5:4])
PGA2 gain [V/V]
GD2 [V/V]
Pga2Offset bitfield
(RegACCfg2[3:0])
PGA2 offset
GDOFF2 [V/V]
00
1
0000
0
01
2
0001
+0.2
10
5
0010
+0.4
11
10
0011
+0.6
0100
+0.8
0101
+1
1000
0
1001
-0.2
1010
-0.4
1011
-0.6
1100
-0.8
1101
-1.0
7.6 Third Stage Programmable Gain Amplifier (PGA3)
The finest gain and offset tuning is performed with the third and last PGA stage, according to the coding of Table 13.
Table 13. PGA3 Gain and Offset Settings
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Pga3Gain bitfield
(RegACCfg3[6:0])
PGA3 Gain
GD3 [V/V]
Pga3Offset bitfield
(RegACCfg4[6:0])
PGA3 Offset
GDOFF3 [V/V]
0000000
0
0000000
0
0000001
1/12 (=0.083)
0000001
+1/12 (=0.083)
...
...
...
0000110
6/12
0010000
+16/12
...
...
...
...
0001100
12/12
0100000
32/12
0010000
16/12
...
...
...
...
0111111
+63/12 (=+5.25)
0100000
32/12
1000000
0
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Table 13. PGA3 Gain and Offset Settings
Pga3Gain bitfield
(RegACCfg3[6:0])
PGA3 Gain
GD3 [V/V]
Pga3Offset bitfield
(RegACCfg4[6:0])
PGA3 Offset
GDOFF3 [V/V]
...
...
1000001
-1/12 (=-0.083)
1000000
64/12
1000010
-2/12
...
...
...
...
1111111
127/12 (=10.58)
1010000
-16/12
...
...
1100000
-32/12
...
...
1111111
-63/12 (=-5.25)
The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the voltage entering the ADC is
given by:
VIN , ADC = GD3 ⋅ VD 2 − GDoff 3 ⋅ S ⋅ VREF
[V ]
Equation 7
where GD3 and GDOFF3 are respectively the gain and offset of PGA3 (in V/V). The control words are Pga3Gain[6:0] and
Pga3Offset[6:0].
To remain within the signal compliance of the PGA stages (no saturation), the condition:
VIN , VD1 , VD 2 <
VBATT
2
Equation 8
must be verified.
To remain within the signal compliance of the ADC (no saturation), the condition:
⎛ V ⎞⎛ OSR − 1 ⎞
VIN , ADC < ⎜ REF ⎟⎜
⎟
⎝ 2 ⎠⎝ OSR ⎠
Equation 9
must be verified.
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Finally, combining Equation 5 to Equation 7 for the three PGA stages, the input voltage VIN,ADC of the ADC is related to
VIN by:
VIN , ADC = GDTOT ⋅ VIN − GDoff TOT ⋅ S ⋅ VREF
[V ]
Equation 10
where the total PGA gain is defined as:
GDTOT = GD3 ⋅ GD2 ⋅ GD1
Equation 11
and the total PGA offset is:
GDoffTOT = GDoff 3 + GD3 ⋅ GDoff 2
Equation 12
7.6.1 PGA Ranges
Figure 11 and Figure 12 illustrates the limits for the maximal conversion precision according to the common mode
voltage (VCOMMON), the ADC over-sampling frequency (fs) and PGA gains. The best linearity performances can be
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obtained only below these limits, as depicted in Figure 11 if the supply voltage (VBATT ) is below 4.2V and as depicted
in Figure 12 if the supply voltage (VBATT ) is above 4.2V.
Max gain on first active PGA
10.0
fs 62.5 or 125kHz
5.0
fs 250kHz
2.5
fs 500kHz
Vcommon
VBATT-1.8V
VBATT-1.2V VBATT-0.8V
VBATT
Figure 11. Common mode input range on PGA for VBATT below 4.2V
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Max gain First active PGA
10.0
fs = 62.5, 125kHz or 250kHz
5.0
2.5
fs frequency 500kHz
Vcommon
VBATT-2.2V
VBATT
VBATT-1.2V VBATT-0.8V
Figure 12. Common mode input range on PGA for VBATT above 4.2V
Max VCOMMON for gain 10 on first active PGA
5.5 V
5.0 V
fs 250 kHz
4.0 V
3.3 V
3.0 V
fs 62.5
or 125kHz
2.4V
2.0 V
fs 500 kHz
1.0 V
VBATT
4.2 V
2.4 V
5.5 V
Figure 13. Common mode input range on PGA vs VBATT
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7.7 Analog-to-Digital Converter (ADC)
The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three
programmable parameters. The setting of these parameters and the resulting performances are described later.
fs :
OSR :
NELCONV :
Over-sampling frequency
Over-Sampling Ratio
Number of Elementary Conversions
7.7.1 Conversion Sequence
A conversion is started each time the bit Start or the Def bit is set. As depicted in Figure 14, a complete analog-todigital conversion sequence is made of a set of NELCONV elementary incremental conversions and a final quantization
step. Each elementary conversion is made of (OSR+1) over-sampling periods Ts=1/fs, i.e.:
TELCONV = (OSR + 1) / f S [s]
Equation 13
The result is the mean of the elementary conversion results. An important feature is that the elementary conversions
are alternatively performed with the offset of the internal amplifiers contributing in one direction and the other to the
output code. Thus, converter internal offset is eliminated if at least two elementary sequences are performed (i.e. if
NELCONV >= 2). A few additional clock cycles are also required to initiate and end the conversion properly.
Init
Elementary
Conversion
Elementary
Conversion
Elementary
Conversion
Elementary
Conversion
Conversion index
Offset
1
+
2
-
NELCONV-1
+
NELCONV
-
TCONV
End
Conversion
Result
Figure 14. Analog-to-Digital Conversion Sequence
Note
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The internal bandgap reference state may be forced High or Low, or may be set
to toggle during conversion at either the same rate or half the rate of the
Elementary Conversion. This may be useful to help eliminate bandgap related
internal offset voltage and 1/fs noise.
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7.7.2 Over-Sampling Frequency (fs)
The word SetFs[1:0] (see Table 14) is used to select the over-sampling frequency fs. The over-sampling frequency is
derived from the 4MHz oscillator clock.
Table 14. Sampling frequency settings
SetFs bitfield
(RegACCfg2[7:6])
Over-Sampling Frequency fs
[Hz]
00
62.5 kHz
01
125 kHz
10
250 kHz
11
500 kHz
7.7.3 Over-Sampling Ratio (OSR)
The over-sampling ratio (OSR) defines the number of integration cycles per elementary conversion. Its value is set with
the word SetOsr[2:0] in power of 2 steps (see Table 15) given by:
OSR = 2 3+SetOsr[2:0] [−]
Equation 14
Table 15. Over-sampling ratio settings
SetOsr[2:0]
(RegACCfg[4:2])
Over-Sampling Ratio
OSR [-]
000
8
001
16
010
32
011
64
100
128
101
256
110
512
111
1024
7.7.4 Number of Elementary Conversions (Nelconv)
As mentioned previously, the whole conversion sequence is made of a set of NELCONV elementary incremental
conversions. This number is set with the word SetNelconv[1:0] in power of 2 steps (see Table 16) given by:
N ELCONV = 2 SetNelconv [1:0]
[−]
Equation 15
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Table 16. Number of elementary conversion
SetOsr[2:0]
(RegACCfg[4:2])
# of Elementary Conversion
NELCONV [-]
00
1
01
2
10
4
11
8
As already mentioned, NELCONV must be equal or greater than 2 to reduce internal amplifier offsets.
7.7.5 Resolution
The theoretical resolution of the ADC, without considering thermal noise, is given by:
n = 2 ⋅ log2 (OSR) + log2 ( N ELCONV ) [bit]
Equation 16
Resolution - n[bits]
16.0
14.0
11
10
01
00
12.0
10.0
8.0
SetNelconv[1:0]
6.0
4.0
000
001
010
011
100
101
110
111
SetOsr[2:0]
Figure 15. Resolution vs. SetOsr[2:0] and SetNelconv[2:0]
Using look-up Table 17 or the graph plotted in Figure 15, resolution can be set between 6 and 16 bits. Notice that,
because of 16-bit register use for the ADC output, practical resolution is limited to 16 bits, i.e. n = 16. Even if the
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resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and NELCONV to higher values
in order to reduce the influence of the thermal noise in the PGA .
Table 17. Resolution1 vs. SetOsr and SetNelconv settings
SetOsr
control bits
SetNelconv control bits
‘00‘
‘01‘
‘10‘
‘11’
‘000‘
6
7
8
9
‘001‘
8
9
10
11
‘010‘
10
11
12
13
‘011‘
12
13
14
15
‘100‘
14
15
16
16
‘101‘
16
16
16
16
‘110‘
16
16
16
16
‘111‘
16
16
16
16
1.
In shaded area, the resolution is truncated to 16 bits due to output register size RegACOut[15:0]
7.7.6 Conversion Time & Throughput
As explained in Figure 15, conversion time is given by:
TCONV = ( NELCONV ⋅ (OSR+ 1) + 1) / f S [s]
Equation 17
and throughput is then simply 1/TCONV. For example, consider an over-sampling ratio of 256, 2 elementary conversions,
and a sampling frequency of 500 kHz (SetOsr = "101", SetNelconv = "01" and SetFs = "00"). In this case, using Table 18,
the conversion time is 515 sampling periods, or 1.03ms. This corresponds to a throughput of 971Hz in continuous-time
mode. The plot of Figure 16 illustrates the classic trade-off between resolution and conversion time.
Table 18. Normalized conversion time (Tconv x fs) vs. SetOsr and SetNelconv settings1
SetOsr bits
OSR
‘00‘
1
‘01‘
2
‘10‘
4
‘11‘
8
10
19
37
73
‘001‘
18
35
69
137
‘010‘
34
67
133
265
‘011‘
66
131
261
521
‘000‘
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NELCONV
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Table 18. Normalized conversion time (Tconv x fs) vs. SetOsr and SetNelconv settings1
SetNelconv control bits
NELCONV
SetOsr bits
OSR
1.
‘00‘
1
‘01‘
2
‘10‘
4
‘11‘
8
‘100‘
130
259
517
1033
‘101‘
258
515
1029
2057
‘110‘
514
1027
2053
4105
‘111‘
1026
2051
4101
8201
Normalized to sampling period 1/fs
Resolution - n[bits]
16.0
14.0
12.0
10.0
11
8.0
6.0
10
01
00
4.0
10
100
1000
10000
Normalized Conversion Time – Tconv / fs [-]
Figure 16. Resolution vs. normalized1 conversion time for different SetNelconv[1:0]
1.
Normalized Conversion Time - TCONV/fs
7.7.7 Continuous-Time vs. On-Request Conversion
The ADC can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit
Continuous).
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In "continuous-time" mode, the input signal is repeatedly converted into digital. After a conversion is finished, a new
one is automatically initiated. The new value is then written in the result register, and the corresponding internal
trigger pulse is generated. This operation is sketched in Figure 17. The conversion time in this case is defined as TCONV.
Tconv
Internal trig
Output code RegACOut[15:0]
Busy
1/fs
Ready
Figure 17. ADC “Continuous-Time” Operation
In the "on-request" mode, the internal behavior of the converter is the same as in the "continuous-time" mode, but the
conversion is initiated on user request (with the Start bit). As shown in Figure 18, the conversion time is also TCONV.
Tconv
Internal trig
START Request
Output code RegACOut[15:0]
Busy
Ready
Figure 18. ADC “On-Request” Operation
7.7.8 Output Code Format
The ADC output code is a 16-bit word in two's complement format (see Table 19). For input voltages outside the range,
the output code is saturated to the closest full-scale value (i.e. 0x7FFF or 0x8000). For resolutions smaller than 16 bits,
the non-significant bits are forced to the values shown in Table 20. The output code, expressed in LSBs, corresponds to:
OUT ADC = 2 16 ⋅
V IN , ADC
V REF
⋅
OSR + 1
OSR
Equation 18
Recalling Equation 10, page 25, this can be rewritten as:
OUTADC = 216 ⋅
VIN
VREF
⎛
V
⋅ ⎜⎜ GDTOT − GDoff TOT ⋅ S ⋅ REF
VIN
⎝
⎞ OSR + 1
⎟⎟ ⋅
[ LSB ]
⎠ OSR
Equation 19
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where, from Equation 11 and Equation 12, the total PGA gain and offset are respectively:
GDTOT = GD3 ⋅ GD2 ⋅ GD1
Equation 20
and:
GDoffTOT = GDoff 3 + GD3 ⋅ GDoff 2
Equation 21
Table 19. Basic ADC Relationships (example for: VREF = 5V, OSR = 512, n = 16bits)
ADC Input Voltage
VIN,ADC
% of Full Scale (FS)
Output in LSBs
Hexadecimal Output Code
+2.49505 V
+0.5 x FS
+215-1 = 32’767
7FFF
+2.49497 V
...
+215-2 = 32’766
7FFE
...
...
...
...
+76.145 μV
...
+1
0001
0
0
0
0000
-76.145 μV
...
-1
FFFF
...
...
...
...
15
-2.49505 V
...
-2 -1 = -32’767
8001
-2.49513 V
-0.5 x FS
-215 = -32’768
8000
Table 20. Last forced LSBs in conversion output register for resolution settings smaller than 16bits1
SetOsr[2:0]
1.
SetNelconv = ‘00’
SetNelconv = ‘01’
SetNelconv = ‘10’
SetNelconv = ‘11’
‘000’
1000000000
100000000
10000000
1000000
‘001’
10000000
1000000
100000
10000
‘010’
100000
10000
1000
100
‘011’
1000
100
10
1
‘100’
10
1
-
-
‘101’
-
-
-
-
‘110’
-
-
-
-
‘111’
-
-
-
-
(n<16) (RegACOutMsb[7:0] & RegACOutLsb[7:0])
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The equivalent LSB size at the input of the PGA chain is:
LSB =
OSR
1 V REF
[V / V ]
⋅
⋅
n
2 GDTOT OSR + 1
Equation 22
Notice that the input voltage VIN,ADC of the ADC must satisfy the condition:
VIN , ADC ≤
1
OSR
⋅ (VREFP − VREFN ) ⋅
2
OSR + 1
Equation 23
to remain within the ADC input range.
7.7.9 Power Saving Modes
During low-speed operation, the bias current in the PGAs and ADC can be programmed to save power using the
control words IbAmpPga[1:0] and IbAmpAdc[1:0] (see Table 21). If the system is idle, the PGAs and ADC can even be
disabled, thus, reducing power consumption to its minimum. This can considerably improve battery lifetime.
Table 21. ADC & PGA power saving modes and maximum sampling frequency
IbAmpAdc [1:0]
IbAmpPga [1:0]
00
01
11
ADC Bias Current PGA Bias Current
1/4 x IADC
1/2 x IADC
IADC
00
01
11
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125
250
500
1/4 x IPGA
1/2 x IPGA
IPGA
Page 35
Max. fs [kHz]
125
250
500
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8 Application hints
8.1 Power Reduction
The ZoomingADC is particularly well suited for low-power applications. When very low power consumption is of
primary concern, such as in battery operated systems, several parameters can be used to reduce power consumption
as follows:
Operate the acquisition chain with a reduced supply voltage VBATT.
Disable the PGAs which are not used during analog-to-digital conversion with Enable[3:0].
Disable all PGAs and the ADC when the system is idle and no conversion is performed.
Use lower bias currents in the PGAs and the ADC using the control words IbAmpPga[1:0] and IbAmpAdc[1:0].
Reduce sampling frequency.
Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower maximum
sampling speed.
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8.2 Gain Configuration Flow
The diagram below shows the flow to set the gain of your configuration:
Set gain
Gain < 10 ?
No
Gain < 100 ?
No
Enable PGA1,2&3
Yes
Yes
Enable PGA3
Enable PGA2&3
Set PGA 1 gain
Set PGA 3 gain
Set PGA 2 gain
Set PGA 2 gain
Set PGA 3 gain
Set PGA 3 gain
GAIN =
PGA2 x PGA3
GAIN =
PGA1 x PGA2 x PGA3
GAIN = PGA3
End
Figure 19. Gain configuration flowchart
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9 I2C Interface
The I2C interface gives access to the chip registers. It complies with the I2C protocol specifications, restricted to the
slave side of the communication.
The device uses a Generic Fast-Mode (400 KHz) I2C Slave Interface in accordance with the I2C bus standard. Its
characteristics can be summarized as follows:
9.1 General Features
Slave only operation
Fast mode operation (up to 400 kHz)
Combined read and write mode support
General call reset support
7-bits default slave address 0x48. Can be changed by fuse and by pinout (D0 and D1).
The interface handles I2C communication at the transaction level. A read transaction is an external request to get the
content of system memory location and a write transaction is an external request to write the content of a system
memory location.
The default I2C slave address is 0x48, 1001000 in binary. This is the standard part I2C slave address. Other addresses
between 1000000 and 1001111 are available.
9.2 Other Slave Address Options
Slave address might be diffenciated (2 fuse-programmed bits + 2 LSBs given by 2 GPIO inputs):
Address bit 3 and bit 2 (100XXxx ) can be changed in production by fuse. Other values are available by special
request. Please contact Semtech Sales for more information. Otherwise, default value is “00”.
The last significant bits (100xxXX ) can be defined by the GPIO pin D0 and D1. This mode is not set by default at
startup, it must be activated in a register with a command. Default value is “00”.
Address bit:
6 5
4
3
2
1
0
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Set externally
(optional)
Fuse
programmed
Fixed
100 XX XX
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9.2.1 Address Set Externally
Bit:
6 5
4
3
2
1
0
100 XX 01
Slave address:
Address bit[0] set to 1
D0
D1
GPIO
Address bit[1] set to 0
Figure 20. Example of I2C address set by external resistors
The GPIO are set as ouput low at startup, so a resistor should be connected to the pad to avoid shortcut at startup.
After startup, the master I2C can send a command (0x96 in RegExtAdd[0x43]) at the default I2C address to change I2C
mode and set D0 and D1 as input address bits.
If several SX87xx devices are connected on the same bus, the master MCU must send the command to each device
simultaneousely using the default address. All SX87xx devices will receive the command at the same time. The master
MCU must ensure that the command has been received by asking each slave device at their new address.
9.3 I2C General Call Reset
The device respond to the I2C general call address (0000000) if the eighth bit is '0'. The devices acknowledge the
general call address and respond to commands in the second byte. If the second byte is 00000110 (06h), the device
reset the internal registers and enter power-down mode.
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS
S
T
O
P
REGISTER
ADDRESS
SDA
L
S
B
M
S
B
A
C
K
0x00
A
C
K
0x06
Figure 21. I2C General Call reset frame
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9.4 I2C Register Access
9.4.1 Writing a Register
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS
REGISTER
ADDRESS
S
T
O
P
REGISTER
VALUE
SDA
M
S
B
L
S
B
A
C
K
A
C
K
A
C
K
Figure 22. I2C timing diagram for writing to a register
9.4.2 Reading in a Register
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS
R
E
S
T
A
R
T
REGISTER
ADDRESS
DEVICE
ADDRESS
R
E
A
D
S
T
O
P
REGISTER
VALUE (n)
SDA
M
S
B
L
S
B
A
C
K
A
C
K
N
O
A
C
K
A
C
K
Figure 23. I2C timing diagram for reading from a register
9.4.3 Writing in Several Consecutive Registers
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS
REGISTER
ADDRESS
REGISTER
VALUE (n)
REGISTER
VALUE (n + x - 1)
S
T
O
P
REGISTER
VALUE (n + x)
SDA
M
S
B
L
S
B
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 24. I2C timing diagram for multiple writing to registers
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9.4.4 Reading from Several Consecutive Registers
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS
R
E
S
T
A
R
T
REGISTER
ADDRESS
DEVICE
ADDRESS
R
E
A
D
REGISTER
VALUE (n)
S
T
O
P
REGISTER
VALUE (n+x)
SDA
M
S
B
L
S
B
A
C
K
A
C
K
A
C
K
N
O
A
C
K
A
C
K
Figure 25. I2C timing diagram for multiple reading from a register
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10 Register Memory Map and Description
10.1 Register Map
Table 22 below describes the register/memory map that can be accessed through the I2C interface. It indicates the
register name, register address and the register contents.
Table 22. Register Map
Adress
Register
Bit
Description
RegRCen
1
RC oscillator control
RC Register
0x30
GPIO Registers
0x40
RegOut
8
D0 to D3 pads data output and direction control
0x41
RegIn
4
D0 to D3 pads input data
0x42
RegTimeout
1
Enable/Disable I2C timeout
0x43
RegExtAdd
8
Set address by external pin
ADC Registers
0x50
RegACOutLsb
8
LSB of ADC result
0x51
RegACOutMsb
8
MSB of ADC result
0x52
RegACCfg0
7
ADC conversion control
0x53
RegACCfg1
8
ADC conversion control
0x54
RegACCfg2
8
ADC conversion control
0x55
RegACCfg3
8
ADC conversion control
0x56
RegACCfg4
7
ADC conversion control
0x57
RegACCfg5
8
ADC conversion control
8
Chip operating mode register
Mode Register
0x70
RegMode
10.2 Registers Descriptions
The register descriptions are presented here in ascending order of Register Address. Some registers carry several
individual data fields of various sizes; from single-bit values (e.g. flags), upwards. Some data fields are spread across
multiple registers. After power on reset the registers will have the values indicated in the tables "Reset" column.
Please write the “Reserved” bits with their reset values.
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10.2.1 RC Register
Table 23. RegRCen[0x30]
Bit
Bit Name
Mode
Reset
Description
7:1
-
r
0000000
Reserved
0
RCEn
rw
1
Enables RC oscillator. Set 0 for low power mode.
10.2.2 GPIO Registers
Table 24. RegOut[0x40]
Bit
Bit Name
Mode
Reset
Description
7
D3Dir
rw
1
D3 pad direction.
1 : Output
0 : Input
6
D2Dir
rw
1
D2 pad direction.
1 : Output
0 : Input
5
D1Dir
rw
1
D1 pad direction.
1 : Output
0 : Input
4
D0Dir
rw
1
D0 pad direction.
1 : Output
0 : Input
3
D3Out
rw
0
D3 pad output value. Only valid when D3Dir=1
2
D2Out
rw
0
D2 pad output value. Only valid when D2Dir=1
1
D1Out
rw
0
D1 pad output value. Only valid when D1Dir=1 and VrefD1In=0
0
D0Out
rw
0
D0 pad output value. Only valid when D0Dir=1 and VrefD1Out=0
Table 25. RegIn[0x41]
Bit
Bit Name
Mode
Reset
Description
7:4
-
r
0000
Reserved
3
D3In
r
-
D3 pad value
2
D2In
r
-
D2 pad value
1
D1In
r
-
D1 pad value
0
D0In
r
-
D0 pad value
Table 26. RegTimout[0x42]
Bit
Bit Name
Mode
Reset
Description
7:6
-
rw
00
Reserved
5
Timeout
w
0
0 : Disabled
1 : Enabled
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Table 26. RegTimout[0x42]
Bit
Bit Name
Mode
Reset
Description
4:0
-
rw
00000
Reserved
Table 27. RegExtAdd[0x43]
Bit
Bit Name
Mode
Reset
Description
7:0
ExternalRd
rw
00000000
Write the 0x96 value into this register to set the two LSbits of the I2C address
by external (D0 and D1).
10.2.3 ZADC Registers
Table 28. RegACOutLsb[0x50]
Bit
Name
Mode
Reset
Description
7:0
Out[7:0]
r
00000000
LSB of the ADC result
Table 29. RegACOutMsb[0x51]
Bit
Name
Mode
Reset
Description
7:0
Out[15:8]
r
00000000
MSB of the ADC result
Table 30. RegACCfg0[0x52]
Bit
Name
Mode
Reset
Description
7
Start
rw
0
Starts an ADC conversion
6:5
SetNelconv
rw
01
Sets the number of elementary conversion to 2SetNelconv.
To compensate for offset the signal is chopped between elementary
conversion.
4:2
SetOsr
rw
010
Sets the ADC over-sampling rate of an elementary conversion to 23+SetOsr.
1
Continuous
rw
0
Sets the continuous ADC conversion mode
0
-
r
0
Reserved
Table 31. RegACCfg1[0x53]
Bit
Name
Mode
Reset
Description
7:6
IbAmpAdc
rw
11
Bias current selection for the ADC
5:4
IbAmpPga
rw
11
Bias current selection for the PGA
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Table 31. RegACCfg1[0x53]
Bit
Name
3
2
1
Enable
0
Mode
Reset
Description
rw
0
PGA3 enable
rw
0
PGA2 enable
rw
0
PGA1 enable
rw
0
ADC enable
Table 32. RegACCfg2[0x54]
Bit
Name
Mode
Reset
Description
7:6
SetFs
rw
00
ADC Sampling Frequency selection
5:4
Pga2Gain
rw
00
PGA2 gain selection
3:0
Pga2Offset
rw
0000
PGA2 offset selection
Table 33. RegACCfg3[0x55]
Bit
Name
Mode
Reset
Description
7
Pga1Gain
rw
0
PGA1 gain selection
6:0
Pga3Gain
rw
0001100
PGA3 gain selection
Table 34. RegACCfg4[0x56]
Bit
Name
Mode
Reset
Description
7
-
rw
0
Reserved
6:0
Pga3Offset
rw
0000000
PGA3 offset selection
Table 35. RegACCfg5[0x57]
Bit
Name
Mode
Reset
Description
7
Busy
r
0
ADC activity flag
6
Def
rw
0
Selects ADC and PGA default configuration, starts an ADC conversion
5:1
Amux
rw
00000
Input channel configuration selector
0
Vmux
rw
0
Reference channel selector
0 : VBATT
1 : VREF
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10.2.4 Mode Registers
Table 36. RegMode[0x70]
Bit
Name
Mode
Reset
Description
7
-
r
1
reserved
6
-
r
0
reserved
5:4
Chopper
rw
00
VREF chopping control. Note 1
11 : Chop at NELCONV/2 rate
10 : Chop at NELCONV rate
01 : Chop state=1
00 : Chop state=0
3
MultForceOn
rw
0
Force charge pump On. Takes priority. Note 2
2
MultForceOff
rw
1
Force charge pump Off. Note 2
1
VrefD0Out
rw
0
Enable VREF output on D0 pin
0
VrefD1In
rw
0
Enable external VREF on D1 pin
(1)
(2)
The chop control is to allow chopping of the internal bandgap reference. This may be useful to help eliminate bandgap related internal
offset voltage and 1/f noise. The bandgap chop state may be forced High or Low, or may be set to toggle during conversion at either the
same rate or half the rate of the Elementary Conversion. (See Conversion Sequence in the ZoomingADC description).
The internal charge pump may be forced On when VBATT supply is below 4.2V or Off when VBATT supply is above 4.2V. Enabling the charge
pump increase the current consumption. If the ADC is not being run at full rate or full accuracy then it may operate sufficiently well when
VBATT is less than 4.2V and internal charge pump forced Off.
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11 Typical Performances
Note
The graphs and tables provided following this note are statistical summary
based on limited number of samples and are provided for informational
purposes only. The performance characteristics listed herein are not tested or
guaranteed. In some graphs or tables, the data presented may be outside the
specified operating range and therefore outside the warranted range.
11.1 Input impedance
The PGAs of the ZoomingADC are a switched capacitor based blocks (see Switched Capacitor Principle section). This
means that it does not use resistors to fix gains, but capacitors and switches. This has important implications on the
nature of the input impedance of the block.
Using switched capacitors is the reason why, while a conversion is done, the input impedance on the selected channel
of the PGAs is inversely proportional to the sampling frequency fs and to stage gain as given in Equation 24.
Z in ≥
1
[Ω ]
f s ⋅ (Cg ⋅ gain + Cp )
Equation 24
The input impedance observed is the input impedance of the first PGA stage that is enabled or the input impedance of
the ADC if all three stages are disabled.
Cg multiplied by gain is the equivalent gain capacitor and Cp is the parasitic capacitor of the first enabled stage. The
values for each ZoomingADC bloc are provided in Table 37:
Table 37. Capacitor values
Acquisition Chain Stage
Gain capacitor Cg
Parasitic capacitor Cp
Units
PGA1
0.45
1.04
pF
PGA2
0.54
1.2
pF
PGA3
0.735
1.53
pF
ADC
2.4
pF
PGA1 (with a gain of 10) and PGA2 (with a gain of 10) have each a minimum input impedance of 300 kOhm at fs = 500
kHz. PGA3 (with a gain of 10) have a minimum input impedance of 250 kOhm at fs = 500 kHz. Larger input impedance
can be obtained by reducing the gain and/or by reducing the over-sampling frequency fs. Therefore, with a gain of 1
and a sampling frequency of 62.5 kHz, Zin > 10.2 MOhm for PGA1.
The input impedance on channels that are not selected is very high (>10MOhm).
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11.1.1 Switched Capacitor Principle
Basically, a switched capacitor is a way to emulate a resistor by using a capacitor. The capacitors are much easier to
realize on CMOS technologies and they show a very good matching precision.
V1
V1
V2
f
f
V2
R
Figure 26. The Switched Capacitor Principle
A resistor is characterized by the current that flows through it (positive current leaves node V1):
I=
V1 −V2
[ A]
R
Equation 25
One can verify that the mean current leaving node V1 with a capacitor switched at frequency f is:
I = (V1 − V 2) ⋅ f ⋅ C [ A]
Equation 26
Therefore as a mean value, the switched capacitor 1/(f x C) is equivalent to a resistor.
It is important to consider that this is only a mean value. If the current is not integrated (low impedance source), the
impedance is infinite during the whole time but the transition.
What does it mean for the ZoomingADC?
If the fs clock is reduced, the mean impedance is increased. By dividing the fs clock by a factor 10, the impedance is
increased by a factor 10.
One can reduce the capacitor that is switched by using an amplifier set to its minimal gain. In particular if PGA1 is used
with gain 1, its mean impedance is 10x bigger than when it is used with gain 10.
Current
integration
Sensor
impedence
V1
Sensor
Node
Capacitance
ZoomingADC (model)
f
f V2
C
Figure 27. The Switched Capacitor Principle
One can increase the effective impedance by increasing the electrical bandwidth of the sensor node so that the
switching current is absorbed through the sensor before the switching period is over. Measuring the sensor node will
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show short voltage spikes at the frequency fs, but these will not influence the measurement. Whereas if the bandwidth
of the node is lower, no spikes will arise, but a small offset can be generated by the integration of the charges
generated by the switched capacitors, this corresponds to the mean impedance effect.
Notes:
(1)
(2)
(3)
One can increase the mean input impedance of the ZoomingADC by lowering the acquisition clock fs.
One can increase the mean input impedance of the ZoomingADC by decreasing the gain of the first enabled amplifier.
One can increase the effective input impedance of the ZoomingADC by having a source with a high electrical bandwidth (sensor electrical bandwidth much higher than fs).
11.2 Frequency Response
The incremental ADC is an over-sampled converter with two main blocks: an analog modulator and a low-pass digital
filter. The main function of the digital filter is to remove the quantization noise introduced by the modulator. This filter
determines the frequency response of the transfer function between the output of the ADC and the analog input VIN.
Notice that the frequency axes are normalized to one elementary conversion period OSR / fs. The plots of Figure 28,
page 50 also show that the frequency response changes with the number of elementary conversions NELCONV
performed. In particular, notches appear for NELCONV >= 2 These notches occur at:
f
i ⋅ fs
NOTCH = -----------------------------------OSR ⋅ N ELCONV
For
i = 1, 2, … ( N ELCONV – 1 )
Equation 27
and are repeated every fs / OSR.
Information on the location of these notches is particularly useful when specific frequencies must be filtered out by the
acquisition system. This chip has no dedicated 50/60 Hz rejection filtering but some rejection can be achieved by using
Equation 27 and setting the appropriate values of OSR, fs and NELCONV.
Table 38. 50/60 Hz Line Rejection Examples
Rejection [Hz]
60
50
Revision 1.01
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fNOTCH [Hz]
fs [kHz]
OSR [-]
NELCONV [-]
61
125
1024
2
61
250
1024
4
61
500
1024
8
53
62.5
1024
8
46
62.5
1024
4
46
125
1024
8
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1.2
1
Nelconv = 1
0.8
0.6
0.4
0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
DATASHEET
Normalized Magnitude [-]
Normalized Magnitude [-]
ADVANCED COMMUNICATIONS & SENSING
4
1.2
1
Nelconv = 2
0.8
0.6
0.4
0.2
0
0
1.2
1
Nelconv = 4
0.8
0.6
0.4
0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
1
1.5
2
2.5
3
3.5
4
Normalized Frequency - f x (OSR / fs) [-]
Normalized Magnitude [-]
Normalized Magnitude [-]
Normalized Frequency - f x (OSR / fs) [-]
0.5
4
Normalized Frequency - f x (OSR / fs) [-]
1.2
1
Nelconv = 8
0.8
0.6
0.4
0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
Normalized Frequency - f x (OSR / fs) [-]
Figure 28. Frequency Response. Normalized Magnitude vs. Frequency for Different NELCONV
11.3 Linearity
11.3.1 Integral Non-Linearity
The different PGA stages have been designed to find the best compromise between the noise performance, the
integral non-linearity and the power consumption. To obtain this, the first stage has the best noise performance and
the third stage the best linearity performance. For large input signals (small PGA gains, i.e. up to about 50), the noise
added by the PGA is very small with respect to the input signal and the second and third stage of the PGA should be
used to get the best linearity. For small input signals (large gains, i.e. above 50), the noise level in the PGA is important
and the first stage of the PGA should be used.
The following figures show the Integral non linearity for different gain settings over the chip temperature range
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DATASHEET
11.3.1.1 Gain 1
VBATT=5V ; VREF=VBATT; PGAs disabled; OSR=1024 ; Nelconv=8 ; fs=250kHz; Resolution=16bits.
10
INL Gain 1 @ -40°C
8
8
6
6
4
4
2
2
INL [LSB]
INL [LSB]
10
0
-2
0
-2
-4
-4
-6
-6
-8
-8
-10
-10
-2
-1.5
-1
-0.5
0
0.5
1
1.5
INL Gain 1 @ 25°C
-2
2
-1.5
-1
-0.5
Figure 29. INL -40°C
10
8
8
6
6
4
4
2
2
INL [LSB]
INL [LSB]
INL Gain 1 @ 85°C
0
-2
-6
-6
-8
-8
-10
-10
-0.5
1.5
2
0
0.5
1
1.5
1
1.5
2
INL Gain 1 @ 125°C
0
-4
-1
1
-2
-4
-1.5
0.5
Figure 30. INL 25°C
10
-2
0
VIN [V]
VIN [V]
2
-2
-1.5
-1
-0.5
VIN [V]
0
0.5
VIN [V]
Figure 31. INL 85°C
Figure 32. INL 125°C
11.3.1.2 Gain 10
VBATT=5V ; VREF=VBATT; ADC and PGA3 enabled ; GD3=10; OSR=1024 ; Nelconv=8 ; fs=250kHz; Resolution=16bits.
10
INL Gain 10 @ -40°C
INL Gain 10 @ 25°C
8
8
6
6
4
4
2
2
INL [LSB]
INL [LSB]
10
0
-2
0
-2
-4
-4
-6
-6
-8
-8
-10
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
Figure 33. INL -40°C
January 2011
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
VIN [V]
VIN [V]
Revision 1.01
© Semtech
-10
-0.2
Figure 34. INL 25°C
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10
10
INL Gain 10 @ 125°C
8
8
6
6
4
4
2
2
INL [LSB]
INL [LSB]
INL Gain 10 @ 85°C
0
-2
0
-2
-4
-4
-6
-6
-8
-8
-10
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
-10
-0.2
0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
VIN [V]
VIN [V]
Figure 35. INL 85°C
Figure 36. INL 125°C
11.3.1.3 Gain 100
VBATT=5V ; VREF=VBATT; ADC, PGA2 and PGA3 enabled ; GD2=10; GD3=10; OSR=1024 ; Nelconv=8 ; fs=250kHz;
Resolution=16bits.
50
INL Gain 100 @ -40°C
40
40
30
30
20
20
10
10
INL [LSB]
INL [LSB]
50
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-0.02
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
-50
-0.02
0.02
INL Gain 100 @ 25°C
-0.015
-0.01
-0.005
VIN [V]
Figure 37. INL -40°C
50
INL Gain 100 @ 85°C
40
40
30
30
20
20
10
10
0
-10
-20
-30
-40
-40
-0.01
-0.005
0
0.005
0.01
0.015
0.02
VIN [V]
0.02
0.01
0.015
0.02
January 2011
INL Gain 100 @ 125°C
-50
-0.02
-0.015
-0.01
-0.005
0
0.005
VIN [V]
Figure 39. INL 85°C
Revision 1.01
© Semtech
0.015
0
-30
-0.015
0.01
-10
-20
-50
-0.02
0.005
Figure 38. INL 25°C
INL [LSB]
INL [LSB]
50
0
VIN [V]
Figure 40. INL 125°C
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11.3.1.4 Gain 1000
VBATT=5V ; VREF=VBATT; ADC, PGA3, PGA2, PGA1 enabled; GD1=10, GD2=10, GD3=10; OSR=1024 ; NELCONV=8 ;
fs=250KHz; Resolution=16bits.
200
200
INL Gain 1000 @ 25°C
150
150
100
100
50
50
INL [LSB]
INL [LSB]
INL Gain 1000 @ -40°C
0
0
-50
-50
-100
-100
-150
-150
-200
-0.002
-0.0015
-0.001
-0.0005
0
0.0005
0.001
0.0015
-200
-0.002
0.002
-0.0015
-0.001
-0.0005
Figure 41. INL -40°C
150
100
100
50
50
INL [LSB]
INL [LSB]
0.0015
0.002
0.001
0.0015
0.002
INL Gain 1000 @ 125°C
150
0
0
-50
-50
-100
-100
-150
-150
-0.001
-0.0005
0
0.0005
0.001
0.0015
0.002
VIN [V]
January 2011
-200
-0.002
-0.0015
-0.001
-0.0005
0
0.0005
VIN [V]
Figure 43. INL 85°C
Revision 1.01
© Semtech
0.001
200
INL Gain 1000 @ 85°C
-0.0015
0.0005
Figure 42. INL 25°C
200
-200
-0.002
0
VIN [V]
VIN [V]
Figure 44. INL 125°C
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11.3.2 Differential Non-Linearity
The differential non-linearity is generated by the ADC. The PGA does not add differential non-linearity. Figure 45 shows
the differential non-linearity.
Figure 45. Differential Non-Linearity of the ADC Converter
11.4 Noise
Ideally, a constant input voltage VIN should result in a constant output code. However, because of circuit noise, the
output code may vary for a fixed input voltage. Thus, a statistical analysis on the output code of 1200 conversions for a
constant input voltage was performed to derive the equivalent noise levels of PGA1, PGA2, and PGA3.
The extracted rms output noise of PGA1, 2, and 3 are given in Table 39, page 56: standard output deviation and
output rms noise voltage.
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Analog
Inputs
Reference
Inputs
VSS
VREF
AC2
AC3
AC4
AC5
AC6
AC7
VBATT
VSS
VREF
VSS
VIN
VN1
±Vin
S
VREFN,WB
DATASHEET
PGA1
VN2
VN3
VIN,ADC
±Vin
±Vin
±Vin
±Voff PGA2
±Voff PGA3
±Vref
GD2
GDOFF2
GD3
GDOFF3
ADC
VREF,ADC
gains:
offsets:
GD1
Figure 46. Simple Noise Model for PGAs and ADC
VN1, VN2, and VN3 are the output rms noise figures of Table 39, GD1, GD2, and GD3 are the PGA gains of stages 1 to 3
respectively. VREFN,WB is the wide band noise on the reference voltage.
The simple noise model of Figure 46 is used to estimate the equivalent input referred rms noise VN,IN of the acquisition
chain in the model of Figure 48, page 56. This is given by the relationship:
2
VN , IN
2
2
⎛ VN 1 ⎞ ⎛ VN 2
⎞ ⎛ VN 3
⎜⎜
⎟⎟ + ⎜⎜
⎟ +⎜
GD1 ⎠ ⎝ GD1 ⋅ GD2 ⎟⎠ ⎜⎝ GDTOT
⎝
=
⎞ ⎛ VREFN ,WB (GD2 ⋅ GDOFF 2 + GDOFF 3 ) ⎞ ⎛ 1 VREFN ,WB ⎞
⎟⎟
⎟⎟ + ⎜⎜ ⋅
⎟⎟ + ⎜⎜
GDTOT
⎠ ⎝ 2 GDTOT ⎠ V 2 rms
⎠ ⎝
(OSR ⋅ N ELCONV )
2
2
2
[
]
Equation 28
On the numerator of Equation 28 :
1 the first parenthesis is the PGA1 gain amplifier contribution to noise
2 the second parenthesis is the PGA2 gain amplifier contribution to noise
3 the third parenthesis is the PGA3 gain amplifier contribution to noise
4 the fourth parenthesis is PGA2 and PGA3 offset amplifiers contributions to noise
5 the last parenthesis is the contribution of the noise on the references of the ADC
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As shown in Equation 28, noise can be reduced by increasing OSR and NELCONV (increases the ADC averaging effect,
but reduces noise).
Table 39. PGA Noise Measurement (n = 16bits, OSR = 512, NELCONV = 2, VREF = 5V)
Parameter
Output RMS noise(uV)
PGA1
PGA2
PGA3
VN1 = 205
VN2 = 340
VN3 = 365
Figure 47 shows the distribution for the ADC alone (PGA1, 2, and 3 bypassed). Quantization noise is dominant in this
case, and, thus, the ADC thermal noise is below 16 bits.
Occurences
[% of total samples]
80
60
40
20
0
-5
-4
-3
-2
-1
0
1
2
3
4
5
Output Code Deviation From Mean Value [LSB]
Figure 47. ADC Noise (PGA1, 2 & 3 Bypassed, OSR = 512, NELCONV = 2)
Analog
Inputs
Reference
Inputs
VSS
VREF
AC2
AC3
AC4
AC5
AC6
AC7
VIN
VN,IN
VIN,ADC
±Vin
S
PGA1
±Vin
±Vin
±Vin
±Voff PGA2
±Voff PGA3
±Vref
ADC
VREF,ADC
VBATT
VSS
VREF
VSS
Figure 48. Total Input Referred Noise
As an example, consider the system where: GD2 = 10 (GD1 = 1; PGA3 bypassed), OSR = 512, NELCONV = 2, VREF = 5 V. In
this case, the noise contribution VN1 of PGA1 is dominant over that of PGA2. Using Equation 28, page 55, we get: VN,IN
= 6.4 μV (rms) at the input of the acquisition chain, or, equivalently, 0.85 LSB at the output of the ADC. Considering 0.2
V (rms) maximum signal amplitude, the signal-to-noise ratio is 90dB.
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11.5 Gain Error and Offset Error
Gain error is defined as the amount of deviation between the ideal transfer function (theoretical Equation 19, page
33) and the measured transfer function (with the offset error removed).
The actual gain of the different stages can vary depending on the fabrication tolerances of the different elements.
Although these tolerances are specified to a maximum of ±3%, they will be most of the time around ±0.5%. Moreover,
the tolerances between the different stages are not correlated and the probability to get the maximal error in the same
direction in all stages is very low. Finally, these gain errors can be calibrated by the software at the same time with the
gain errors of the sensor for instance.
Figure 49 shows gain error drift vs. temperature for different PGA gains. The curves are expressed in % of Full-Scale
Range (FSR) normalized to 25°C.
Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The offset of the ADC and
the PGA1 stage are completely suppressed if NELCONV > 1.
The measured offset drift vs. temperature curves for different PGA gains are depicted in Figure 50. The output offset
error, expressed in LSB for 16-bit setting, is normalized to 25°C. Notice that if the ADC is used alone, the output offset
error is below +/-1 LSB and has no drift.
NORMALIZED TO 25°C
Output Offset Er ror [LSB]
Gain Error [% of FSR]
0.2
0.1
0.0
-0.1
1
5
20
100
-0.2
-0.3
-0.4
-50
-25
0
25
50
75
60
40
20
0
-20
-40
-25
0
25
50
75
100
Temperature [°C]
Figure 49. Gain Error vs. Temperature for Different Gains
January 2011
1
5
20
100
80
-50
100
Temperature [°C]
Revision 1.01
© Semtech
NORMALIZED TO 25°C
100
Page 57
Figure 50. Offset Error vs. Temperature for Different Gains
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11.6 Power Consumption
Figure 51 plots the variation of current consumption with supply voltage VBATT, as well as the distribution between the
3 PGA stages and the ADC (see Table 40, page 60). The Charge Pump is forced ON for VBATT < 4.2V and forced OFF for
VBATT > 4.2V.
1'100
ADC
ADC+PGA1
1'000
ADC+PGA12
900
ADC+PGA123
IDD[uA]
800
700
600
500
400
300
200
2
2.5
3
3.5
4
4.5
5
5.5
VBATT [V]
Figure 51. Current Consumption vs. Supply Voltage and PGAs
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As shown in Figure 52, if lower sampling frequency is used, the current consumption can be lowered by reducing the
bias currents of the PGAs and the ADC with registers IbAmpPga and IbAmpAdc. (In Figure 52, IbAmpPga/Adc = '11', '10',
'00' for fs = 500, 250, 62.5 kHz respectively. The Charge Pump is forced ON for VBATT < 4.2V and forced OFF for VBATT >
4.2V.
1'100
62.5Khz, Ibias = 0.25
125Khz, Ibias = 0.25
1'000
250Khz, Ibias = 0.5
900
500Khz, Ibias = 1
IDD [uA]
800
700
600
500
400
300
200
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VBATT [V]
Figure 52. Current Consumption vs Temperature and ADC Sampling Frequency
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Current consumption vs. temperature is depicted in Figure 53, showing the increase between -40 and +125°C.
1300
Vbatt = 2.4v
1200
Vbatt = 3.5v
Vbatt = 5.5v
IDD [uA]
1100
1000
900
800
700
600
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 53. Current Consumption vs Temperature and Supply Voltage
Table 40. Typical Current Distribution in Acquisition Chain (n = 16 bits, fs = 250kHz)
Supply
ADC
PGA1
PGA2
PGA3
Total
VBATT = 2.4V
207
70
51
78
406
VBATT = 3.5V
282
82
61
91
516
VBATT = 5.5V
338
103
67
98
606
Revision 1.01
© Semtech
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Unit
uA
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DATASHEET
FAMILY OVERVIEW
This chapter gives an overview of similar devices based on the ZoomingADC but with different features or packages.
Each part is described in it’s own datasheet.
12 Comparizon table
Table 41. Family comparizon table
Part number
SX8723C
SX8724C
SX8725C
SX8723S
SX8724S
SX8725S
Package
MLPD-W-12 4x4
MLPQ-16 4x4
MLPD-W-12 4x4
MLPQ-16 4x4
MLPQ-16 4x4
MLPQ-16 4x4
Protocol
I2C
I2C
I2C
SPI
SPI
SPI
D0
I2C addr, Digital
IO or Vref OUT
I2C addr, Digital
IO or Vref OUT
I2C add, Digital IO Digital IO or Vref
or Vref OUT
OUT
Digital IO or Vref
OUT
Digital IO or Vref
OUT
D1
I2C addr, Digital
IO or Vref IN
I2C addr, Digital
IO or Vref IN
I2C addr, Digital
IO or Vref IN
Digital IO or Vref
OUT.
Digital IO or Vref
IN
Digital IO or Vref
IN
D2
N.A.
Digital IO
N.A.
N.A.
N.A.
N.A.
D3
N.A.
Digital IO
N.A.
N.A.
N.A.
N.A.
2
3
1
2
3
1
GPIO
Differential input
channels
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13 Comparizon by package pinout
AC2
10
VPUMP
5
N.C.
3
8 SDA
AC4
4
5
7 D0
VPUMP
SCL
SDA
AC2
VPUMP
SCLK
SDI
7
8
11
D2
AC6
2
10
D3
AC7
3
9
D1
AC4
4
5
NC
1
12
AC3
NC
2
11
AC2
AC3
1
VBATT
3
10
VPUMP
N.C.
2
VSS
4
READY
5
SX8725C
(Top view)
D1 6
Revision 1.01
© Semtech
6
7
11
SDO/RDY
10
CS
9
D1
12
D0
11
SDO/RDY
10
CS
9
D1
12
D0
11
SDO/RDY
8
16
15
14
13
SX8725S
(Top view)
9 SCL
N.C.
3
10
CS
8 SDA
N.C.
4
9
D1
7 D0
January 2011
SX8724S
(Top view)
SDI
6
1
SCLK
5
AC3
VPUMP
SX8724C
(Top view)
D0
Page 62
5
6
VBATT
4
13
AC5
AC4
14
AC2
3
15
N.C.
AC7
16
READY
2
13
VSS
AC6
14
12
D0
8
15
VBATT
1
7
16
AC5
AC3
6
AC2
AC5
D1 6
9 SCL
SX8723S
(Top view)
12
READY
READY
2
7
8
READY
4
N.C.
13
VSS
VSS
SX8723C
(Top view)
14
VSS
3
1
15
VBATT
VBATT
AC3
SDI
11
16
READY
AC5 2
SCLK
AC3
VSS
12
VBATT
AC4 1
VPUMP
SPI versions
AC2
I2C versions
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DATASHEET
MECHANICAL
14 PCB Layout Considerations
PCB layout considerations to be taken when using the SX8724C are relatively simple to get the highest performances
out of the ZoomingADC. The most important to achieve good performances out the ZoomingADC is to have a good
voltage reference. The SX8724C has already an internal reference that is good enough to get the best performances
with a minimal amount of external components, but, in case an external reference is needed this one must be as clean
as possible in order to get the desired performance. Separating the digital from the analog lines will be also a good
choice to reduce the noise induced by the digital lines. It is also advised to have separated ground planes for digital
and analog signals with the shortest return path, as well as making the power supply lines as wider as possible and to
have good decoupling capacitors.
15 How to Evaluate
For evaluation purposes SX8724CEVK evaluation kit can be ordered. This kit connects to any PC using a USB port. The
"SX87xx Evaluation Tools" software gives the user the ability to control the SX8724C registers as well as getting the raw
data from the ZoomingADC and displaying it on the "Graphical User interface". For more information please look at
SEMTECH web site (http://www.semtech.com).
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16 Package Outline Drawing: MLPQ-W16-4x4-EP1
A
D
DIMENSIONS
MILLIMETERS
DIM
MIN NOM MAX
B
PIN 1
INDICATOR
(LASER MARK)
E
A2
A
SEATING
PLANE
aaa C
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
0.80
0.70
0.05
0.00
(0.20)
0.25 0.30 0.35
3.90 4.00 4.10
2.55 2.70 2.80
3.90 4.00 4.10
2.55 2.70 2.80
0.65 BSC
0.30 0.40 0.50
16
0.08
0.10
C
A1
D1
LxN
e/2
E/2
E1
2
1
N
e
bxN
D/2
bbb
C A B
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Figure 54. Package Outline Drawing
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17 Land Pattern Drawing: 4x4MLPQ-W16-EP1
K
DIM
(C)
G
H
Z
Y
X
C
G
H
K
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.156)
.122
.106
.106
.026
.016
.033
.189
(3.95)
3.10
2.70
2.70
0.65
0.40
0.85
4.80
P
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
4. SQUARE PACKAGE - DIMENSIONS APPLY IN BOTH " X " AND " Y " DIRECTIONS.
Figure 55. Land Pattern Drawing
Revision 1.01
© Semtech
January 2011
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SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
18 Tape and Reel Specification
MLP/QFN (0.70mm - 1.00mm package thickness)
Single Sprocket holes
Tolerances for Ao & Bo are +/- 0.20mm
Tolerances for Ko is +/- 0.10mm
Tolerance for Pocket Pitch is +/- 0.10mm
Tolerance for Tape width is +/-0.30mm
Trailer and Leader Length are minimum required length
Package Orientation and Feed Direction
MLP (square)
MLP (rectangular)
Direction of Feed
Direction of Feed
Figure 56. Direction of Feed
Figure 57. User direction of feed
Table 42. Tape and reel specifications
Pkg size
4x4
Revision 1.01
© Semtech
carrier tape (mm)
Tape
Width
(W)
12
Reel
Pocket
Pitch (P)
Ao
Bo
Ko
Reel Size
(in)
8
4.35
4.35
1.10
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January 2011
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Reel
Width
(mm)
12.4
Trailer
Length (mm)
400
Leader
Length
(mm)
400
QTY per
Reel
1000/3000
www.semtech.com/products/
SX8724C
ZoomingADC for sensing data acquisition
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
© Semtech 2010
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Contact information
Semtech Corporation Advanced Communications & Sensing Products
E-mail: [email protected] or [email protected]
Internet: http://www.semtech.com
USA
200 Flynn Road, Camarillo, CA 93012-8790.
Tel: +1 805 498 2111 Fax: +1 805 498 3804
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Tel: +44 (0)1794 527 600 Fax: +44 (0)1794 527 601
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Revision 1.01
© Semtech
January 2011
Page 67
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