YMF724F DS-1 OVERVIEW YMF724F (DS-1) is a high performance audio controller for the PCI Bus. DS-1 consists of two separated functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine. The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio provides 64-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware accelerator, Downloadable Sound (DLS) and DirectMusic accelerator. Legacy Audio block supports FM Synthesizer, Sound Blaster Pro, MPU401 UART mode and Joystick function in order to provide hardware compatibility for numerous PC games on real DOS without any software driver. To achieve legacy DMAC compatibility on the PCI, DS-1 supports both PC/PCI and Distributed DMA protocols. DS-1 also supports Serialized IRQ for legacy IRQ compatibility. DS-1 supports the connection to AC’97 which provides high quality DAC, ADC and analog mixing. In addition, it supports consumer IEC958, Audio Digital Interface (SPDIF) output, for high-quality, external audio amplification. FEATURES • PCI 2.1 Compliant • PC’97/PC’98 specification Compliant • PCI Bus Power Management rev. 1.0 Compliant (Support D0, D2 and D3 state) • PCI Bus Master for PCI Audio True Full Duplex Playback and Capture with different Sampling Rate Maximum 64-voice XG capital Wavetable Synthesizer including GM compatibility DirectSound Hardware Acceleration DirectMusic Hardware Acceleration Downloadable Sound (DLS) level-1 • Legacy Audio compatibility FM Synthesizer Hardware Sound Blaster Pro compatibility MPU401 UART mode MIDI interface Joystick • Supports PC/PCI and Distributed DMA for legacy DMAC (8237) emulation • Supports Serialized IRQ • Supports YAMAHA AC-3 device (YMF727 : AC3F2) interface to enable AC-3 decode • Supports Consumer IEC958 Output (SPDIF) port • Supports AC’97 Interface (AC-Link) • Hardware Volume Control • EEPROM Interface • Single Crystal operation (24.576MHz) • 5V Power supply for I/O. 3.3V Power supply for Internal core logic • 144-pin LQFP (YMF724F-V) YAMAHA CORPORATION YMF724F CATALOG CATALOG No.:LSI-4MF724F20 September 21, 1998 January 14, 1999 YMF724F Logos GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 Compliant. XG logo is a trademark of YAMAHA Corporation. SONDIUS-XG logo is a trademark that Stanford University in the United States and YAMAHA Corporation hold jointly. Sensaura logo is a trademark of Central Research Laboratories Limited. 1. GM system level 1 GM system level 1 is a world standard format about MIDI synthesizer which provides voice arrangements and MIDI functions. 2. XG XG is a format about MIDI synthesizer that is proposed by YAMAHA, and keeps the upper compatibility of GM system level 1. The good points are the voice arrangements kept extensively, a large number of the voices, modification of the voices, 3 kinds of effects, and so on. 3. SONDIUS-XG Products bearing the SONDIUS-XG logo are licensed under patents of Stanford University and YAMAHA Corporation as listed on <http://www.sondius-xg.com>. The SONDIUS-XG produces acoustic sound outputs by running a virtual simulation of the actual acoustic instrument operation. Therefore, it provides much more real-world acoustic sound outputs fundamentally different from the Wavetable sound generator that simply processes the recorded acoustic sound sources only. The SONDIUS-XG adds the technology of virtual acoustic sound to the XG format. 4. Sensaura Sensaura is a technology which provides 3D positional audio and moving effect by HRTF (Head Related Transfer Function) with 2 speakers or headphone. This feature makes it possible to enjoy invariable and unchangeable sound feelings in all-positional area covering as wide as 360 degrees. January 14, 1999 -2- YMF724F PIN CONFIGURATION 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GREF GP3 GP2 GP1 GP0 ROMDI/TEST2# TEST1# TEST0# NC LVSS LOOPF1 LOOPF0 LVDD ROMCS TEST4# VDD5 XO24 XI24 VSS VSS VDD3 DIT TEST7# TEST6# TEST5# CMCLK CSDO CBCLK CSDI CSYNC CRST# TEST3# NC NC NC ASDI YMF724F-V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 XRST# ACS# ACDO ACDI ASCLK ASDO ABCLK ALRCK VSS VSS VDD3 VDD5 PVDD NC PCREQ# PCGNT# SERIRQ# AD0 AD1 PVSS AD2 AD3 AD4 PVSS AD5 AD6 AD7 PVSS PVDD CBE0# AD8 AD9 PVSS AD10 AD11 AD12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 CBE3# PVDD PVSS IDSEL AD23 AD22 AD21 PVSS AD20 AD19 PVSS AD18 AD17 AD16 PVDD PVSS VSS VDD3 CBE2# FRAME# IRDY# TRDY# PVSS DEVSEL# STOP# PERR# SERR# PVSS PAR CBE1# AD15 PVSS PVDD AD14 AD13 PVSS GP4 GP5 GP6 GP7 RXD TXD ROMDO/VOLDW# ROMSK/VOLUP# VDD5 VDD3 VSS VSS IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 INTA# VSS RST# VDD5 PVSS PCICLK PVDD GNT# REQ# AD31 AD30 AD29 PVSS AD28 AD27 AD26 PVSS AD25 AD24 144 Pin LQFP Top View January 14, 1999 -3- YMF724F PIN DESCRIPTION 1. PCI Bus Interface (53-pin) name I/O Type Size function PCICLK I P PCI Clock RST# I P Reset AD[31:0] IO Ptr Address / Data C/BE[3:0]# IO Ptr Command / Byte Enable PAR IO Ptr Parity FRAME# IO Pstr Frame IRDY# IO Pstr Initiator Ready TRDY# IO Pstr Target Ready STOP# IO Pstr Stop IDSEL I P DEVSEL# IO Pstr Device Select REQA# O P PCI Request GNTA# I P PCI Grant PCREQ# O Ptr PC/PCI Request PCGNT# I Ptr PC/PCI Grant PERR# IO Pstr Parity Error SERR# O Pod System Error INTA# O Pod Interrupt signal output for PCI bus SERIRQ# IO Ptr Serialized IRQ. ID Select 2. AC’97 Interface (6-pin) Name I/O Type Size CRST# O T 6mA CMCLK O C - function Reset signal for AC’97 Master Clock of AC link (24.576MHz) and AC3F2 CBCLK I T - AC-link: Bit Clock for AC’97 audio data CSDO O T 6mA AC-link: AC’97 Serial audio output data CSDI I T - AC-link: AC’97 Serial audio input data CSYNC O T 6mA AC-link: Synchronized signal January 14, 1999 -4- YMF724F 3. YMF727(AC3F2) Interface (9-pin) name I/O type size function XRST# O C 2mA Reset for local device ACS# O T 3mA Chip select for AC3F2 ASCLK O T 6mA Clock for Serial control data transfer of AC3F2 ACDO O T 3mA Serial control data output of AC3F2 ACDI I Tup - Serial control data input of AC3F2 ALRCK O T 3mA L/R clock for Serial audio data of AC3F2 ABCLK O T 6mA Bit clock for Serial audio data of AC3F2 ASDO O T 3mA Serial audio data output to AC3F2 ASDI I Tup - I/O type Size O T 3mA Mixed Serial audio data input of AC3F2 4. SPDIF Interface (1-pin) name DIT function Digital audio interface output (48kHz) 5. Legacy Device Interface (16-pin) name IRQ5 I/O type Size O Ttr 12mA function Interrupt5 of Legacy Audio It is directly connected to the interrupt signal of System I/O chip. IRQ7 O Ttr 12mA Interrupt7 of Legacy Audio IRQ9 O Ttr 12mA Interrupt9 of Legacy Audio IRQ10 O Ttr 12mA Interrupt10 of Legacy Audio IRQ11 O Ttr 12mA Interrupt11 of Legacy Audio. GP[3:0] I A - Game Port GP[7:4] I Tup - Game Port GREF I A - Reference for Game Port RXD I Tup - MIDI Data Receive TXD O T 3mA MIDI Data Transfer January 14, 1999 -5- YMF724F 6. Miscellaneous (15-pin) name I/O type Size ROMCS O T 3mA ROMSK / VOLUP# IO Tup 3mA ROMDO / VOLDW# IO Tup 3mA ROMDI / TEST2# I Tup - XI24 I C - 24.576 MHz Crystal XO24 O C 2mA 24.576 MHz Crystal TEST[7:4,1:0]# I Tup - IO Tup 3mA - - - TEST3# LOOPF[1:0] function Chip select for external EEPROM Serial clock for external EEPROM or Hardware Volume (Up) Serial data output for external EEPROM or Hardware Volume (Down) Serial data input for external EEPROM or Test pin (Do not connect externally when EEPROM is not.) Test pins (Do not connect externally) Test pin (Connect to ground) Capacitor of PLL Note) Hardware volume and EEPROM interface can not be used at the same time. When both hardware volume and EEPROM are not used, do not connect these pins externally. 7. Power Supply (39-pin) name I/O type Size function PVDD[5:0] - - - Power supply for PCI Bus Interface (+5.0) PVSS[14:0] - - - Ground for PCI Bus Interface LVDD - - - Power supply for PLL Filter (+3.3) LVSS - - - Ground for PLL Filter VDD3[3:0] - - - Power supply (+3.3V) VDD5[3:0] - - - Power supply (+5.0V) VSS[7:0] - - - Ground TYPE T : TTL A : Analog Ptr : Tri-State PCI Ttr : Tri-State TTL C : CMOS Pstr : Sustained Tri-Sate PCI Tup : Pull up (Max. 300kohm) TTL P : PCI Pod : Open Drain PCI January 14, 1999 -6- YMF724F BLOCK DIAGRAM PC-PCI / D-DMA / S-IRQ Legacy Audio SB Pro FM MPU401 Joystick Rate Converter / Mixer AC'97 Interface SPDIF (output) PCI Bus Interface BUS Master DMA Controller PCI Audio XG Synthesizer Direct Sound Acc. Wave In/Out AC3F2 Interface Memory January 14, 1999 -7- -8- Joystick Vjoyd.vxd Msjstck.drv FM SB Pro I/O Traps DOS VM I/O Traps MPU401 MidiOut Device WaveIn Device WaveOut Device DLS Appllication XG/DLS Engine DRV for PCI Audio MidiOut Device Win16API PCI Audio DS-1 Slot Manager (Up to 64-sound) YMF724F(DS-1) VxD for Legacy DRV for Legacy MidiIn Device MMSystem VxD for PCI Audio Soft Effect DirectSound HAL Win32API AC-3 Application DirectSound VxD DirectX Application YMF724F SYSTEM DIAGRAM January 14, 1999 YMF724F FUNCTION OVERVIEW 1. PCI INTERFACE DS-1 supports the PCI bus interface and complies to PCI revision 2.1. 1-1. PCI Bus Command DS-1 supports the following PCI Bus commands. 1-1-1. Target Device Mode C/BE[3:0]# Command 0 0 0 0 Interrupt Acknowledge (not support) 0 0 0 1 Special Cycle (not support) 0 0 1 0 I/O Read 0 0 1 1 I/O Write 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 Memory Read 0 1 1 1 Memory Write 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 Configuration Read 1 0 1 1 Configuration Write 1 1 0 0 Memory Read Multiple (not support) 1 1 0 1 Dual Address Cycle (not support) 1 1 1 0 Memory Read Line (not support) 1 1 1 1 Memory Write and Invalidate (not support) DS-1 does not assert DEVSEL# when accessed with commands that are indicated as (not supported) or reserved. 1-1-2. Master Device Mode C/BE[3:0]# Command 0 1 1 0 Memory Read 0 1 1 1 Memory Write ## When DS-1 becomes a Master Device, it generates only memory write and read cycle commands. January 14, 1999 -9- YMF724F 1-2. PCI Configuration Register In addition to the Configuration Register defined by PCI Revision 2.1, DS-1 provides proprietary PCI Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. The following shows the overview of the PCI Configuration Register. Offset b[31..24] b[23..16] b[15..8] b[7..0] 00-03h Device ID Vendor ID 04-07h Status Command 08-0Bh Base Class Code Sub Class Code Programming IF Revision ID 0C-0Fh Reserved Header Type Latency Timer Reserved 10-13h PCI Audio Memory Base Address 14-2Bh Reserved 2C-2Fh Subsystem ID Subsystem Vendor ID 30-33h Reserved 34-37h Reserved 38-3Bh 3C-3Fh Cap Pointer Reserved Maximum Latency Minimum Grant Interrupt Pin Interrupt Line 40-43h Extended Legacy Audio Control Legacy Audio Control 44-47h Subsystem ID Write Subsystem Vendor ID Write 48-4Bh DS-1 Power Control DS-1 Control 4C-4Fh Reserved D-DMA Slave Configuration 50-53h Power Management Capabilities 54-57h Reserved Power Management Control / Status 58-5Bh Reserved ACPI Mode 5C-FFh Reserved Next Item Pointer Capability ID Reserved registers are hardwired to “0”. All data written to these registers are discarded. The values read from these registers are all zero. DS-1 can be accessed by using any bus width, 8-bit, 16-bit or 32-bit. January 14, 1999 -10- YMF724F 00 - 01h: Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Vendor ID b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.1. This register is hardwired to 1073h. 02 - 03h: Device ID Read Only Default: 000Dh Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Device ID b[15:0] ........Device ID This register contains the Device ID of DS-1. This register is hardwired to 000Dh. 04 - 05h: Command Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - SER - PER - - - BME MS - b1................MS: Memory Space This bit enables DS-1 to response to Memory Space Access. “0”: DS-1 ignores Memory Space Access. (default) “1”: DS-1 responds to Memory Space Access. b2................BME: Bus Master Enable This bit enables DS-1 to act as a master device on the PCI bus. “0”: Do not set DS-1 to be the master device. (default) “1”: Set DS-1 to be the master device. b6................PER: Parity Error Response This bit enables DS-1 responses to Parity Error. “0”: DS-1 ignores all parity errors. “1”: DS-1 performs error operation when DS-1 detects a parity error. January 14, 1999 -11- YMF724F b8................SER: SERR# Enable This bit enables DS-1 to drive SERR#. “0”: Do not drive SERR#. (default) “1”: Drives SERR# when DS-1 detects an Address Parity Error on normal target cycle or a Data Parity Error on special cycle. 06 - 07h: Status Read / Write Clear Default: 0210h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 DPE SSE RMA RTA STA b10 b9 DEVT b4................CAP: Capability b8 b7 b6 b5 b4 b3 b2 b1 b0 DPD - - - CAP - - - - (Read Only) This bit indicates that DS-1 supports the capability register. This bit is read only. When 58-59h : ACPI Mode register, ACPI bit is “0”, the bit is “1”. When ACPI bit is “1”, the bit is “0”. b8................DPD: Data Parity Error Detected This bit indicates that DS-1 detects a Data Parity Error during a PCI master cycle. b[10:9] ........DEVT: DEVSEL Timing This bit indicates that the decoding speed of DS-1 is Medium. b11..............STA: Signaled Target Abort This bit indicates that DS-1 terminates a transaction with Target Abort during a target cycle. b12..............RTA: Received Target Abort This bit indicates that a transaction is terminated with Target Abort while DS-1 is in the master memory cycle. b13..............RMA: Received Master Abort This bit indicates that a transaction is terminated with Master Abort while DS-1 is in the master memory cycle. b14..............SSE: Signaled System Error This bit indicates that DS-1 asserts SERR#. b15..............DPE: Detected Parity Error This bit indicates that DS-1 detects Address Parity Error or Data Parity Error during a transaction. January 14, 1999 -12- YMF724F 08h: Revision ID Read Only Default: 03h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Revision ID b[7:0] ..........Revision ID This register contains the revision number of DS-1. This register is hardwired to 03h. 09h: Programming Interface Read Only Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Programming Interface b[7:0] ..........Programming Interface This register indicates the programming interface of DS-1. This register is hardwired to 00h. 0Ah: Sub-class Code Read Only Default: 01h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Sub-class Code b[7:0] ..........Sub-class Code This register indicates the sub-class of DS-1. This register is hardwired to 01h. DS-1 belongs to the Audio Sub-class. 0Bh: Base Class Code Read Only Default: 04h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Base Class Code b[7:0] ..........Base Class Code This register indicates the base class of DS-1. This register is hardwired to 04h. DS-1 belongs to the Multimedia Base Class. January 14, 1999 -13- YMF724F 0Dh: Latency Timer Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Latency Timer b[7:0] ..........Latency Timer When DS-1 becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer. 0Eh: Header Type Read Only Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Header Type b[7:0] ..........Header Type This register indicates the device type of DS-1. This is hardwired to 00h. 10 - 13h: PCI Audio Memory Base Address Read / Write Default: 00000000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 MBA - - - - - - - - - - - - - - - b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 MBA (higher) b[31:15] ......MBA: Memory Base Address This register indicates the physical Memory Base address of the PCI Audio registers in DS-1. address can be located anywhere in the 32-bit address space. The base Data in the DS-1 register is not prefetchable. DS-1 needs 32768-bytes of memory address space. January 14, 1999 -14- YMF724F 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem Vendor ID b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. To write the IHV’s Vendor ID, use 44-45h (Subsystem Vendor ID Write Register). IHVs must change this ID to their Vendor ID in the BIOS POST routine. In case of the system such as Sound Card which BIOS can not control, this ID can be changed by connecting EEPROM externally. Then, Subsystem Vendor ID Write Register is invalid. In case EEPROM is not externally, the default value is the YAMAHA's Vendor ID, 1073h. 2E-2Fh: Subsystem ID Read Only Default: 000Dh Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 Subsystem ID b[15:0] ........Subsystem ID This register contains the Subsystem ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. To write the IHV's Device ID, use 46-47h (Subsystem ID Write Register). IHVs must change this ID to their ID in the BIOS POST routine. In case of the system such as Sound Card which BIOS can not control, this ID can be changed by connecting EEPROM externally. Then, Subsystem ID Write Register is invalid. In case EEPROM is not externally, the default value is the YAMAHA's Device ID, 000Dh. 34h: Capability Register Pointer Read Only Default: 50h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Capability Register Pointer b[7:0] ..........Capability Register Pointer This register indicates the offset address of the Capabilities register in the PCI Configuration register when 58-59h: ACPI Mode register, ACPI bit is “0”. registers as the capabilities. DS-1 provides PCI Bus Power Management The Power Management registers are mapped to 50h - 57h in the PCI Configuration register, and this register indicates “50h”. When ACPI bit is “1”, this register indicates “00h”. January 14, 1999 -15- b0 YMF724F 3Ch: Interrupt Line Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Line b[7:0] ..........Interrupt Line This register indicates the interrupt channel that INTA# is assigned to. 3Dh: Interrupt Pin Read Only Default: 01h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Interrupt Pin b[7:0] ..........Interrupt Pin DS-1 supports INTA# only. This register is hardwired to 01h. 3Eh: Minimum Grant Read Only Default: 05h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Minimum Grant b[7:0] ..........Minimum Grant This register indicates the length of the burst period required by DS-1. This register is hardwired to 05h. 3Fh: Maximum Latency Read Only Default: 19h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Maximum Latency b[7:0] ..........Maximum Latency This register indicates how often DS-1 generates the Bus Master Request. This register is hardwired to 19h. January 14, 1999 -16- YMF724F 40 - 41h: Legacy Audio Control Read / Write Default: 907Fh Access Bus Width: 8, 16, 32-bit b15 b14 LAD SIEN b13 b12 b11 b10 MPUIRQ b9 b8 b7 SBIRQ b6 SDMA b5 b4 I/O MIEN b3 b2 b1 b0................SBEN: Sound Blaster Enable This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits, when LAD is set to “0”. The FM Synthesizer registers can be accessed via SB I/O space, while the SB block is enabled, even if FMEN is set to “0”. “0”: Disable the mapping of the SB block to the I/O space “1”: Enable the mapping of the SB block to the I/O space (default) b1................FMEN: FM Synthesizer Enable This bit enables the mapping of the FM Synthesizer block in the I/O space specified by the FMIO bits, when LAD is set to “0”. FM Synthesizer registers can be accessed via SB I/O space, while the SB block is enabled, even if FMEN is set to “0”. “0”: Disable the mapping of the FM Synthesizer block to the FMIO space “1”: Enable the mapping of the FM Synthesizer block to the FMIO space (default) After setting FMEN to “1”, about 100 msec is necessary before accessing these I/O space. b2................GPEN: Gameport Enable This bit enables the mapping of the Joystick block in the I/O space specified by the JSIO bits, when LAD is set to “0”. “0”: Disable the mapping of the Joystick block “1”: Enable the mapping of the Joystick block (default) b3................MEN: MPU401 Enable This bit enables the mapping of the MPU401 block in the I/O space specified by the MPUIO bits, when LAD is set to “0”. “0”: Disable the mapping of the MPU401 block “1”: Enable the mapping of the MPU401 block (default) b4................MIEN: MPU401 IRQ Enable This bit enables the interrupt service of MPU401, when LAD is set to “0” and MEN is set to “1”. MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin. “0”: The MPU401 block can not use the interrupt service. “1”: The MPU401 block can use interrupt signals determined by the MPUIRQ bits. (default) b5................I/O: I/O Address Aliasing Control This bit selects the number of bits to decode for the I/O address of each block. “0”: 16-bit address decode “1”: 10-bit address decode (default) January 14, 1999 -17- b0 MEN GPEN FMEN SBEN YMF724F b[7:6] ..........SDMA: Sound Blaster DMA-8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block. “0”: DMA ch0 “1”: DMA ch1 “2”: reserved “3”: DMA ch3 (default) b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block. “0”: IRQ5 “1”: IRQ7 “2”: IRQ9 “3”: IRQ10 “4”: IRQ11 “5” - “7”: reserved. (default) b[13:11] ......MPUIRQ: MPU401 IRQ Channel Select When MIEN is set to “1”, these bits select the interrupt channel for the MPU401 block. “0”: IRQ5 “1”: IRQ7 “2”: IRQ9 “3”: IRQ10 “4”: IRQ11 “5” - “7”: reserved (default) Same interrupt channels can be assigned to SBIRQ and MPUIRQ. b14..............SIEN: Serialized IRQ enable DS-1 supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and Serialized IRQ. The interrupt protocol is selected with IMOD and SIEN as follows. The interrupt channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ,. Only one protocol can be used at once. SIEN IMOD Interrupt protocol 0 0 Legacy interrupt (IRQs) 0 1 PCI interrupt (INTA#) 1 * Serialized IRQ (default) b15..............LAD: Legacy Audio Disable This bit disables the Legacy Audio block. “0”: Enables the Legacy Audio block “1”: Disables the Legacy Audio block (default) When this bit is set to “1”, DS-1 does not respond to the I/O Target transaction for legacy I/O address on the PCI bus. January 14, 1999 -18- YMF724F 42 - 43h: Extended Legacy Audio Control Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 IMOD b14 b13 SBVER b12 b11 SMOD b10 b9 b8 - - MAIM b7 b6 JSIO b5 b4 b3 MPUIO b2 SBIO b1 FMIO b[1:0] ..........FMIO: FM I/O Address allocation These bits determine the base I/O address for the of the FM Synthesizer block (FMBase). FM Synthesizer block uses 4 bytes in the I/O address space. “0”: 388h “1”: 398h “2”: 3A0h “3”: 3A8h (default) b[3:2] ..........SBIO: SB I/O Address allocation These bits determine the base I/O address for the Sound Blaster Pro block (SBBase). This block uses 16 bytes in the I/O address space. “0”: 220h “1”: 240h “2”: 260h “3”: 280h (default) b[5:4] ..........MPUIO: MPU I/O Address allocation These bits determine the base I/O address for the MPU401 block (MPUBase). This block uses 2 bytes in the I/O address space. “0”: 330h “1”: 300h “2”: 332h “3”: 334h (default) b[7:6] ..........JSIO: Joystick I/O Address allocation These bits determine the base I/O address for the Joystick block (JSBase). This block uses 1 byte in the I/O address space. “0”: 201h “1”: 202h “2”: 204h “3”: 205h (default) b8................MAIM: MPU401 Acknowledge Interrupt Mask This bit determine whether interrupt is asserted when the acknowledge, which is occurred by changing MPU401 mode form default to UART, is returned. “0”: Interrupt is asserted when the acknowledge is returned. (default) “1”: Interrupt is masked when the acknowledge is returned. January 14, 1999 -19- b0 YMF724F b[12:11] ......SMOD: SB DMA mode These bits determine the protocol to achieve the DMAC(8237) function on the PCI bus. “0”: PC/PCI (default) “1”: reserved “2”: Distributed DMA “3” reserved b[14:13] ......SBVER: SB Version Select These bits set the version of the SB Pro DSP. The value set in these bits is returned by sending the E1h DSP command. “0”: ver 3.01 “1”: ver 2.01 “2”: ver 1.05 “3”: reserved (default) b15..............IMOD: Legacy IRQ mode DS-1 supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and Serialized IRQ. SIEN The interrupt protocol is selected with IMOD and SIEN as follows. IMOD Interrupt protocol 0 0 Legacy interrupt (IRQs) 0 1 PCI interrupt (INTA#) 1 * Serialized IRQ (default) 44-45h: Subsystem Vendor ID Write Register Read / Write Default: 1073h Access Bus Width: 16-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 Subsystem Vendor ID Write b[15:0] ........Subsystem Vendor ID Write Register This register sets the Subsystem Vendor ID that is read from 2C-2Dh (Subsystem Vendor ID register). The default value is the YAMAHA Vendor ID, 1073h. IHVs must change this ID to their Vendor ID in the BIOS POST routine. In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem Vendor ID. January 14, 1999 -20- b0 YMF724F 46-47h: Subsystem ID Write Register Read / Write Default: 000Dh Access Bus Width: 16-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Subsystem ID Write b[15:0] ........Subsystem ID Write Register This register sets the Subsystem ID that is read from 2E-2Fh (Subsystem ID register). The default value is the DS-1 Device ID, 000Dh. IHVs must change this ID to their ID in the BIOS POST routine. In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem ID. 48-49h: DS-1 Control Register Read / Write Default: 0001h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 - - - - - - - - - - - - - - b3 b2 b1 b0 XRST CRST b0................CRST: AC’97 Software Reset Signal Control This bit controls the CRST# signal. “0”: Inactive (CRST#=High) “1”: Active (CRST#=Low) (default) b1................XRST: Local Device Software Reset Signal Control This bit controls the XRST# signal. “0”: Inactive (XRST#=High) (default) “1”: Active (XRST#=Low) 4A-4Bh: DS-1 Power Control Register Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 - - PSN PSL1 b1 b0................DMC: Disable Master Clock Oscillation Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz). “0”: Normal (default) “1”: Disable b1................DPLL0: Disable PLL0 Clock Oscillation Setting this bit to “1” disables the oscillation of PLL for the Legacy Audio function. “0”: Normal (default) “1”: Disable January 14, 1999 -21- b0 PSL0 DPLL1 DPLL0 DMC YMF724F b2................DPLL1: Disable PLL1 Clock Oscillation Setting this bit to “1” disables the oscillation of PLL for the PCI Audio function. “0”: Normal (default) “1”: Disable b3................PSL0: Power Save Legacy Audio Block 0 Setting this bit to “1” stops providing the clock with the Legacy Audio function block 0. This block includes FM Synthesizer and SB Pro engines. “0”: Normal (default) “1”: Power Save b4................PSL1: Power Save Legacy Audio Block 1 Setting this bit to “1” stops providing the clock with the Legacy Audio function block 1. This block includes MPU401 and Joystick. “0”: Normal (default) “1”: Power Save b5................PSN: Power Save PCI Audio block Setting this bit to “1” stops providing the clock with the PCI Audio function block. This block includes PCI Audio, SRC, AC3F2 I/F, AC’97 I/F, H/W Vol. and SPDIF. “0”: Normal (default) “1”: Power Save b8................PR0: AC’97 Power down Control 0 This bit controls the power state of the ADC and Input Mux in AC’97. “0”: Normal (default) “1”: Power down b9................PR1: AC’97 Power down Control 1 This bit controls the power state of the DAC in AC’97. “0”: Normal (default) “1”: Power down b10..............PR2: AC’97 Power down Control 2 This bit controls the power state of the Analog Mixer (Vref still on) in AC‘97. This power state retains the Reference Voltage of AC’97. “0”: Normal (default) “1”: Power down b11..............PR3: AC’97 Power down Control 3 This bit controls the power state of the Analog Mixer (Vref off) in AC’97. This power state removes Reference Voltage of AC’97. “0”: Normal (default) “1”: Power down January 14, 1999 -22- YMF724F b12..............PR4: AC’97 Power down Control 4 This bit controls the power state of the AC-link in AC’97. “0”: Normal (default) “1”: Power down b13..............PR5: AC’97 Power down Control 5 Setting this bit to “1” disables the internal clock of AC’97. clock is supplied from DS-1. In case AC’97 is used with DS-1, the master Therefore, when the clock of AC’97 is stopped completely, set both PR5 and PSN bits to “1”. “0”: Normal (default) “1”: Disable b[15:14] ......AC’97 Power down Control 6 and 7 These bits control PR6 and PR7 status of the power control register in AC’97. PSL0 Legacy func. 0 Master (24.576MHz) PLL0 33.87MHz DMC DPLL0 FM Synthesizer SB Pro PSL1 Legacy func. 1 MPU401 Joystick PSN PCI func. 0 PLL1 49.152MHz DPLL1 AC3F2 I/F AC'97 I/F H/W Vol. PCI Audio SRC SPDIF PCI func. 1 PCICLK (33MHz) PCI I/F PC/PCI D-DMA S-IRQ - Set DPLL0, DPLL1, PSL0, PSL1 and PSN bits to “1”, when DMC bit is set to “1”. - Set PSL0 and PSL1 bits to “1”, when DPLL0 bit is set to “1”. - Set PSN bit to “1”, when DPLL1 bit is set to “1”. January 14, 1999 -23- YMF724F 4C-4Dh: D-DMA Slave Configuration Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 Base Address b4 b3 EA b2 b1 TS b0................CE: Channel Enable This bit enables the Distributed DMA function. “0”: Disable Distributed DMA (default) “1”: Enable Distributed DMA b[2:1] ..........TS: Transfer Size These bits indicate the size of the DMA transfer. Since DS-1 supports only 8-bit DMA transfer, the bits are hardwired to 00b. b3................EA: Extended Address DS-1 does not support extended address mode. This bit is hardwired to 0b. b[15:4] ........Base Address : D-DMA Slave Base Address These bits indicate the D-DMA slave base address. 50h: Capability ID Read Only Default: 01h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Capability ID b[7:0] ..........Capability ID: Capability Identifier This register indicates that the new capability register is for Power Management control. This register is hardwired to 01h. January 14, 1999 -24- b0 CE YMF724F 51h: Next Item Pointer Read Only Default: 00h Access Bus Width: 8, 16, 32-bit b7 b6 b5 b4 b3 b2 b1 b0 Next Item Pointer b[7:0] ..........Next Item Pointer DS-1 does not provide other new capability besides Power Management. This register is hardwired to 00h. 52-53h: Power Management Capabilities Read Only Default: 0401h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 - - - - - D2S D1S - - - - - - b2 b1 Version b[2:0] ..........Version These bits contain the revision number of the Power Management Interface Specification. They are hardwired to 001b. b9................D1S: D1 Support This bit indicates whether DS-1 support “D1” of the power state. externally, this bit can be set to “1”, and D1 state can support. Only when EEPROM connects When EEPROM does not connect externally, use ACPI mode (58-59h: ACPI Mode Register, ACPI bit) to support D1 state. The default value is “0”. b10..............D2S: D2 Support This bit indicates that DS-1 support “D2” of the power state. It is hardwired to “1”. January 14, 1999 -25- b0 YMF724F 54-55h: Power Management Control / Status Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 - - - - - - - - - - - - - - b1 b0 PS b[1:0] ..........PS: Power State These bits determine the power state of DS-1. “0”: D0 “1”: D1 “2”: D2 “3”: D3hot DS-1 supports the following power states: (not supported) When the power state is changed from D3hot to D0, DS-1 resets the PCI Configuration register 00-3Fh. DS-1 transits to D0 Uninitialized state. Though the power state of this register is changed, the power consumption of DS-1 is not changed. To support low power, Windows driver controls DS-1 Power Control Register. DS-1 can support the power state of D0, D1, D2 and D3 with ACPI. In this case, set ACPI bit (58-59h: ACPI Mode Register) to “1” to disable Capabilities of PCI Bus Power Management. 58-59h: ACPI Mode Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - - - - - - - - - ACPI b0................ACPI: ACPI Mode Select This bit select either PCI Bus Power Management or ACPI Mode for power management of DS-1. “0”: PCI Bus Power Management is used. (34h) are enabled. “1”: ACPI Mode is used. CAP bit (06-07h: Status Register) and Capabilities Pointer (default) CAP bit and Capabilities Pointer are hardwired “0”, and disabled. January 14, 1999 -26- YMF724F 2. ISA Compatible Device DS-1 contains the following functions to maintain the compatibility with the past ISA Sound Devices. These devices are considered Legacy devices and the functions are referred to as Legacy Audio. Legacy Audio is independent from PCI Audio and can be used simultaneously. The configuration is set in the Legacy Audio Control Register in the PCI Configuration Register space. Basically, these registers are configured by the BIOS. Also, logical device IDs are assigned to the devices to support Plug and Play. Yamaha defines the following logical IDs. To control the device with the BIOS, the logical device IDs must be defined in the PnP BIOS extended ROM space. The logical IDs are determined by how it is configured. Logical Device ID IDs and configuration are as follows. Functions used (Block) FM YMH0100 (*) MPU401 SB Pro (*) O O O YMH0101 Joystick O * The blocks pertain to the following. FM: Points to the FM synthesizer mapped to AdLibBase (0x0388). SB Pro: Points to the Voice Playback section only. These devices are independent from each other, and can be Enabled/Disabled individually. AdLib and Sound Blaster must be disabled to disable the internal FM Synthesizer. However, both Disabling just AdLib only masks the access. The driver by Yamaha supports only logical device ID, YMH0100. For YMH0101, use the driver provided by Microsoft. January 14, 1999 -27- YMF724F DS-1 supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI. In addition, DS-1 supports the old type of interrupts used by ISA and the Serialized IRQ protocol. Yamaha recommends the combination of PC/PCI and Serialized IRQ. The system block diagram when using Intel chip set is shown below. North Brigde (430TX/440BX) PCI Address/Data Control PCREQ# PCGNT# DS-1 IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 South Bridge (PIIX4E) SERIRQ# Select either protocols The PCI-to-ISA bridge needs to support PC/PCI. IRQ is directly connected to the IRQ input pins on the PCI-to-ISA bridge. January 14, 1999 -28- YMF724F 2-1. FM Synthesizer Block FM Synthesizer Block is register compatible with YMF289B. However, Power Management register has been deleted because it is now controlled by the PCI Configuration Register. The following shows the FMBase I/O map of FM Synthesizer. FMBase (R) Status Register port FMBase (W) Address port for Register Array 0 FMBase+1 (R/W) Data port FMBase+2 (W) Address port for Register Array 1 FMBase+3 (R/W) Data port The default FMBase value is 0x0388. The following shows the FM Synthesizer Block registers. 2-1-1. Status Register FM Synthesizer Status Register (RO): Address D7 D6 D5 D4 D3 D2 D1 D0 xxh IRQ FT1 FT2 - - BUSY - BUSY January 14, 1999 -29- YMF724F 2-1-2. FM Synthesizer Data Register FM Synthesizer Data Register Array 0 (R/W): Address D7 D6 D5 D4 D3 00-01h LSI TEST 02h TIMER 1 03h TIMER 2 04h 08h (*1) 20-35h D2 D1 D0 RST MT1 MT2 - - - ST2 ST1 - NTS - - - - - - AM VIB EGT KSR (*2) 40-55h MULT KSL TL (*3) AR DR (*4) SL RR 60-75h 80-95h A0-A8h F-NUM (L) B0-B8h - - KON BDh DAM DVB RHY BD *6 *6 CHR CHL - - - - C0-C8h (*5) E0-F5h BLOCK F-NUM (H) SD TOM TC FB HH CNT - WS FM Synthesizer Data Register Array 1 (R/W) Address D7 D6 D5 D4 - - - - - - AM VIB EGT KSR 00-01h 04h 05h (*1) 20-35h D3 D2 40-55h * NEW CONNECTION SEL - * MULT KSL TL (*3) AR DR (*4) SL RR 60-75h 80-95h A0-A8h F-NUM (L) B0-B8h - - KON C0-C8h *6 *6 CHR CHL - - - - E0-F5h D0 LSI TEST (*2) (*5) D1 BLOCK F-NUM (H) FB - CNT WS *1 : 26h, 27h, 2Eh and 2Fh do not exist. *2 : 46h, 47h, 4Eh and 4Fh do not exist. *3 : 66h, 67h, 6Eh and 6Fh do not exist. *4 : 86h, 87h, 8Eh and 8Fh do not exist. *5 : E6h, E7h, EEh and EFh do not exist. *6 : The bits exist, but do not function. January 14, 1999 -30- YMF724F 2-2. Sound Blaster Pro Block This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. functions are supported (record functions are not supported). Only playback However, to maintain compatibility for games, it is designed so that every DSP command receives a correct response. The DMA transfer of this block uses PC/PCI or D-DMA protocol. The following shows the SBBase I/O map of SB Pro. SBBase (R) FM Synthesizer Status port SBBase (W) FM Synthesizer Address port for Register Array 0 SBBase+1h (R/W) FM Synthesizer Data register SBBase+2h (W) FM Synthesizer Address port for Register Array 1 SBBase+3h (R/W) FM Synthesizer Data port SBBase+4h (W) SB Mixer Address port SBBase+5h (R/W) SB Mixer Data port SBBase+6h (W) SB DSP Reset port SBBase+8h (R) FM Synthesizer Status port SBBase+8h (W) FM Synthesizer Address port for Register Array 0 SBBase+9h (R/W) FM Synthesizer Data port SBBase+Ah (R) DSP Read Data port SBBase+Ch (R) DSP Write-buffer status port SBBase+Ch (W) DSP Write Command/Data port SBBase+Eh (R) DSP Read-buffer status port January 14, 1999 -31- YMF724F 2-2-1. DSP Command The following shows the list of DSP Commands that are supported by the SB Pro engine. Both SB and SB Pro commands are supported. CMD Support Function 10h 14h 16h 17h 1Ch 1Fh 20h(*1) 24h(*1) 2Ch(*1) 30h 31h 34h 35h 36h(*2) 37h(*2) 38h 40h 48h 74h 75h 76h 77h 7Dh 7Fh 80h 90h 91h 98h(*1) 99h(*1) A0h(*1) A8h(*1) D0h D1h(*3) D3h(*3) D4h D8h DAh E1h o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o 8bit direct mode single byte digitized sound output 8bit single-cycle DMA mode digitized sound output 8bit to 2bit ADPCM single-cycle DMA mode digitized sound output 8bit to 2bit ADPCM single-cycle DMA mode digitized sound output with ref. byte 8bit auto-init DMA mode digitized sound output 8bit to 2bit ADPCM auto-init DMA mode digitized sound output with ref. byte 8bit direct mode single byte digitized sound input 8bit single-cycle DMA mode digitized sound input 8bit auto-init DMA mode digitized sound input Polling mode MIDI input Interrupt mode MIDI input UART polling mode MIDI I/O UART interrupt mode MIDI I/O UART polling mode MIDI I/O with time stamping UART interrupt mode MIDI I/O with time stamping MIDI output Set digitized sound transfer Time Constant Set DSP block transfer size 8bit to 4bit ADPCM single-cycle DMA mode digitized sound output 8bit to 4bit ADPCM single-cycle DMA mode digitized sound output with ref. byte 8bit to 3bit ADPCM single-cycle DAM mode digitized sound output 8bit to 3bit ADPCM single-cycle DMA mode digitized sound output with ref. byte 8bit to 4bit ADPCM auto-init DMA mode digitized sound output with ref. byte 8bit to 3bit ADPCM auto-init DMA mode digitized sound output with ref. byte Pause DAC for a duration 8bit high-speed auto-init DMA mode digitized sound output 8bit high-speed single-cycle DMA mode digitized sound output 8bit high-speed auto-init DMA mode digitized sound input 8bit high-speed single-cycle DMA mode digitized sound input Set input mode to mono Set input mode to stereo Pause 8bit DMA mode digitized sound I/O Turn on speaker Turn off speaker Continue 8bit DMA mode digitized sound I/O Get speaker status Exit 8bit auto-init DMA mode digitized sound I/O Get DSP version number Note: (*1) The SB Block responds correctly to the commands for recording and also executes the DMA transfer. 80h is always transferred. (*2) Only output is supported for this command. (*3) This command only changes Speaker Status (D8h). Undocumented commands other than the ones listed above are also supported. January 14, 1999 -32- YMF724F 2-2-2. Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro. Address b7 b6 b5 b4 00h Voice Volume L "1" 0Ah - - - "1" 0Ch - - Ifilter* "1" 0Eh - - Ofilter* "1" 22h Master Volume L 26h 28h 2Eh b1 b0 Voice Volume R Remark - "1" MIC Volume* Input Source* "1" - "1" - St. SW "1" Master Volume R MIDI Volume L "1" MIDI Volume R "1" CD Volume L* "1" CD Volume R* "1" Line Volume L* SBPDA - "1" - F1h F8h b2 Reset 04h F0h b3 - - - Line Volume R* - SS SCAN DATA - - SB Pro Mixer "1" "1" SM SE SBPDR - - SBI Suspend / Resume IRQ Status The registers marked with * exist, but do not function. DS-1 does not have the circuit that corresponds to the SB Mixer. Therefore, the volume settings on the SB Mixer are converted to the DSP coefficients of DS-1 or to AC’97 register values. The conversion for each case is described below. (1) SB Mixer ® DSP The volume of master, MIDI and Voice, are applied to this case. When the SB register is set, a 14-bit coefficient value is determined from the following conversion table and used as the DSP coefficient. The attenuation value of Master Volume, MIDI, and voice are summed together to obtain the coefficient. These volumes cannot be controlled from PCI Audio block. January 14, 1999 -33- YMF724F (1) Volume for MIDI MIDI Vol. (26h) 0 0 Master Vol. (22h) 1 2 3 4 5 6 7 1 2 3 4 5 6 7 mute mute mute mute mute mute mute mute 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h -26dB mute -52dB -42dB -36dB -32dB -30dB -28dB 0000h 0029h 0082h 0103h 019Bh 0206h 028Ch 0335h mute -42dB -32dB -26dB -22dB -20dB -18dB -16dB 0000h 0082h 019Bh 0335h 0515h 0666h 080Eh 0A24h mute -36dB -26dB -20dB -16dB -14dB -12dB -10dB 0000h 0103h 0335h 0666h 0A24h 0CC5h 1013h 143Dh mute -32dB -22dB -16dB -12dB -10dB -8dB -6dB 0000h 019Bh 0515h 0A24h 1013h 143Dh 197Ah 2013h mute -30dB -20dB -14dB -10dB -8dB -6dB -4dB 2861h 0000h 0206h 0666h 0CC5h 143Dh 197Ah 2013h mute -28dB -18dB -12dB -8dB -6dB -4dB -2dB 0000h 028Ch 080Eh 1013h 197Ah 2013h 2861h 32D6h mute -26dB -16dB -10dB -6dB -4dB -2dB 0dB 0000h 0335h 0A24h 143Dh 2013h 2861h 32D6h 3FFFh The default is Master = 4, MIDI = 4 (-12dB). (2) Volume for Voice Voice Vol. (04h) 0 Master Vol. (22h) 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 mute mute mute mute mute mute mute mute 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h mute -56dB -46dB -40dB -36dB -34dB -32dB -30dB 0000h 0019h 0052h 00A3h 0103h 0146h 019Bh 0206h mute -46dB -36dB -30dB -26dB -24dB -22dB -20dB 0000h 0052h 0103h 0206h 0335h 0409h 0515h 0666Eh mute -40dB -30dB -24dB -20dB -18dB -16dB -14dB 0000h 00A3h 0206h 0409h 0666h 080Eh 0A24h 0CC5h mute -36dB -26dB -20dB -16dB -14dB -12dB -10dB 143Dh 0000h 0103h 0335h 0666h 0A24h 0CC5h 1013h mute -34dB -24dB -18dB -14dB -12dB -10dB -8dB 0000h 0146h 0409h 080Eh 0CC5h 1013h 143Dh 197Ah mute -32dB -22dB -16dB -12dB -10dB -8dB -6dB 0000h 019Bh 0515h 0A24h 1013h 143Dh 197Ah 2013h mute -30dB -20dB -14dB -10dB -8dB -6dB -4dB 0000h 0206h 0666h 0CC5h 143Dh 187Ah 2013h 2861h The default is Master = 4, Voice = 4 (-16dB). (2) SB Mixer ® AC’97 The volume of CD, Line and MIC are applied to this case. when these values are changed. AC’97 volume are not updated automatically Thus, the SB Mixer values need to be written to the AC’97 register with the software. January 14, 1999 -34- YMF724F 2-2-3. SB Suspend / Resume The SB block can read the internal state as to support Suspend and Resume functions. is made up of 218 flip flops. The internal state To read the state, these states are shifted in order and read 8 bits at a time from the SCAN DATA register. These registers are mapped to the SB Mixer space (see SB Mixer Register map). The registers have the following functions. F0h: Scan In/ Out Control Read / Write Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 SBPDA - - - SS SM SE SBPDR b0................SBPDR: Sound Blaster Power Down Request This bit stops the internal state of the Sound Blaster block. “0”: Normal (default) “1”: Stop b1................SE: Scan Enable This bit Shifts the internal state by 1 bit. Setting a “1” followed by a “0” shifts the internal state. b2................SM: Scan Mode This bit sets whether to read or write the state. “0”: Write (default) “1”: Read b3................SS: Scan Select This bit gives permission to read or write the internal data to the SCAN DATA register. “0”: Normal operation (Do not allow read or write). (default) “1”: Allow read and write. b7................SBPDA: Sound Blaster Power Down Acknowledgement This bit indicates that the SB Block is ready to read or write to the internal state after setting SBPDR. This bit is read only. “0”: Read/Write not possible “1”: Read/ Write possible January 14, 1999 -35- YMF724F F1h: Scan In/ Out Data Read / Write Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 SCAN DATA b[7:0] ..........SCAN DATA This is the data port for reading and writing the internal state. F8h: Interrupt Flag Register Read Only Default: 00h b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - - SBI b0................SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. read port to clearing the interrupt and this bit. This bit is read only. Thus, read the SB DSP Then, the value of the read port is invalid. January 14, 1999 -36- YMF724F 2-3. MPU401 This block is for transmitting and receiving MIDI data. It is compatible with UART mode of “MPU401”. Full duplex operation is possible using the 16-byte FIFO for each direction, transmitting and receiving. The following shows the MPUBase I/O map for MPU401. MPUBase (R/W) MIDI Data port MPUBase + 1h (R) Status Register port MPUBase + 1h (W) Command Register port port D7 D6 D5 D4 D3 +0h Data +1h (W) Command +1h (R) /DSR D2 D1 D0 /DRR - - - - - - 2-4. Joystick JSBase (R/W) port D7 D6 D5 D4 D3 D2 D1 D0 +0h JBB2 JBB1 JAB2 JAB1 JBCY JBCX JACY JACX JACX... JACY... JBCX... JBCY... JAB1... JAB2... JBB1... JBB2... Joystick A, Coordinate X Joystick A, Coordinate Y Joystick B, Coordinate X Joystick B, Coordinate Y Joystick A, Button 1 Joystick A, Button 2 Joystick B, Button 1 Joystick B, Button 2 January 14, 1999 -37- YMF724F 3. DMA Emulation Protocol The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA DMAC) on the system to transfer the sound data from/to the host. For DS-1, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block. Because signals to connect to the ISA DMAC are generally not available on the PCI bus, there are two ways proposed from the industry to emulate the ISA DMAC on the PCI bus. One is PC/PCI and the other is DDMA. DS-1 supports both protocols for transferring SB Pro sound data on the PCI bus. 3-1. PC/PCI DS-1 provides two signals, PCREQ# and PCGNT# to realize the PC/PCI. The format of the signals is shown below. DS-1 asserts PCREQ# and sets PCREQ# to “HIGH” using the PCICLK corresponding to the DMA channel it is going to use. In addition, DS-1 determines whether the next PCI I/O cycle is its own from the channel information that is encoded in PCGNT#. 0ns 100ns 200ns 300ns 400ns PCICLK REQ# start CH0 CH1 CH2 CH3 CH4 CH5 GNT# CH6 CH7 start bit0 bit1 bit2 PCGNT# is encoded as follows. GNT# Encoding bit2 bit1 bit0 GNT# Bits DMA Channel 0 0 0 0 DMA Channel 1 0 0 1 DMA Channel 2 0 1 0 DMA Channel 3 0 1 1 Reserved 1 0 0 DMA Channel 5 1 0 1 DMA Channel 6 1 1 0 DMA Channel 7 1 1 1 DS-1 supports only 8-bit DMA channels (DMA Channel 0-3). It also only supports Single DMA transfer. January 14, 1999 -38- YMF724F 3-2. D-DMA DS-1 provides the following registers to support D-DMA. D-DMA Slave Configuration Register (4C-4Dh) of the PCI Configuration register is used to set the Base address of the Slave Address. Slave Address Base + 0h Base + 0h Base + 1h Base + 1h Base + 2h Base + 2h Base + 3h Base + 3h Base + 4h Base + 4h Base + 5h Base + 5h Base + 6h Base + 6h Base + 7h Base + 8h Base + 8h Base + 9h Base + Ah Base + Bh Base + Ch Base + Dh Base + Eh Base + Fh R/W W R W R W R W R W R W R W R N/A W R W N/A W W W N/A R/W Register Name Base Address 0-7 Current Address 0-7 Base Address 8-15 Current Address 8-15 Base Address 16-23 Current Address 16-23 Base Address 24-31 Current Address 24-31 Base Word Count 0-7 Current Word Count 0-7 Base Word Count 8-15 Current Word Count 8-15 Base Word Count 16-23 Current Word Count 16-23 Reserved Command Status Request Reserved Mode Reserved Master Clear Reserved Multi-Channel Mask These registers can be accessed by 8-bit or 16-bit bus width. DS-1 supports 8-bit DMA transfer only. January 14, 1999 -39- YMF724F 4. Interrupt Routing DS-1 supports three types of interrupts, interrupt signal on the PCI bus (INTA#), interrupt signal on the ISA bus (IRQ[5,7,9,10,11]), and Serialized IRQ. The IRQs on DS-1 are routed as shown below. PCI Audio SIEN=0, IMOD=1 SIEN=0, IMOD=0 IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 SIEN=1, IMOD=* IRQ Sound Blaster Pro Select Signal SBIRQ[2:0] ISA IRQ SIEN=0, IMOD=1 SIEN=0, IMOD=0 SIEN=1, IMOD=* SERIRQ# Selector INTA Selector INTA# IRQ MPU401 SIEN, IMOD SERIRQ Select Signal MPUIRQ[2:0] PCI Audio can only use INTA#, but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the three protocols. The protocol can be switched using 40-43h (Legacy Audio Control Register) of the PCI Configuration Register. 4-1. Serialized IRQ Serialized IRQ is a method to encode IRQs of 15 channels into one signal. DS-1 provides the SERIRQ# pin to support Serialized IRQ. Only one channel out of the 5 channels, IRQ5, IRQ7, IRQ9, IRQ10, and IRQ11, can be encoded into the IRQ/Data frame of Serialized IRQ. The IRQ channel is selected using 40h-43h (Legacy Audio Control Register) of the PCI Configuration Register. 5. Digital Audio Interface DS-1 only supports SPDIF output conforming to IEC958. The only supported Fs is 48 kHz. It can be selectable from the Dolby Digital (AC-3) encoded data or the result of Digital Mixing. January 14, 1999 -40- YMF724F 6. Hardware Volume Control The hardware volume control determines the AC’97 master volume without using any software control using the external circuit listed below. Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used. Push SW 1k VOLUP# Push SW 1k VOLDW# 1000p 1000p DS-1 provides a shadow register for the AC’97 master volume. When the software accesses the AC’97 Master Volume, it is always reflected in the shadow register. The value of the shadow register is incremented by 1.5dB on the rising edge of the signal input to the VOLUP# pin. If it is already set to the maximum value, it does not change. The value set in the shadow register automatically updates the AC’97 master volume register through the AC-Link. The value of the shadow register is decremented by 1.5dB on the rising edge of the signal input to the VOLDW# pin. If it is already set to the minimum value, it does not change. The value set in the shadow register automatically updates the AC’97 master volume register through the AC-Link. Also, when both VOLUP#, VOLDW# pins are at LOW level, the MUTE bit of the shadow address is enabled and the Master Volume Mute bit of the AC’97 register is automatically set through the AC-Link. When a rising edge is detected on either VOLUP# or VOLDW#, the MUTE bit is reset through the AC-Link. The Master Volume is set to the value before the Mute. If the AC-Link is BUSY (when controlling the register from the AC’97 Control Register), the value in the shadow register is set to AC’97 on the next frame. The AC’97 Control Register is set to BUSY in this case. When the master volume changes or is muted due to VOLUP#, VOLDW#, an interrupt is generated at the host. The interrupt is used to notify the driver that the Master Volume has been changed from the outside. January 14, 1999 -41- YMF724F ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Item Symbol Min. Max. Unit Power Supply Voltage 1 (PVDD, VDD5) VDD5 -0.5 7.0 V Power Supply Voltage 2 (VDD3, LVDD) VDD3 -0.3 4.6 V Input Voltage 1 (PVDD, VDD5) VIN5 -0.5 VDD5+0.5 V Input Voltage 2 (VDD3, LVDD) VIN3 -0.3 VDD3+0.3 V Operating Ambient Temperature TOP 0 70 °C Storage Temperature TSTG -50 125 °C Note : PVSS=LVSS=VSS=0[V] 2. Recommended Operating Conditions Item Symbol Min. Typ. Max. Unit Power Supply Voltage 1 (PVDD, VDD5) VDD5 4.75 5.00 5.25 V Power Supply Voltage 2 (VDD3, LVDD) VDD3 3.00 3.30 3.60 V Operating Ambient Temperature TOP 0 25 70 °C Note : PVSS=LVSS=VSS=0[V] January 14, 1999 -42- YMF724F 3. DC Characteristics Item Symbol Condition Min. Typ. Max. Unit High Level Input Voltage 1 VIH1 *1 2.2 VDD5 +0.5 V Low Level Input Voltage 1 VIL1 *1 -0.5 0.8 V High Level Input Voltage 2 VIH2 *2 2.2 VDD5 +0.5 V Low Level Input Voltage 2 VIL2 *2 -0.5 0.6 V High Level Input Voltage 3 VIH3 *3 2.2 Low Level Input Voltage 3 VIL3 *3 High Level Input Voltage 4 VIH4 *4 Low Level Input Voltage 4 VIL4 *4 Input Leakage Current IIL V 0.8 0.7VDD5 0< VIN < VDD5 -10 2.4 High Level Output Voltage 1 VOH1 *5, IOH1 = -1mA Low Level Output Voltage 1 VOL1 *5, IOL1 = 3mA High Level Output Voltage 2 VOH2 *6, IOH2 = -2mA Low Level Output Voltage 2 VOL2 *6, IOL2 = 6mA High Level Output Voltage 3 VOH3 *7, IOH3 = -4mA Low Level Output Voltage 3 VOL3 *7, IOL3 = 12mA High Level Output Voltage 4 VOH4 *8, IOH4 = -80µA Low Level Output Voltage 4 VOL4 *8, IOL4 = 2mA Input Pin Capacitance CIN Clock Pin Capacitance V V 0.2VDD5 V 10 µA V 0.55 2.4 V V 0.55 2.4 V V 0.55 VDD5-1.0 V V 0.4 V 5 15 pF CCLK 5 15 pF IDSEL Pin Capacitance CIDSEL 5 15 pF Output Leakage Current IOL -10 10 µA PVDD+VDD5 60 mA VDD3 145 mA 0.5 2 mA 6 10 mA Power Supply Current 1 (Normal Operation) Power Supply Current 2 (Power Save) *9, PVDD+VDD5 *9, VDD3 Note : Top = 0~70°C, PVDD=5.0±0.25[V], VDD5=5.0±0.25[V], VDD3=3.3±0.3[V], LVDD=3.3±0.3[V], CL=50 pF *1: Applicable to all PCI Iuput/Output pins and Iunput pins except PCICLK and RST# pin. *2: Applicable to RST# pin. *3: Applicable to CBCLK, CSDI, ACDI, ASDI, GP[7:4], RXD, VOLUP#, VOLDW#, ROMDI and TEST[7:0]# pins. *4: Applicable to XI24 pin. *5: Applicable to AD[31:0], C/BE[3:0]#, PAR, REQ#, PCREQ#, SERIRQ#, TXD, ALRCK, ASDO, ACDO, ACS#, ROMSK, ROMDO, ROMCS and DIT pins. *6: Applicable to FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, PERR#, SERR#, ABCLK, ASCLK, CRST#, CSYNC and CSDO pins. *7: Applicable to IRQ5, IRQ7, IRQ9, IRQ10, IRQ11 and INTA# pins. *8: Applicable to CMCLK, XRST# and XO24 pins. *9: DS-1 Power Control Register, DMC=DPLL0=DPLL1=PSN=PSL0=PSL1=“1”, PCICLK (33MHz) is stopped. January 14, 1999 -43- YMF724F 4. AC Characteristics 4-1. Master Clock (Fig.1) Item Symbol Min. Typ. Max. Unit XI24 Cycle Time tXICYC - 40.69 - ns XI24 High Time tXIHIGH 16 - 24 ns XI24 Low Time tXILOW 16 - 24 ns Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V 3.5 V 2.5 V XI24 1.0 V t XIHIGH t XILOW t XICYC Fig.1: XI24 Master Clock timing 4-2. Reset (Fig.2) Item Reset Active Time after Power Stable Power Stable to Reset Rising Edge Reset Slew Rate Symbol Min. Typ. Max. Unit tRST 1 - - ms tRSTOFF 10 - - ms - 50 - - mV/ns Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF 4.75 V PVDD, VDD5 3.0 V LVDD, VDD3 t RSTOFF t RST RST# 0.6 V Fig.2: PCI Reset timing January 14, 1999 -44- YMF724F 4-3. PCI Interface (Fig.3, 4) Item Symbol Condition Min. Typ. Max. Unit PCICLK Cycle Time tPCYC 30 - - ns PCICLK High Time tPHIGH 11 - - ns PCICLK Low Time tPLOW 11 - - ns PCICLK Slew Rate - 1 - 4 V/ns 2 - 11 ns 2 - 12 ns PCICLK to Signal Valid Delay tPVAL (Bused signal) tPVAL(PTP) (Point to Point) Float to Active Delay tPON 2 - - ns Active to Float Delay tPOFF - - 28 ns (Bused signal) 7 - - ns *10 (Point to Point) 10 *11 (Point to Point) 12 - - ns 0 - - ns tPSU Input Setup Time to PCICLK tPSU(PTP) Input Hold Time for PCICLK tPH ns Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF *10: This characteristic is applicable to REQ# and PCREQ# signal. *11: This characteristic is applicable to GNT# and PCGNT# signal. 2.2 V 1.5 V PCICLK 0.8 V t PHIGH t PLOW t PCYC Fig.3: PCI Clock timing 1.5 V PCICLK t PVAL 1.5 V OUTPUT t PON Tri-State OUTPUT t PSU t POFF t PH 1.5 V INPUT Fig.4: PCI Bus Signals timing January 14, 1999 -45- YMF724F 4-4. AC’97 / AC3F2 Master Clock Item (Fig.5) Symbol Min. Typ. Max. Unit CMCLK Cycle Time tCMCYC - 40.69 - ns CMCLK High Time tCMHIGH 8 - - ns CMCLK Low Time tCMLOW 8 - ns CMCLK Rising Time tCMR - 4.6 - ns CMCLK Falling Time tCMF - 2.1 - ns Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF t CMR t CMF 3.5 V 2.5 V CMCLK 0.4 V t CMHIGH t CMLOW t CMCYC Fig.5: Master Clock timing for AC’97 and AC3F2 4-5. AC-link (Fig.6) Item Symbol Condition Min. Typ. Max. Unit CBCLK Cycle Time tCBICYC - 81.4 - ns CBCLK High Time tCBIHIGH 35 40.7 45 ns CBCLK Low Time tCBILOW 35 40.7 45 ns CSYNC Cycle Time tCSYCYC - 20.8 - ns CSYNC High Time tCSYHIGH - 1.3 - ns CSYNC Low Time tCSYLOW - 19.5 - ns CBCLK to Signal Valid Delay tCVAL *12 - - 20 ns Output Hold Time for CBCLK tCOH *12 0 - - ns Input Setup Time to CBCLK tCISU *13 15 - - ns Input Hold Time for CBCLK tCIH *13 5 - - ns - 1.3 - µs Warm Reset Width Note) Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF *12: This characteristic is applicable to CSYNC and CSDO signal. *13: This characteristic is applicable to CSDI signal. January 14, 1999 -46- YMF724F t CBICYC 2.2 V CBCLK 1.5 V t CBIHIGH 0.8 V t CBILOW t COH t CSYLOW t CVAL 2.2 V SYNC 1.5 V 0.8 V t CSYHIGH t CSYCYC t CVAL t COH 2.2 V CSDO 0.8 V t CISU t CIH 2.2 V CSDI 0.8 V Fig.6: AC-link timing 4-6 AC3F2 Interface (Fig.7, 8) Item Symbol Condition Min. Typ. Max. Unit ASCLK Cycle Time tASCCYC - 325 - ns ASCLK High Time tASCHIGH 140 - 180 ns ASCLK Low Time tASCLOW 140 - 180 ns ASCLK to Signal Valid Delay tACVAL *14 - - 50 ns Output Hold Time for ASCLK tACOH *14 -10 - - ns Input Setup Time to ASCLK tACISU *15 20 - - ns Input Hold Time for ASCLK tACIH *15 10 - - ns ABCLK Cycle Time tABICYC - 325 - ns ABCLK High Time tABIHIGH 140 - 180 ns ABCLK Low Time tABILOW 140 - 180 ns ABCLK to Signal Valid Delay tASVAL *16 - - 50 ns Output Hold Time for ABCLK tASOH *16 -10 - - ns Input Setup Time to ABCLK tASISU *17 20 - - ns Input Hold Time for ABCLK tASIH *17 10 - - ns Note) Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF *14: This characteristic is applicable to ACS and ACDO signal. *15:This characteristic is applicable to ACDI signal. *16: This characteristic is applicable to ASDO and ALRCK signal. *17: This characteristic is applicable to ASDI signal. January 14, 1999 -47- YMF724F t ASCCYC 2.2 V 1.5 V ASCLK 0.8 V t ASCLOW t ASCHIGH t ACVAL t ACOH 2.2 V ACS, ACDO 0.8 V t ACISU t ACIH 2.2 V ACDI 0.8 V Fig.7: AC3F2 Control Interface timing tABICYC 2.2 V 1.5 V ABCLK 0.8 V tABILOW tABIHIGH tASVAL t ASOH 2.2 V ASDO, ALRCK 0.8 V t ASISU t ASIH 2.2 V ASDI 0.8 V Fig.8: AC3F2 Audio Interface timing January 14, 1999 -48- YMF724F EXTERNAL DIMENSIONS YMF724F-V 22.00±0.40 20.00±0.30 108 73 72 144 37 1.40±0.20 1 1.70MAX. 0 MIN. (STAND OFF) 22.00±0.40 20.00±0.30 109 36 0.20±0.10 P-0.50TYP (1.00) 0-10˚ LEAD THICKNESS : 0.15+0.10 -0.06 0.50±0.20 The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. For detailed information, please contact your nearest agent of Yamaha. January 14, 1999 -49- YMF724F IMPORTANT NOTICE 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS. 4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT, COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY. 5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND TITLE. Note) The specifications of this product are subject to improvement change without prior notice. AGENCY YAMAHA CORPORATION Address inquires to : Semi-conductor Sales Department - Head Office - Tokyo Office - Osaka Office - U.S.A. Office 203, MatsunokiJima, Toyooka-mura. Iwata-gun, Shizuoka-ken, 438-0192 Tel. +81-539-62-4918 Fax. +81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. +81-3-5488-5431 Fax. +81-3-5488-5088 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. +81-6-6633-3690 Fax. +81-6-6633-3691 YAMAHA System Technology. 100 Century Center Court, San Jose, CA 95112 Tel. +1-408-467-2300 Fax. +1-408-437-8791 January 14, 1999 -50-