ETC YMF744B

YMF744B
Preliminary
DS-1S
OVERVIEW
YMF744B (DS-1S) is a high performance audio controller for the PCI Bus. DS-1S consists of two separated
functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block
allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine.
The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without
utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio
provides 64-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware
accelerator, Downloadable Sound (DLS) and DirectMusic accelerator.
Legacy Audio block supports FM Synthesizer, Sound Blaster Pro, MPU401 UART mode and Joystick
function in order to provide hardware compatibility for numerous PC games on real DOS without any software
driver. To achieve legacy DMAC compatibility on the PCI, DS-1S supports both PC/PCI and Distributed
DMA protocols. DS-1S also supports Serialized IRQ for legacy IRQ compatibility.
DS-1S supports the connection to AC’97 which provides high quality DAC, ADC and analog mixing, and it
can connect two AC’97s. In addition, it supports consumer IEC958, Audio Digital Interface (SPDIF), to
connect external audio equipment by digital.
FEATURES
• PCI 2.2 Compliant
• PC’98/PC’99 specification Compliant
• PCI Bus Power Management rev. 1.0 Compliant
(Support D0, D2 and D3 state)
• Supports clock run
• PCI Bus Master for PCI Audio
True Full Duplex Playback and Capture with
different Sampling Rate
Maximum 64-voice XG capital Wavetable
Synthesizer including GM compatibility
DirectSound Hardware Acceleration
DirectMusic Hardware Acceleration
Downloadable Sound (DLS) level-1
• Legacy Audio compatibility
FM Synthesizer
Hardware Sound Blaster Pro compatibility
MPU401 UART mode MIDI interface
Joystick
• Supports Serialized IRQ
• Supports PC/PCI and Distributed DMA for legacy
DMAC (8237) emulation
• Supports I2S serial input for Zoomed Video Port
• Supports Consumer IEC958 Output (SPDIF OUT)
• Supports Consumer IEC958 Input (SPDIF IN)
• Supports AC’97 Interface (AC-Link) Revision 2.1
• AC’97 Digital Docking
• Supports 4-Channel Speaker
• Hardware Volume Control
• EEPROM Interface
• Single Crystal operation (24.576MHz)
• 3.3V Power supply (5V tolerant)
• 128-pin LQFP YMF744B-V : 0.5mm pin pitch
YMF744B-R : 0.4mm pin pitch
The contents of this catalog are target specifications and are subject to change
without prior notice. When using this device, please recheck the specifications.
YAMAHA CORPORATION
YMF744B CATALOG
December 18, 1998
CATALOG No.:LSI-4MF744B00
February 3, 1999
YMF744B
LOGOS
GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI),
and indicates GM system level 1 Compliant.
XG logo is a trademark of YAMAHA Corporation.
SONDIUS-XG logo is a trademark that Stanford University in the United States and
YAMAHA Corporation hold jointly.
Sensaura logo is a trademark of Central Research Laboratories Limited.
1. GM system level 1
GM system level 1 is a world standard format about MIDI synthesizer which provides voice arrangements
and MIDI functions.
2. XG
XG is a format about MIDI synthesizer that is proposed by YAMAHA, and keeps the upper compatibility of
GM system level 1.
The good points are the voice arrangements kept extensively, a large number of the
voices, modification of the voices, 3 kinds of effects, and so on.
3. SONDIUS-XG
Products bearing the SONDIUS-XG logo are licensed under patents of Stanford University and YAMAHA
Corporation as listed on <http://www.sondius-xg.com>.
The SONDIUS-XG produces acoustic sound
outputs by running a virtual simulation of the actual acoustic instrument operation.
Therefore, it provides
much more real-world acoustic sound outputs fundamentally different from the Wavetable sound generator
that simply processes the recorded acoustic sound sources only.
The SONDIUS-XG adds the technology
of virtual acoustic sound to the XG format.
4. Sensaura
Sensaura is a technology which provides 3D positional audio and moving effect by HRTF (Head Related
Transfer Function) with 2 speakers or headphone.
This feature makes it possible to enjoy invariable and
unchangeable sound feelings in all-positional area covering as wide as 360 degrees.
February 3, 1999
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YMF744B
PIN CONFIGURATION
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
AD27
AD28
PVSS5
AD29
AD30
AD31
REQ#
GNT#
PCICLK
RST#
PVSS6
PVDD3
RESERVE0
INTA#
CVDD2
RESERVE1
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
TXD
RXD
YMF744B-V (0.5mm pin pitch)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
TEST#
VDD2
VSS3
VDD1
CMCLK
CSDO
CBCLK
CSDI0
CSYNC
CRST#
VDD0
VSS2
RESERVE2
RESERVE3
CSDI2
DOCKEN#
VSS1
XI24
XO24
LOOPF
LVDD
CVDD1
ZVBCLK
ZVLRCK
ZVSDI
SPDIFOUT
SPDIFIN
IRQ11
IRQ10
IRQ9
IRQ7
IRQ5
GPIO2
GPIO1
GPIO0
RESERVE8
RESERVE9
RESERVE10
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
AD7
AD6
AD5
PVDD0
AD4
AD3
AD2
AD1
PVSS0
AD0
SERIRQ#
PCGNT#
PCREQ#
CLKRUN#
CVDD0
ROMDI
ROMDO/VOLDW#
ROMSK/VOLUP#
ROMCS
RESERVE16
RESERVE15
RESERVE14
RESERVE13
RESERVE12
RESERVE11
VSS0
AD26
PVDD2
AD25
AD24
CBE3#
IDSEL
AD23
PVSS4
AD22
AD21
AD20
AD19
AD18
AD17
AD16
CBE2#
PVSS3
FRAME#
IRDY#
TRDY#
DEVSEL#
PVDD1
STOP#
PERR#
SERR#
PAR
CBE1#
PVSS2
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
PVSS1
CBE0#
128 Pin LQFP Top View
February 3, 1999
-3-
YMF744B
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
AD25
PVDD2
AD26
AD27
AD28
PVSS5
AD29
AD30
AD31
REQ#
GNT#
PCICLK
RST#
PVSS6
PVDD3
RESERVE0
INTA#
CVDD2
RESERVE1
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
TXD
RXD
TEST#
VDD2
VSS3
YMF744B-R (0.4mm pin pitch)
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VDD1
CMCLK
CSDO
CBCLK
CSDI0
CSYNC
CRST#
VDD0
VSS2
RESERVE2
RESERVE3
CSDI2
DOCKEN#
VSS1
XI24
XO24
LOOPF
LVDD
CVDD1
ZVBCLK
ZVLRCK
ZVSDI
SPDIFOUT
SPDIFIN
IRQ11
IRQ10
IRQ9
IRQ7
IRQ5
GPIO2
GPIO1
GPIO0
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AD8
PVSS1
CBE0#
AD7
AD6
AD5
PVDD0
AD4
AD3
AD2
AD1
PVSS0
AD0
SERIRQ#
PCGNT#
PCREQ#
CLKRUN#
CVDD0
ROMDI
ROMDO/VOLDW#
ROMSK/VOLUP#
ROMCS
RESERVE16
RESERVE15
RESERVE14
RESERVE13
RESERVE12
RESERVE11
VSS0
RESERVE10
RESERVE9
RESERVE8
AD24
CBE3#
IDSEL
AD23
PVSS4
AD22
AD21
AD20
AD19
AD18
AD17
AD16
CBE2#
PVSS3
FRAME#
IRDY#
TRDY#
DEVSEL#
PVDD1
STOP#
PERR#
SERR#
PAR
CBE1#
PVSS2
AD15
AD14
AD13
AD12
AD11
AD10
AD9
128 Pin LQFP Top View
February 3, 1999
-4-
YMF744B
PIN DESCRIPTION
1. PCI Bus Interface (54-pin)
Name
I/O
Type
Size
Function
PCICLK
I
P
PCI Clock
RST#
I
P
Reset
AD[31:0]
IO
Ptr
Address / Data
C/BE[3:0]#
IO
Ptr
Command / Byte Enable
PAR
IO
Ptr
Parity
FRAME#
IO
Pstr
Frame
IRDY#
IO
Pstr
Initiator Ready
TRDY#
IO
Pstr
Target Ready
STOP#
IO
Pstr
Stop
IDSEL
I
P
DEVSEL#
IO
Pstr
Device Select
REQ#
O
Ptr
PCI Request
GNT#
I
P
PCREQ#
O
Ptr
PCGNT#
I
P
PERR#
IO
Pstr
Parity Error
SERR#
O
Pod
System Error
INTA#
O
Pod
Interrupt signal output for PCI bus
SERIRQ#
IO
Ptr
Serialized IRQ
CLKRUN#
IO
Ptr
Clock Run
ID Select
PCI Grant
PC/PCI Request
PC/PCI Grant
2. AC’97 Interface (8-pin)
Name
I/O
Type
Size
Function
CRST#
O
T
6mA
Reset signal for AC’97
CMCLK
O
C
6mA
Master Clock for AC’97 (24.576MHz)
CBCLK
I
T
-
AC-link: Bit Clock for AC’97 audio data
CSDO
O
T
6mA
AC-link: AC’97 Serial audio output data
CSYNC
O
T
6mA
AC-link: AC’97 Synchronized signal
CSDI0
I
T
-
AC-link: AC’97 Serial audio input data (Primary)
CSDI2
I
Tup
-
AC-link: AC’97 Serial audio input data (Secondary)
DOCKEN#
I
Tup
-
Docking Enable
February 3, 1999
-5-
YMF744B
3. External Audio Interface (5-pin)
Name
I/O
Type
Size
Function
SPDIFOUT
O
T
2mA
Digital Audio Interface output
SPDIFIN
I
Tup
-
Digital Audio Interface input
ZVBCLK
I
Tup
-
Zoomed Video Port
Bit Clock
ZVLRCK
I
Tup
-
Zoomed Video Port
L/R Clock
ZVSDI
I
Tup
-
Zoomed Video Port
Serial Data
4. Legacy Device Interface (15-pin)
Name
I/O
Type
Size
Function
Interrupt5 of Legacy Audio
IRQ5
O
Ttr
12mA
It is directly connected to the interrupt signal of
System I/O chip.
IRQ7
O
Ttr
12mA
Interrupt7 of Legacy Audio
IRQ9
O
Ttr
12mA
Interrupt9 of Legacy Audio
IRQ10
O
Ttr
12mA
Interrupt10 of Legacy Audio
IRQ11
O
Ttr
12mA
Interrupt11 of Legacy Audio.
GP[3:0]
I
A
-
Game Port
GP[7:4]
I
Tup
-
Game Port
RXD
I
Tup
-
MIDI Data Receive
TXD
O
T
2mA
MIDI Data Transfer
I/O
Type
Size
ROMCS
O
T
2mA
ROMSK / VOLUP#
IO
Tup
2mA
ROMDO / VOLDW#
IO
Tup
2mA
ROMDI
I
Tup
-
Serial data input for external EEPROM
XI24
I
C
-
24.576 MHz Crystal
XO24
O
C
-
24.576 MHz Crystal
LOOPF
I
A
-
Capacitor for PLL
IO
Tup
2mA
I
Tup
-
5. Miscellaneous (11-pin)
Name
GPIO[2:0]
TEST#
Function
Chip select for external EEPROM
Serial clock for external EEPROM
or Hardware Volume (Up)
Serial data output for external EEPROM
or Hardware Volume (Down)
General purpose Input / Output
GPIO2 can use for a reset pin of Secondary AC’97.
LSI Test pin (Do not connect externally.)
February 3, 1999
-6-
YMF744B
6. Power Supply (22-pin)
Name
I/O
Type
Size
Function
PVDD[3:0]
-
-
-
3.3V Power supply for PCI Bus Interface
PVSS[6:0]
-
-
-
Ground for PCI Bus Interface
CVDD[2:0]
-
-
-
3.3V Power supply for Core logic
VDD[2:0]
-
-
-
3.3V Power supply
VSS[3:0]
-
-
-
Ground
LVDD
-
-
-
3.3V Power supply for PLL Filter
I/O
Type
Size
RESERVE0
O
Pod
-
RESERVE[3:2]
I
Tup
-
RESERVE[16:8,1]
-
-
-
7. Reserve Pin (13-pin)
Name
Function
Reserve pins (Do not connect externally.)
TYPE
T : TTL
A : Analog
Ptr : Tri-State PCI
Ttr : Tri-State TTL
C : CMOS
Pstr : Sustained Tri-Sate PCI
Tup : Pull up (Max. 300kohm) TTL
P : PCI
Pod : Open Drain PCI
February 3, 1999
-7-
YMF744B
EEPROM I/F
SPDIF Input
GPIO
ZV Port
PCI Side Band
PC/PCI
S-IRQ
Selector
BLOCK DIAGRAM
SPDIF
Output
Legacy Audio
FM Synthesizer
SB Pro
D-DMA Engine
PCI
Interface
SRC
Sampling
Converter
MPU401
Joystick
Audio
Function
Config
Register
AC-Link
Interface
Revision2.1
PCI Bus Master
DMA Controller
PCI Native Audio
XG Synthesizer
DirectSound Acc.
Wave In/Out
February 3, 1999
-8-
YMF744B
FUNCTION OVERVIEW
1. PCI INTERFACE
DS-1S supports the PCI bus interface and complies to PCI revision 2.2.
1-1. PCI Bus Command
DS-1S supports the following PCI Bus commands.
1-1-1. Target Device Mode
C/BE[3:0]#
Command
0
0
0
0
Interrupt Acknowledge (not support)
0
0
0
1
Special Cycle (not support)
0
0
1
0
I/O Read
0
0
1
1
I/O Write
0
1
0
0
reserved
0
1
0
1
reserved
0
1
1
0
Memory Read
0
1
1
1
Memory Write
1
0
0
0
reserved
1
0
0
1
reserved
1
0
1
0
Configuration Read
1
0
1
1
Configuration Write
1
1
0
0
Memory Read Multiple (not support)
1
1
0
1
Dual Address Cycle (not support)
1
1
1
0
Memory Read Line (not support)
1
1
1
1
Memory Write and Invalidate (not support)
DS-1S does not assert DEVSEL# when accessed with commands that are indicated as (not supported) or
reserved.
1-1-2. Master Device Mode
C/BE[3:0]#
Command
0
1
1
0
Memory Read
0
1
1
1
Memory Write
When DS-1S becomes a Master Device, it generates only memory write and read cycle commands.
February 3, 1999
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YMF744B
1-2. PCI Configuration Register
In addition to the Configuration Register defined by PCI Revision 2.2, DS-1S provides proprietary PCI
Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro,
MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software
from YAMAHA Corporation.
The following shows the overview of the PCI Configuration Register.
Offset
b[31..24]
b[23..16]
b[15..8]
b[7..0]
00-03h
Device ID
Vendor ID
04-07h
Status
Command
08-0Bh
Base Class Code
Sub Class Code
Programming IF
Revision ID
0C-0Fh
Reserved
Header Type
Latency Timer
Reserved
10-13h
PCI Audio Memory Base Address
14-17h
Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA)
18-1Bh
Legacy Audio I/O Base Address (Dummy for Joystick)
1C-2Bh
Reserved
2C-2Fh
Subsystem ID
Subsystem Vendor ID
30-33h
Reserved
34-37h
Reserved
38-3Bh
3C-3Fh
Cap Pointer
Reserved
Maximum Latency
Minimum Grant
Interrupt Pin
Interrupt Line
40-43h
Extended Legacy Audio Control
Legacy Audio Control
44-47h
Subsystem ID Write
Subsystem Vendor ID Write
48-4Bh
DS-1S Power Control 1
DS-1S Control
4C-4Fh
DS-1S Power Control 2
D-DMA Slave Configuration
50-53h
Power Management Capabilities
54-57h
Reserved
Power Management Control / Status
58-5Bh
DS-1S Secondary AC’97 Power Control
ACPI Mode
5C-5Fh
Next Item Pointer
Capability ID
Reserved
60-63h
Sound Blaster Base Address
FM Synthesizer Base Address
64-67h
Joystick Base Address
MPU401 Base Address
68-FFh
Reserved
Reserved
registers are hardwired to “0”.
All data written to these registers are discarded.
The values
read from these registers are all zero.
DS-1S can be accessed by using any bus width, 8-bit, 16-bit or 32-bit.
February 3, 1999
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YMF744B
00-01h: Vendor ID
Read Only
Default: 1073h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Vendor ID
b[15:0] ........Vendor ID
This register contains the YAMAHA Vendor ID registered in Revision 2.2.
This register is hardwired to
1073h.
02-03h: Device ID
Read Only
Default: 0010h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Device ID
b[15:0] ........Device ID
This register contains the Device ID of DS-1S.
This register is hardwired to 0010h.
04-05h: Command
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
-
-
-
-
-
-
-
SER
-
PER
-
-
-
BME
MS
IOS
b0................IOS: I/O Space
This bit is a dummy one that is capable of writing.
This bit indicates for BIOS or OS that DS-1S
includes I/O devices.
b1................MS: Memory Space
This bit enables DS-1S to response to Memory Space Access.
“0”: DS-1S ignores Memory Space Access.
(default)
“1”: DS-1S responds to Memory Space Access.
b2................BME: Bus Master Enable
This bit enables DS-1S to act as a master device on the PCI bus.
“0”: Do not set DS-1S to be the master device.
(default)
“1”: Set DS-1S to be the master device.
February 3, 1999
-11-
YMF744B
b6................PER: Parity Error Response
This bit enables DS-1S responses to Parity Error.
“0”: DS-1S ignores all parity errors.
“1”: DS-1S performs error operation when DS-1S detects a parity error.
b8................SER: SERR# Enable
This bit enables DS-1S to drive SERR#.
“0”: Do not drive SERR#.
(default)
“1”: Drives SERR# when DS-1S detects an Address Parity Error on normal target cycle or a Data Parity
Error on special cycle.
06-07h: Status
Read / Write Clear
Default: 0210h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
DPE
SSE
RMA
RTA
STA
b10
b9
DEVT
b4................CAP: Capability
b8
b7
b6
b5
b4
b3
b2
b1
b0
DPD
-
-
-
CAP
-
-
-
-
(Read Only)
This bit indicates that DS-1S supports the capability register.
This bit is read only.
When 58-59h :
ACPI Mode register, ACPI bit is “0”, the bit is “1”. When ACPI bit is “1”, the bit is “0”.
b8................DPD: Data Parity Error Detected
This bit indicates that DS-1S detects a Data Parity Error during a PCI master cycle.
b[10:9] ........DEVT: DEVSEL Timing
This bit indicates that the decoding speed of DS-1S is Medium.
b11..............STA: Signaled Target Abort
This bit indicates that DS-1S terminates a transaction with Target Abort during a target cycle.
b12..............RTA: Received Target Abort
This bit indicates that a transaction is terminated with Target Abort while DS-1S is in the master memory
cycle.
b13..............RMA: Received Master Abort
This bit indicates that a transaction is terminated with Master Abort while DS-1S is in the master memory
cycle.
b14..............SSE: Signaled System Error
This bit indicates that DS-1S asserts SERR#.
b15..............DPE: Detected Parity Error
This bit indicates that DS-1S detects Address Parity Error or Data Parity Error during a transaction.
February 3, 1999
-12-
YMF744B
08h: Revision ID
Read Only
Default: 02h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Revision ID
b[7:0] ..........Revision ID
This register contains the revision number of DS-1S.
This register is hardwired to 02h.
09h: Programming Interface
Read Only
Default: 00h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Programming Interface
b[7:0] ..........Programming Interface
This register indicates the programming interface of DS-1S.
This register is hardwired to 00h.
0Ah: Sub-class Code
Read Only
Default: 01h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Sub-class Code
b[7:0] ..........Sub-class Code
This register indicates the sub-class of DS-1S.
This register is hardwired to 01h.
DS-1S belongs to the
Audio Sub-class.
0Bh: Base Class Code
Read Only
Default: 04h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Base Class Code
b[7:0] ..........Base Class Code
This register indicates the base class of DS-1S.
This register is hardwired to 04h.
DS-1S belongs to
the Multimedia Base Class.
February 3, 1999
-13-
YMF744B
0Dh: Latency Timer
Read / Write
Default: 00h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Latency Timer
b[7:0] ..........Latency Timer
When DS-1S becomes a Bus Master device, this register indicates the initial value of the Master Latency
Timer.
0Eh: Header Type
Read Only
Default: 00h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Header Type
b[7:0] ..........Header Type
This register indicates the device type of DS-1S.
This is hardwired to 00h.
10-13h: PCI Audio Memory Base Address
Read / Write
Default: 00000000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
MBA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
MBA (higher)
b[31:15] ......MBA: Memory Base Address
This register indicates the physical Memory Base address of the PCI Audio registers in DS-1S.
address can be located anywhere in the 32-bit address space.
The base
Data in the DS-1S register is not
prefetchable.
Size of the register to be mapped into the memory space is 32,768 bytes.
February 3, 1999
-14-
YMF744B
14-17h: Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA)
Read / Write
Default: 00000001h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
IOBASE0
b5
b4
b3
b2
b1
b0
-
-
-
-
-
I/O
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
b0................IO
(Read Only)
This bit indicates that the base address is assigned to I/O. This bit is hardwired to “1”.
b[15:6] ........IOBASE0
This register is used so that the OS may secure I/O resources for Sound Blaster Pro, FM Synthesizer,
MPU401 and D-DMA controller.
Because this register is a dummy one, each for the I/O addresses of
the above blocks is assigned with the I/O addresses set to 4C-4Dh and 60-65h respectively by the software
driver.
18-1Bh: Legacy Audio I/O Base Address (Dummy for Joystick)
Read / Write
Default: 00000001h
Access Bus Width: 8, 16, 32-bit
b15
B14
b13
b12
b11
b10
b9
b31
B30
b29
b28
b27
b26
b25
-
-
-
-
-
-
-
b8
b7
b6
b5
b4
b3
b2
b1
-
I/O
b24
b23
b22
b21
b20
b19
b18
b17
b16
-
-
-
-
-
-
-
-
-
IOBASE1
b0................IO
(Read Only)
This bit indicates that the base address is assigned to I/O. This bit is hardwired to “1”.
b[15:2] ........IOBASE1
This register is used so that the OS may secure I/O resource for the joystick port.
Because this register is
a dummy one, the joystick I/O address is assigned with the I/O address set to 66-67h by the software
driver.
February 3, 1999
-15-
b0
YMF744B
2C-2Dh: Subsystem Vendor ID
Read Only
Default: 1073h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Subsystem Vendor ID
b[15:0] ........Subsystem Vendor ID
This register contains the Subsystem Vendor ID.
In general, this ID is used to distinguish adapters or
systems made by different IHVs using the same chip by the same vendor.
This register is read only.
write the IHV’s Vendor ID, use 44-45h (Subsystem Vendor ID Write Register).
To
IHVs must change this
ID to their Vendor ID in the BIOS POST routine.
In case of the system such as Sound Card which BIOS can not control, this ID can be changed by
connecting EEPROM externally.
Then, Subsystem Vendor ID Write Register is invalid.
In case EEPROM is not externally, the default value is the YAMAHA's Vendor ID, 1073h.
2E-2Fh: Subsystem ID
Read Only
Default: 0010h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
Subsystem ID
b[15:0] ........Subsystem ID
This register contains the Subsystem ID.
In general, this ID is used to distinguish adapters or systems
made by different IHVs using the same chip by the same vendor.
This register is read only.
To write
the IHV's Device ID, use 46-47h (Subsystem ID Write Register).
IHVs must change this ID to their ID
in the BIOS POST routine.
In case of the system such as Sound Card which BIOS can not control, this ID can be changed by
connecting EEPROM externally.
Then, Subsystem ID Write Register is invalid.
In case EEPROM is not externally, the default value is the YAMAHA's Device ID, 0010h.
February 3, 1999
-16-
b0
YMF744B
34h: Capability Register Pointer
Read Only
Default: 50h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Capability Register Pointer
b[7:0] ..........Capability Register Pointer
This register indicates the offset address of the Capabilities register in the PCI Configuration register
when 58-59h: ACPI Mode register, ACPI bit is “0”.
registers as the capabilities.
DS-1S provides PCI Bus Power Management
The Power Management registers are mapped to 50h - 57h in the PCI
Configuration register, and this register indicates “50h”.
When ACPI bit is “1”, this register indicates “00h”.
3Ch: Interrupt Line
Read / Write
Default: 00h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Interrupt Line
b[7:0] ..........Interrupt Line
This register indicates the interrupt channel that INTA# is assigned to.
3Dh: Interrupt Pin
Read Only
Default: 01h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Interrupt Pin
b[7:0] ..........Interrupt Pin
DS-1S supports INTA# only.
This register is hardwired to 01h.
3Eh: Minimum Grant
Read Only
Default: 05h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Minimum Grant
b[7:0] ..........Minimum Grant
This register indicates the length of the burst period required by DS-1S.
This register is hardwired to 05h.
February 3, 1999
-17-
YMF744B
3Fh: Maximum Latency
Read Only
Default: 19h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Maximum Latency
b[7:0] ..........Maximum Latency
This register indicates how often DS-1S generates the Bus Master Request.
This register is hardwired to 19h.
40-41h: Legacy Audio Control
Read / Write
Default: 907Fh
Access Bus Width: 8, 16, 32-bit
b15
b14
LAD
SIEN
b13
b12
b11
b10
MPUIRQ
b9
b8
b7
SBIRQ
b6
SDMA
b5
b4
I/O
MIEN
b3
b2
b1
MEN GPEN FMEN SBEN
b0................SBEN: Sound Blaster Enable
This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits,
when LAD is set to “0”.
The FM Synthesizer registers can be accessed via SB I/O space, while the SB
block is enabled, even if FMEN is set to “0”.
“0”: Disable the mapping of the SB block to the I/O space
“1”: Enable the mapping of the SB block to the I/O space
(default)
b1................FMEN: FM Synthesizer Enable
This bit enables the mapping of the FM Synthesizer block in the I/O space specified by the FMIO bits,
when LAD is set to “0”.
FM Synthesizer registers can be accessed via SB I/O space, while the SB block
is enabled, even if FMEN is set to “0”.
“0”: Disable the mapping of the FM Synthesizer block to the FMIO space
“1”: Enable the mapping of the FM Synthesizer block to the FMIO space
(default)
After setting FMEN to “1”, about 100 msec is necessary before accessing these I/O space.
b2................GPEN: Gameport Enable
This bit enables the mapping of the Joystick block in the I/O space specified by the JSIO bits, when LAD
is set to “0”.
“0”: Disable the mapping of the Joystick block
“1”: Enable the mapping of the Joystick block
(default)
b3................MEN: MPU401 Enable
This bit enables the mapping of the MPU401 block in the I/O space specified by the MPUIO bits, when
LAD is set to “0”.
“0”: Disable the mapping of the MPU401 block
“1”: Enable the mapping of the MPU401 block
(default)
February 3, 1999
-18-
b0
YMF744B
b4................MIEN: MPU401 IRQ Enable
This bit enables the interrupt service of MPU401, when LAD is set to “0” and MEN is set to “1”.
MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin.
“0”: The MPU401 block can not use the interrupt service.
“1”: The MPU401 block can use interrupt signals determined by the MPUIRQ bits.
(default)
b5................I/O: I/O Address Aliasing Control
This bit selects the number of bits to decode for the I/O address of each block.
“0”: 16-bit address decode
“1”: 10-bit address decode
(default)
b[7:6] ..........SDMA: Sound Blaster DMA-8 Channel Select
These bits select the DMA channel for the Sound Blaster Pro block.
“0”:
DMA ch0
“1”:
DMA ch1
“2”:
reserved
“3”:
DMA ch3
(default)
b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select
These bits select the interrupt channel for the Sound Blaster Pro block.
“0”:
IRQ5
“1”:
IRQ7
“2”:
IRQ9
“3”:
IRQ10
“4”:
IRQ11
“5” - “7”:
reserved.
(default)
b[13:11] ......MPUIRQ: MPU401 IRQ Channel Select
When MIEN is set to “1”, these bits select the interrupt channel for the MPU401 block.
“0”:
IRQ5
“1”:
IRQ7
“2”:
IRQ9
“3”:
IRQ10
“4”:
IRQ11
“5” - “7”:
reserved
(default)
Same interrupt channels can be assigned to SBIRQ and MPUIRQ.
February 3, 1999
-19-
YMF744B
b14..............SIEN: Serialized IRQ enable
DS-1S supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and
Serialized IRQ.
The interrupt protocol is selected with IMOD and SIEN as follows.
The interrupt channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ,.
Only one
protocol can be used at once.
SIEN
IMOD
Interrupt protocol
0
0
Legacy interrupt (IRQs)
0
1
PCI interrupt (INTA#)
1
*
Serialized IRQ
(default)
b15..............LAD: Legacy Audio Disable
This bit disables the Legacy Audio block.
“0”: Enables the Legacy Audio block
“1”: Disables the Legacy Audio block
(default)
When this bit is set to “1”, DS-1S does not respond to the I/O Target transaction for legacy I/O address on
the PCI bus.
42-43h: Extended Legacy Audio Control
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
IMOD
b14
b13
b12
SBVER
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
-
-
MAIM
-
-
-
-
-
-
-
-
SMOD
b8................MAIM: MPU401 Acknowledge Interrupt Mask
This bit determine whether interrupt is asserted when the acknowledge, which is occurred by changing
MPU401 mode form default to UART, is returned.
“0”: Interrupt is asserted when the acknowledge is returned.
(default)
“1”: Interrupt is masked when the acknowledge is returned.
b[12:11] ......SMOD: SB DMA mode
These bits determine the protocol to achieve the DMAC(8237) function on the PCI bus.
“0”:
PC/PCI
“1”:
reserved
“2”:
Distributed DMA
“3”
reserved
(default)
February 3, 1999
-20-
YMF744B
b[14:13] ......SBVER: SB Version Select
These bits set the version of the SB Pro DSP.
The value set in these bits is returned by sending the E1h
DSP command.
“0”:
ver 3.01
“1”:
ver 2.01
“2”:
ver 1.05
“3”:
reserved
(default)
b15..............IMOD: Legacy IRQ mode
The legacy interrupt protocol is selected with IMOD and SIEN.
Refer to the explanation of SIEN bit.
44-45h: Subsystem Vendor ID Write Register
Read / Write
Default: 1073h
Access Bus Width: 16-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Subsystem Vendor ID Write
b[15:0] ........Subsystem Vendor ID Write Register
This register sets the Subsystem Vendor ID that is read from 2C-2Dh (Subsystem Vendor ID register).
The default value is the YAMAHA Vendor ID, 1073h.
IHVs must change this ID to their Vendor ID in
the BIOS POST routine.
In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem Vendor ID.
46-47h: Subsystem ID Write Register
Read / Write
Default: 0010h
Access Bus Width: 16-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
Subsystem ID Write
b[15:0] ........Subsystem ID Write Register
This register sets the Subsystem ID that is read from 2E-2Fh (Subsystem ID register).
The default value is the DS-1S Device ID, 0010h.
IHVs must change this ID to their ID in the BIOS
POST routine.
In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem ID.
February 3, 1999
-21-
b0
YMF744B
48-49h: DS-1S Control
Read / Write
Default: 0001h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
-
-
-
-
-
-
-
-
-
-
-
-
b3
b2
ACLS WRST
B1
b0
-
CRST
b0................CRST: AC’97 Software Reset Signal Control
This bit controls the CRST# signal.
“0”: Inactive (CRST#=High)
“1”: Active (CRST#=Low)
(default)
b2................WRST: AC’97 Warm Reset
This bit places the AC’97 in warm reset condition when the BIT_CLK signal on the AC’97 remains in
inactive state.
If this bit is set to “1”, it will automatically return to “0” after 1.3µs time duration.
bit is valid only while the ACLS bit is set to “0”.
This
Except in this case, even if this bit is attempted to be
set to “1”, no warm reset will be generated (write operation of “1” remains disabled).
“0”: Normal
(default)
“1”: AC’97 Warm Reset
b3................ACLS: AC-Link Status
(Read Only)
This bit indicates whether or not the AC-link is active.
active state (the BIT_CLK signal is active).
This bit is “1” when the AC-link remains in
This bit is “0” during the following conditions:
- When the CRST# pin is active (CRST#=Low)
- When either the PR4 bit or PR5 bit of 4A-4Bh: DS-1S Power Control 1 register is set to “1”
“0”: AC’97 Inactive
(default)
“1”: AC’97 Active
February 3, 1999
-22-
YMF744B
4A-4Bh: DS-1S Power Control 1
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
-
JSR
-
-
-
DPLL
-
DMC
b0................DMC: Disable Master Clock Oscillation
Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz).
“0”: Normal
(default)
“1”: Disable
b2................DPLL: Disable PLL Clock Oscillation
Setting this bit to “1” disables the oscillation of PLL.
“0”: Normal
(default)
“1”: Disable
b6................JSR: Joystick Reset
This bit controls reset of the flip-flop circuit following the analog comparator stage on the joystick port.
The Initial value is set to “0” immediately after power on reset or hardware reset.
“0”: Normal
(default)
“1”: Resets the flip-flop circuit following the analog comparator stage on the joystick port
b8................PR0: AC’97 Power Down Control 0
This bit controls the power state of the ADC and Input Mux in the Primary AC’97.
“0”: Normal
(default)
“1”: Power down
b9................PR1: AC’97 Power Down Control 1
This bit controls the power state of the DAC in the Primary AC’97.
“0”: Normal
(default)
“1”: Power down
b10..............PR2: AC’97 Power Down Control 2
This bit controls the power state of the Analog Mixer (Vref still on) in the Primary AC’97.
This power
state retains the Reference Voltage of the AC’97.
“0”: Normal
(default)
“1”: Power down
b11..............PR3: AC’97 Power Down Control 3
This bit controls the power state of the Analog Mixer (Vref off) in the Primary AC’97.
This power
state removes Reference Voltage of the AC’97.
“0”: Normal
(default)
“1”: Power down
February 3, 1999
-23-
YMF744B
b12..............PR4: AC’97 Power Down Control 4
This bit controls the power state of the AC-link in the Primary AC’97.
“0”: Normal
(default)
“1”: Power down
b13..............PR5: AC’97 Power Down Control 5
Setting this bit to “1” disables the internal clock of the Primary AC’97.
DS-1S, the master clock is supplied from DS-1S.
In case the AC’97 is used with
Therefore, when the clock is stopped completely, set
PR5 bits to “1” firstly, then the CMCD bit should be set to “1” after duration of 20µs or longer.
“0”: Normal
(default)
“1”: Disable
b14..............PR6: AC’97 Power Down Control 6
This bit controls PR6 bit status of the power control register in the Primary AC’97.
b15..............PR7: AC’97 Power Down Control 7
This bit controls PR7 bit status of the power control register in the Primary AC’97.
Respective data set to b[15:8] are correspondingly set into the “Power down Control/Status” register in the
Primary AC’97 via the AC-Link. These are not set into the power down register in the Secondary AC’97.
4C-4Dh: D-DMA Slave Configuration
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
Base Address
b4
b3
EA
b2
b1
TS
b0................CE: Channel Enable
This bit enables the Distributed DMA function.
“0”: Disable Distributed DMA
(default)
“1”: Enable Distributed DMA
b[2:1] ..........TS: Transfer Size
These bits indicate the size of the DMA transfer. Since DS-1S supports only 8-bit DMA transfer, the bits
are hardwired to 00b.
b3................EA: Extended Address
DS-1S does not support extended address mode.
This bit is hardwired to 0b.
b[15:4] ........Base Address : D-DMA Slave Base Address
These bits indicate the D-DMA slave base address.
February 3, 1999
-24-
b0
CE
YMF744B
4E-4Fh: DS-1S Power Control 2
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
-
-
-
PSHWV
PSIO
b10
b9
PSACL PSDIR
b8
b7
PSDIT
PSZV
b6
b5
b4
b3
b2
PSSRC PSPCA PSJOY PSMPU PSSB
b1
b0
PSFM
CMCD
b0................CMCD: CODEC Master Clock Disable
Setting this bit to “1” disables the oscillation of the CMCLK.
To stop a clock, when the CMCLK is
supplied to the AC’97, it is required that b13:PR5 bit of 4A-4Bh register is set to “1”.
(If the Secondary
AC’97 is used, it is also necessary that b5:SPR5 bit of 5A-5Bh register is set to “1”.)
“0”: Normal
(default)
“1”: Disable
b1................PSFM: Power Save FM Synthesizer
Setting this bit to “1” stops a clock supplied to the FM synthesizer block.
“0”: Normal
(default)
“1”: Disable
b2................PSSB: Power Save Sound Blaster
Setting this bit to “1” stops a clock supplied to the Sound Blaster block.
“0”: Normal
(default)
“1”: Disable
b3................PSMPU: Power Save MPU401
Setting this bit to “1” stops a clock supplied to the MPU401 block.
“0”: Normal
(default)
“1”: Disable
b4................PSJOY: Power Save Joystick
Setting this bit to “1” disables the comparator of the Joystick block.
“0”: Normal
(default)
“1”: Disable
b5................PSPCA: Power Save PCI Audio
Setting this bit to “1” stops a clock supplied to the PCI Audio block.
“0”: Normal
(default)
“1”: Disable
b6................PSSRC: Power Save SRC
Setting this bit to “1” stops a clock supplied to the SRC block.
“0”: Normal
(default)
“1”: Disable
February 3, 1999
-25-
YMF744B
b7................PSZV: Power Save Zoomed Video port
Setting this bit to “1” stops a clock supplied to the Zoomed Video port block.
“0”: Normal
(default)
“1”: Disable
b8................PSDIT: Power Save Digital Audio Interface Transmitter
Setting this bit to “1” stops a clock supplied to the DIT block.
“0”: Normal
(default)
“1”: Disable
b9................PSDIR: Power Save Digital Audio Interface Receiver
Setting this bit to “1” stops a clock supplied to the DIR block.
“0”: Normal
(default)
“1”: Disable
b10..............PSACL: Power Save AC-Link
Setting this bit to “1” stops a clock supplied to the AC-Link block.
“0”: Normal
(default)
“1”: Disable
b11..............PSIO: Power Save I/O Pad
Setting this bit to “1” fixes the levels of the I/O pins except for the PCI interface and AC-Link. Output
pins retain current level, and any signals from input pins are ignored.
“0”: Normal
(default)
“1”: Fix the level of the I/O pad
b12..............PSHWV: Power Save Hardware Volume
Setting this bit to “1” stops a clock supplied to the Hardware Volume block.
“0”: Normal
(default)
“1”: Disable
February 3, 1999
-26-
YMF744B
CMCD
PSFM
PSSB
PSMPU
PSJOY
PSPCA
Master
Clock
(24.576MHz)
PLL
PSSRC
PSZV
DPLL
DMC
PSDIT
PSDIR
PSHWV
PSACL
AC97 Master Clock
FM Synthesizer
SB Pro
MPU401
Joystick
PCI Audio
SRC
ZVport
SPDIF out
SPDIF in
H/W Vol.
AC-link
PCI I/F
PC/PCI
S-IRQ
EEPROM I/F
PCI
Clock
(33MHz)
PSIO
External Input
I/O Pad
Power Management Block
50h: Capability ID
Read Only
Default: 01h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Capability ID
b[7:0] ..........Capability ID: Capability Identifier
This register indicates that the new capability register is for Power Management control.
This register is
hardwired to 01h.
February 3, 1999
-27-
YMF744B
51h: Next Item Pointer
Read Only
Default: 00h
Access Bus Width: 8, 16, 32-bit
b7
b6
b5
b4
b3
b2
b1
b0
Next Item Pointer
b[7:0] ..........Next Item Pointer
DS-1S does not provide other new capability besides Power Management.
This register is hardwired to
00h.
52-53h: Power Management Capabilities
Read Only
Default: 0401h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
-
-
-
-
-
D2S
-
-
-
-
-
-
-
b2
b1
b0
Version
b[2:0] ..........Version
These bits contain the revision number of the Power Management Interface Specification.
They are
hardwired to 001b.
b10..............D2S: D2 Support
This bit indicates that DS-1S support “D2” of the power state.
It is hardwired to “1”.
54-55h: Power Management Control / Status
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
b1
b0
PS
b[1:0] ..........PS: Power State
These bits determine the power state of DS-1S.
“0”:
D0
“1”:
D1
“2”:
D2
“3”:
D3hot
DS-1S supports the following power states:
(not supported)
When the power state is changed from D3hot to D0, DS-1S resets the PCI Configuration register 00-3Fh.
DS-1S transits to D0 Uninitialized state.
Though the power state of this register is changed, the power consumption of DS-1S is not changed.
To
support low power, Windows driver controls DS-1S Power Control Register.
DS-1S can support the power state of D0, D1, D2 and D3 with ACPI.
In this case, set ACPI bit (58-59h:
ACPI Mode Register) to “1” to disable Capabilities of PCI Bus Power Management.
February 3, 1999
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YMF744B
58-59h: ACPI Mode
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ACPI
b0................ACPI: ACPI Mode Select
This bit select either PCI Bus Power Management or ACPI Mode for power management of DS-1S.
“0”: PCI Bus Power Management is used.
(34h) are enabled.
CAP bit (06-07h: Status Register) and Capabilities Pointer
(default)
“1”: ACPI Mode is used.
CAP bit and Capabilities Pointer are hardwired “0”, and disabled.
5A-5Bh: DS-1S Secondary AC’97 Power Control
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
-
-
-
-
-
-
-
-
b7
b6
b5
b4
b3
b2
b1
SPR7 SPR6 SPR5 SPR4 SPR3 SPR2 SPR1 SPR0
b0................SPR0: Secondary AC’97 Power Down Control 0
This bit controls the power state of the ADC and Input Mux in the Secondary AC’97.
“0”: Normal
(default)
“1”: Power down
b1................SPR1: Secondary AC’97 Power Down Control 1
This bit controls the power state of the DAC in the Secondary AC’97.
“0”: Normal
(default)
“1”: Power down
b2................SPR2: Secondary AC’97 Power Down Control 2
This bit controls the power state of the Analog Mixer (Vref still on) in the Secondary AC’97.
This
power state retains the Reference Voltage of the AC’97.
“0”: Normal
(default)
“1”: Power down
b3................SPR3: Secondary AC’97 Power Down Control 3
This bit controls the power state of the Analog Mixer (Vref off) in the Secondary AC’97.
This power
state removes Reference Voltage of the AC’97.
“0”: Normal
(default)
“1”: Power down
February 3, 1999
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b0
YMF744B
b4................SPR4: Secondary AC’97 Power Down Control 4
This bit controls the power state of the AC-link in the Secondary AC’97.
“0”: Normal
(default)
“1”: Power down
b5................SPR5: Secondary AC’97 Power Down Control 5
Setting this bit to “1” disables the internal clock of the Secondary AC’97.
DS-1S, the master clock is supplied from DS-1S.
In case the AC’97 is used with
Therefore, when the clock is stopped completely, set
SPR5 bits to “1” firstly, then the CMCD bit should be set to “1” after duration of 20µs or longer.
“0”: Normal
(default)
“1”: Disable
b6................SPR6: Secondary AC’97 Power Down Control 6
This bit controls PR6 bit status of the power control register in the Secondary AC’97.
b7................SPR7: Secondary AC’97 Power Down Control 7
This bit controls PR7 bit status of the power control register in the Secondary AC’97.
Respective data set to b[7:0] are correspondingly set into the “Power down Control/Status” register in the
Secondary AC’97 via the AC-Link. These are not set into the power down register in the Primary AC’97.
60-61h: FM Synthesizer Base Address
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
FM Synthesizer Base Address
b1
b0
-
-
b[15:2] ........FM Synthesizer Base Address
This register sets the base address of the FM synthesizer. If b5:I/O bit of 40h register is set to “1”, b[9:2]
bits are decoded by ignoring b[15:10] bits.
62-63h: Sound Blaster Base Address
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
Sound Blaster Base Address
b7
b6
b5
b4
b3
b2
b1
b0
-
-
-
-
b[15:4] ........Sound Blaster Base Address
This register sets the base address of the Sound Blaster. If b5:I/O bit of 40h register is set to “1”, b[9:4]
bits are decoded by ignoring b[15:10] bits.
February 3, 1999
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YMF744B
64-65h: MPU401 Base Address
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
MPU401 Base Address
b0
-
b[15:1] ........MPU401 Base Address
This register sets the base address of the MPU401. If b5:I/O bit of 40h register is set to “1”, b[9:1] bits are
decoded by ignoring b[15:10] bits.
66-67h: Joystick Base Address
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
Joystick Base Address
b[15:0] ........Joystick Base Address
This register sets the base address of the Joystick. If b5:I/O bit of 40h register is set to “1”, b[9:0] bits are
decoded by ignoring b[15:10] bits.
February 3, 1999
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b0
YMF744B
2. ISA Compatible Device
DS-1S contains the following functions to maintain the compatibility with the past ISA Sound Devices.
These devices are considered Legacy devices and the functions are referred to as Legacy Audio.
Legacy Audio is independent from PCI Audio and can be used simultaneously.
The configuration is set in the Legacy Audio Control Register in the PCI Configuration Register space.
Basically, these registers are configured by the BIOS.
Also, logical device IDs are assigned to the devices to support Plug and Play.
Yamaha defines the following
logical IDs.
To control the device with the BIOS, the logical device IDs must be defined in the PnP BIOS extended ROM
space.
The logical IDs are determined by how it is configured.
Logical Device ID
IDs and configuration are as follows.
Functions used (Block)
FM
YMH0100
(*)
MPU401
SB Pro (*)
O
O
O
YMH0101
Joystick
O
* The blocks pertain to the following.
FM:
Points to the FM synthesizer mapped to AdLibBase (0x0388).
SB Pro:
Points to the Voice Playback section only.
These devices are independent from each other, and can be Enabled/Disabled individually.
AdLib and Sound Blaster must be disabled to disable the internal FM Synthesizer.
However, both
Disabling just AdLib
only masks the access.
The driver by Yamaha supports only logical device ID, YMH0100.
For YMH0101, use the driver provided
by Microsoft.
February 3, 1999
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YMF744B
DS-1S supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI.
In addition, DS-
1S supports the old type of interrupts used by ISA and the Serialized IRQ protocol.
Yamaha recommends the combination of PC/PCI and Serialized IRQ.
The system block diagram when using Intel chip set is shown below.
North
Brigde
(430TX/440BX)
PCI
Address/Data
Control
PCREQ#
PCGNT#
DS-1S
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
South
Bridge
(PIIX4E)
SERIRQ#
Select either protocols
The PCI-to-ISA bridge needs to support PC/PCI.
IRQ is directly connected to the IRQ input pins on the
PCI-to-ISA bridge.
February 3, 1999
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YMF744B
2-1. FM Synthesizer Block
FM Synthesizer Block is register compatible with YMF289B.
However, Power Management register
has been deleted because it is now controlled by the PCI Configuration Register.
The following shows the FMBase I/O map of FM Synthesizer.
FMBase
(R)
Status Register port
FMBase
(W)
Address port for Register Array 0
FMBase+1
(R/W)
Data port
FMBase+2
(W)
Address port for Register Array 1
FMBase+3
(R/W)
Data port
The default FMBase value is 0x0388.
The following shows the FM Synthesizer Block registers.
2-1-1. Status Register
FM Synthesizer Status Register (RO):
Address
D7
D6
D5
D4
D3
D2
D1
D0
xxh
IRQ
FT1
FT2
-
-
BUSY
-
BUSY
February 3, 1999
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YMF744B
2-1-2. FM Synthesizer Data Register
FM Synthesizer Data Register Array 0 (R/W):
Address
D7
D6
D5
D4
D3
00-01h
LSI TEST
02h
TIMER 1
03h
TIMER 2
04h
08h
(*1)
20-35h
D2
D1
D0
RST
MT1
MT2
-
-
-
ST2
ST1
-
NTS
-
-
-
-
-
-
AM
VIB
EGT
KSR
(*2)
40-55h
MULT
KSL
TL
(*3)
AR
DR
(*4)
SL
RR
60-75h
80-95h
A0-A8h
F-NUM (L)
B0-B8h
-
-
KON
BDh
DAM
DVB
RHY
BD
*6
*6
CHR
CHL
-
-
-
-
C0-C8h
(*5)
E0-F5h
BLOCK
F-NUM (H)
SD
TOM
TC
FB
HH
CNT
-
WS
FM Synthesizer Data Register Array 1 (R/W)
Address
D7
D6
D5
D4
-
-
-
-
-
-
AM
VIB
EGT
KSR
00-01h
04h
05h
(*1)
20-35h
D3
D2
40-55h
*
NEW
CONNECTION SEL
-
*
MULT
KSL
TL
(*3)
AR
DR
(*4)
SL
RR
60-75h
80-95h
A0-A8h
F-NUM (L)
B0-B8h
-
-
KON
C0-C8h
*6
*6
CHR
CHL
-
-
-
-
E0-F5h
D0
LSI TEST
(*2)
(*5)
D1
BLOCK
F-NUM (H)
FB
-
CNT
WS
*1 : 26h, 27h, 2Eh and 2Fh do not exist.
*2 : 46h, 47h, 4Eh and 4Fh do not exist.
*3 : 66h, 67h, 6Eh and 6Fh do not exist.
*4 : 86h, 87h, 8Eh and 8Fh do not exist.
*5 : E6h, E7h, EEh and EFh do not exist.
*6 : The bits exist, but do not function.
February 3, 1999
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YMF744B
2-2. Sound Blaster Pro Block
This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro.
functions are supported (record functions are not supported).
Only playback
However, to maintain compatibility for
games, it is designed so that every DSP command receives a correct response.
The DMA transfer of this block uses PC/PCI or D-DMA protocol.
The following shows the SBBase I/O map of SB Pro.
SBBase
(R)
FM Synthesizer Status port
SBBase
(W)
FM Synthesizer Address port for Register Array 0
SBBase+1h
(R/W)
FM Synthesizer Data register
SBBase+2h
(W)
FM Synthesizer Address port for Register Array 1
SBBase+3h
(R/W)
FM Synthesizer Data port
SBBase+4h
(W)
SB Mixer Address port
SBBase+5h
(R/W)
SB Mixer Data port
SBBase+6h
(W)
SB DSP Reset port
SBBase+8h
(R)
FM Synthesizer Status port
SBBase+8h
(W)
FM Synthesizer Address port for Register Array 0
SBBase+9h
(R/W)
FM Synthesizer Data port
SBBase+Ah
(R)
DSP Read Data port
SBBase+Ch
(R)
DSP Write-buffer status port
SBBase+Ch
(W)
DSP Write Command/Data port
SBBase+Eh
(R)
DSP Read-buffer status port
February 3, 1999
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YMF744B
2-2-1. DSP Command
The following shows the list of DSP Commands that are supported by the SB Pro engine.
Both SB and
SB Pro commands are supported.
CMD Support Function
10h
14h
16h
17h
1Ch
1Fh
20h(*1)
24h(*1)
2Ch(*1)
30h
31h
34h
35h
36h(*2)
37h(*2)
38h
40h
48h
74h
75h
76h
77h
7Dh
7Fh
80h
90h
91h
98h(*1)
99h(*1)
A0h(*1)
A8h(*1)
D0h
D1h(*3)
D3h(*3)
D4h
D8h
DAh
E1h
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
8bit direct mode single byte digitized sound output
8bit single-cycle DMA mode digitized sound output
8bit to 2bit ADPCM single-cycle DMA mode digitized sound output
8bit to 2bit ADPCM single-cycle DMA mode digitized sound output with ref. byte
8bit auto-init DMA mode digitized sound output
8bit to 2bit ADPCM auto-init DMA mode digitized sound output with ref. byte
8bit direct mode single byte digitized sound input
8bit single-cycle DMA mode digitized sound input
8bit auto-init DMA mode digitized sound input
Polling mode MIDI input
Interrupt mode MIDI input
UART polling mode MIDI I/O
UART interrupt mode MIDI I/O
UART polling mode MIDI I/O with time stamping
UART interrupt mode MIDI I/O with time stamping
MIDI output
Set digitized sound transfer Time Constant
Set DSP block transfer size
8bit to 4bit ADPCM single-cycle DMA mode digitized sound output
8bit to 4bit ADPCM single-cycle DMA mode digitized sound output with ref. byte
8bit to 3bit ADPCM single-cycle DAM mode digitized sound output
8bit to 3bit ADPCM single-cycle DMA mode digitized sound output with ref. byte
8bit to 4bit ADPCM auto-init DMA mode digitized sound output with ref. byte
8bit to 3bit ADPCM auto-init DMA mode digitized sound output with ref. byte
Pause DAC for a duration
8bit high-speed auto-init DMA mode digitized sound output
8bit high-speed single-cycle DMA mode digitized sound output
8bit high-speed auto-init DMA mode digitized sound input
8bit high-speed single-cycle DMA mode digitized sound input
Set input mode to mono
Set input mode to stereo
Pause 8bit DMA mode digitized sound I/O
Turn on speaker
Turn off speaker
Continue 8bit DMA mode digitized sound I/O
Get speaker status
Exit 8bit auto-init DMA mode digitized sound I/O
Get DSP version number
Note:
(*1) The SB Block responds correctly to the commands for recording and also executes the DMA transfer.
80h is always transferred.
(*2) Only output is supported for this command.
(*3) This command only changes Speaker Status (D8h).
Undocumented commands other than the ones listed above are also supported.
February 3, 1999
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YMF744B
2-2-2. Sound Blaster Pro Mixer
The following shows the register map of the Mixer section of Sound Blaster Pro.
Address
b7
b6
b5
b4
00h
Voice Volume L
"1"
0Ah
-
-
-
"1"
0Ch
-
-
Ifilter*
"1"
0Eh
-
-
Ofilter*
"1"
22h
Master Volume L
26h
28h
2Eh
b1
b0
Voice Volume R
Remark
-
"1"
MIC Volume*
Input Source*
"1"
-
"1"
-
St. SW
"1"
Master Volume R
MIDI Volume L
"1"
MIDI Volume R
"1"
CD Volume L*
"1"
CD Volume R*
"1"
Line Volume L*
SBPDA
-
"1"
-
F1h
F8h
b2
Reset
04h
F0h
b3
-
-
-
Line Volume R*
-
SS
SCAN
DATA
-
-
SB Pro Mixer
"1"
"1"
SM
SE
SBPDR
-
-
SBI
Suspend / Resume
IRQ Status
The registers marked with * exist, but do not function.
DS-1S does not have the circuit that corresponds to the SB Mixer.
Therefore, the volume settings on the
SB Mixer are converted to the DSP coefficients of DS-1S or to AC’97 register values.
The conversion for each case is described below.
(1) SB Mixer ® DSP
The volume of master, MIDI and Voice, are applied to this case.
When the SB register is set, a 14-bit coefficient value is determined from the following conversion table
and used as the DSP coefficient.
The attenuation value of Master Volume, MIDI, and voice are summed
together to obtain the coefficient.
These volumes cannot be controlled from PCI Audio block.
February 3, 1999
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YMF744B
(1) Volume for MIDI
MIDI Vol. (26h)
0
0
Master Vol. (22h)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
mute
mute
mute
mute
mute
mute
mute
mute
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
-26dB
mute
-52dB
-42dB
-36dB
-32dB
-30dB
-28dB
0000h
0029h
0082h
0103h
019Bh
0206h
028Ch
0335h
mute
-42dB
-32dB
-26dB
-22dB
-20dB
-18dB
-16dB
0000h
0082h
019Bh
0335h
0515h
0666h
080Eh
0A24h
mute
-36dB
-26dB
-20dB
-16dB
-14dB
-12dB
-10dB
0000h
0103h
0335h
0666h
0A24h
0CC5h
1013h
143Dh
mute
-32dB
-22dB
-16dB
-12dB
-10dB
-8dB
-6dB
0000h
019Bh
0515h
0A24h
1013h
143Dh
197Ah
2013h
mute
-30dB
-20dB
-14dB
-10dB
-8dB
-6dB
-4dB
2861h
0000h
0206h
0666h
0CC5h
143Dh
197Ah
2013h
mute
-28dB
-18dB
-12dB
-8dB
-6dB
-4dB
-2dB
0000h
028Ch
080Eh
1013h
197Ah
2013h
2861h
32D6h
mute
-26dB
-16dB
-10dB
-6dB
-4dB
-2dB
0dB
0000h
0335h
0A24h
143Dh
2013h
2861h
32D6h
3FFFh
The default is Master = 4, MIDI = 4 (-12dB).
(2) Volume for Voice
Voice Vol. (04h)
0
Master Vol. (22h)
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
mute
mute
mute
mute
mute
mute
mute
mute
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
mute
-56dB
-46dB
-40dB
-36dB
-34dB
-32dB
-30dB
0000h
0019h
0052h
00A3h
0103h
0146h
019Bh
0206h
mute
-46dB
-36dB
-30dB
-26dB
-24dB
-22dB
-20dB
0000h
0052h
0103h
0206h
0335h
0409h
0515h
0666Eh
mute
-40dB
-30dB
-24dB
-20dB
-18dB
-16dB
-14dB
0000h
00A3h
0206h
0409h
0666h
080Eh
0A24h
0CC5h
mute
-36dB
-26dB
-20dB
-16dB
-14dB
-12dB
-10dB
143Dh
0000h
0103h
0335h
0666h
0A24h
0CC5h
1013h
mute
-34dB
-24dB
-18dB
-14dB
-12dB
-10dB
-8dB
0000h
0146h
0409h
080Eh
0CC5h
1013h
143Dh
197Ah
mute
-32dB
-22dB
-16dB
-12dB
-10dB
-8dB
-6dB
0000h
019Bh
0515h
0A24h
1013h
143Dh
197Ah
2013h
mute
-30dB
-20dB
-14dB
-10dB
-8dB
-6dB
-4dB
0000h
0206h
0666h
0CC5h
143Dh
187Ah
2013h
2861h
The default is Master = 4, Voice = 4 (-16dB).
(2) SB Mixer ® AC’97
The volume of CD, Line and MIC are applied to this case.
when these values are changed.
AC’97 volume are not updated automatically
Thus, the SB Mixer values need to be written to the AC’97 register with
the software.
February 3, 1999
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YMF744B
2-2-3. SB Suspend / Resume
The SB block can read the internal state as to support Suspend and Resume functions.
is made up of 268 flip flops.
The internal state
To read the state, these states are shifted in order and read 8 bits at a time
from the SCAN DATA register.
These registers are mapped to the SB Mixer space (see SB Mixer Register map).
The registers have the
following functions.
F0h: Scan In/ Out Control
Read / Write
Default: 00h
b7
b6
b5
b4
b3
b2
b1
b0
SBPDA
-
-
-
SS
SM
SE
SBPDR
b0................SBPDR: Sound Blaster Power Down Request
This bit stops the internal state of the Sound Blaster block.
“0”: Normal
(default)
“1”: Stop
b1................SE: Scan Enable
This bit Shifts the internal state by 1 bit.
Setting a “1” followed by a “0” shifts the internal state.
b2................SM: Scan Mode
This bit sets whether to read or write the state.
“0”: Write
(default)
“1”: Read
b3................SS: Scan Select
This bit gives permission to read or write the internal data to the SCAN DATA register.
“0”: Normal operation (Do not allow read or write).
(default)
“1”: Allow read and write.
b7................SBPDA: Sound Blaster Power Down Acknowledgement
This bit indicates that the SB Block is ready to read or write to the internal state after setting SBPDR.
This bit is read only.
“0”: Read/Write not possible
“1”: Read/ Write possible
February 3, 1999
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YMF744B
F1h: Scan In/ Out Data
Read / Write
Default: 00h
b7
b6
b5
b4
b3
b2
b1
b0
SCAN DATA
b[7:0] ..........SCAN DATA
This is the data port for reading and writing the internal state.
F2h: Current FM Synthesizer Index
Read Only
Default: 00h
b7
b6
b5
b4
b3
b2
b1
b0
Current FM Synthesizer Index
b[7:0] ..........Current FM Synthesizer Index
This register indicates current index of the FM Synthesizer.
F3h: Current FM Synthesizer Array
Read Only
Default: 00h
b7
B6
b5
b4
b3
b2
b1
b0
-
-
-
-
-
-
-
CFA
b0................CFA: Current FM Synthesizer Arary
This bit indicates that the FM Synthesizer array is being currently set to Array 0 or 1.
“0”: Array 0
(default)
“1”: Array 1
F4h: FM Synthesizer / MPU401 Status
Read Only
Default: 80h
b7
b6
FFEMP FFFUL
b5
b4
b3
b2
b1
b0
-
-
-
-
-
MPUS
b0................MPUS: MPU401 Status
This bit indicates current MPU401 status.
“0”: Default mode (Intelligent mode)
(default)
“1”: UART mode
b6................FFFUL: FM Synthesizer FIFO Full
This bit indicates whether or not FIFO followed by the FM Synthesizer is full.
“0”: not Full
(default)
“1”: Full
February 3, 1999
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YMF744B
b7................FFEMP: FM Synthesizer Empty
This bit indicates whether or not FIFO followed by the FM Synthesizer is empty.
“0”: not Empty
“1”: Empty
(default)
i) Scan Out
ii) Scan In
SBPDA=0
SBPDR=1
SBPDA=1
: not ready for scanning
internal state data
:
inhibit further DMA,
internal state shutdown
: ready for scanning
internal state data
SBPDA=0
: not ready for scanning
internal state data
SBPDR=1
: inhibit further DMA,
internal state shutdown
SBPDA=1
: ready for scanning
internal state data
internal state write in
SM=1
: internal state read out
SM=0
:
SS=1
: reading internal state
SS=1
: writing internal state
SE=1 -> 0
: shifting internal state
scan data out 1-bit at a time
Scan Data (Write)
SE=1 -> 0
8 times
internal state
scan data in
:
shifting internal state
scan data in 1-bit at a time
:
8 times
N times
N times
Scan Data (Read)
: internal state
scan data out
SM=0
Suspend Preparation
SS=0
SBPDR=0
Resume Completion
N = 34 byte (Total Scan Data = 268 bit (33 byte x 8 + 4 bit))
February 3, 1999
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YMF744B
2-2-4. SB IRQ Status
F8h: Interrupt Flag Register
Read Only
Default: 00h
b7
b6
b5
b4
b3
b2
b1
b0
-
-
-
-
-
-
-
SBI
b0................SBI: SB Interrupt Flag
This bit indicates that the SB DSP occurs the interrupt.
read port to clearing the interrupt and this bit.
This bit is read only.
Thus, read the SB DSP
Then, the value of the read port is invalid.
2-3. MPU401
This block is for transmitting and receiving MIDI data.
It is compatible with UART mode of “MPU401”.
Full duplex operation is possible using the 16-byte FIFO for each direction, transmitting and receiving.
The following shows the MPUBase I/O map for MPU401.
MPUBase
(R/W)
MIDI Data port
MPUBase + 1h
(R)
Status Register port
MPUBase + 1h
(W)
Command Register port
port
D7
D6
D5
D4
D3
+0h
Data
+1h (W)
Command
+1h (R)
/DSR
D2
D1
D0
/DRR
-
-
-
-
-
-
2-4. Joystick
JSBase
(R/W)
port
D7
D6
D5
D4
D3
D2
D1
D0
+0h
JBB2
JBB1
JAB2
JAB1
JBCY
JBCX
JACY
JACX
JACX...
Joystick A, Coordinate X
JACY...
Joystick A, Coordinate Y
JBCX...
Joystick B, Coordinate X
JBCY...
Joystick B, Coordinate Y
JAB1...
Joystick A, Button 1
JAB2...
Joystick A, Button 2
JBB1...
Joystick B, Button 1
JBB2...
Joystick B, Button 2
February 3, 1999
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YMF744B
3. DMA Emulation Protocol
The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA
DMAC) on the system to transfer the sound data from/to the host.
For DS-1S, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of
the Legacy Audio Block.
Because signals to connect to the ISA DMAC are generally not available on the PCI bus, there are two ways
proposed from the industry to emulate the ISA DMAC on the PCI bus. One is PC/PCI and the other is DDMA.
DS-1S supports both protocols for transferring SB Pro sound data on the PCI bus.
3-1. PC/PCI
DS-1S provides two signals, PCREQ# and PCGNT# to realize the PC/PCI.
shown below.
The format of the signals is
DS-1S asserts PCREQ# and sets PCREQ# to “HIGH” using the PCICLK corresponding to
the DMA channel it is going to use.
In addition, DS-1S determines whether the next PCI I/O cycle is its own from the channel information that is
encoded in PCGNT#.
0ns
100ns
200ns
300ns
400ns
PCICLK
REQ#
start
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GNT#
start
bit0
bit1
bit2
PCGNT# is encoded as follows.
bit2
0
0
0
0
1
1
1
1
bit1
0
0
1
1
0
0
1
1
GNT# Encoding
bit0 GNT# Bits
DMA Channel 0
0
DMA Channel 1
1
DMA Channel 2
0
DMA Channel 3
1
Reserved
0
DMA Channel 5
1
DMA Channel 6
0
DMA Channel 7
1
DS-1S supports only 8-bit DMA channels (DMA Channel 0-3).
It also only supports Single DMA transfer.
February 3, 1999
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YMF744B
3-2. D-DMA
DS-1S provides the following registers to support D-DMA.
D-DMA Slave Configuration Register (4C-
4Dh) of the PCI Configuration register is used to set the Base address of the Slave Address.
Slave Address
Base + 0h
Base + 0h
Base + 1h
Base + 1h
Base + 2h
Base + 2h
Base + 3h
Base + 3h
Base + 4h
Base + 4h
Base + 5h
Base + 5h
Base + 6h
Base + 6h
Base + 7h
Base + 8h
Base + 8h
Base + 9h
Base + Ah
Base + Bh
Base + Ch
Base + Dh
Base + Eh
Base + Fh
R/W
W
R
W
R
W
R
W
R
W
R
W
R
W
R
N/A
W
R
W
N/A
W
W
W
N/A
R/W
Register Name
Base Address 0-7
Current Address 0-7
Base Address 8-15
Current Address 8-15
Base Address 16-23
Current Address 16-23
Base Address 24-31
Current Address 24-31
Base Word Count 0-7
Current Word Count 0-7
Base Word Count 8-15
Current Word Count 8-15
Base Word Count 16-23
Current Word Count 16-23
Reserved
Command
Status
Request
Reserved
Mode
Reserved
Master Clear
Reserved
Multi-Channel Mask
These registers can be accessed by 8-bit or 16-bit bus width.
DS-1S supports 8-bit DMA transfer only.
February 3, 1999
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YMF744B
4. Interrupt Routing
DS-1S supports three types of interrupts, interrupt signal on the PCI bus (INTA#), interrupt signal on the ISA
bus (IRQ[5,7,9,10,11]), and Serialized IRQ.
The IRQs on DS-1S are routed as shown below.
PCI Audio
SIEN=0, IMOD=1
SIEN=0, IMOD=0
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
SIEN=1, IMOD=*
IRQ
Sound Blaster Pro
Select Signal
SBIRQ[2:0]
ISA IRQ
SIEN=0, IMOD=1
SIEN=0, IMOD=0
SIEN=1, IMOD=*
SERIRQ#
Selector
INTA
Selector
INTA#
IRQ
MPU401
SIEN, IMOD
SERIRQ
Select Signal
MPUIRQ[2:0]
PCI Audio can only use INTA#, but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block
can use any of the three protocols.
The protocol can be switched using 40-43h (Legacy Audio Control Register) of the PCI Configuration
Register.
4-1. Serialized IRQ
Serialized IRQ is a method to encode IRQs of 15 channels into one signal.
DS-1S provides the SERIRQ# pin to support Serialized IRQ.
Only one channel out of the 5 channels, IRQ5, IRQ7, IRQ9, IRQ10, and IRQ11, can be encoded into the
IRQ/Data frame of Serialized IRQ.
The IRQ channel is selected using 40h-43h (Legacy Audio Control Register) of the PCI Configuration
Register.
February 3, 1999
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YMF744B
5. Hardware Volume Control
The hardware volume control determines the AC’97 master volume without using any software control using
the external circuit listed below.
Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used.
Push SW
1k
VOLUP#
Push SW
1k
VOLDW#
1000p
1000p
DS-1S provides a shadow register for the AC’97 master volume.
When the software accesses the AC’97
master volume, it is always reflected in the shadow register.
Bringing the VOLUP# pin LOW level increments the left and right-channel shadow register by +1.5dB
respectively.
If either one of channel shadow registers have been already set to maximum value (00000b),
the corresponding channel shadow register remains in the same value, and the other channel shadow register
will only be incremented.
If both of channel shadow registers have been already set to maximum values,
they remain in the same values.
Bringing the VOLDW# pin LOW level decrements the left and right-channel shadow register by -1.5dB
respectively.
If either one of channel shadow registers have been already set to minimum value (11111b),
the corresponding channel shadow register remains in the same value, and the other channel shadow register
will only be decremented.
If both of channel shadow registers have been already set to minimum values,
they remain in the same values.
The master volume for the AC’97 is updated automatically via the AC-Link by setting corresponding values
to the shadow registers.
When both of the VOLUP# and VOLDW# pins are at LOW level at the same time, the MUTE bit of the
shadow register is enabled to automatically set the MUTE bit of the AC’97 master volume via the AC-Link.
When either one of the VOLUP# or VOLDW# pins is at LOW level, mute condition of the AC’97 is
deactivated via the AC-Link.
At this point of time, the master volume is set to the value before the mute.
When the AC-Link is busy (in case the register is controlled by the AC’97 Control Register), shadow register
values will be set to the AC’97 on the next frame.
At this time, BUSY is set at the AC’97 control register.
When the master volume is changed or muted depending on the logic level transition status of the VOLUP#
and VOLDW# pins, an interrupt is generated at the host.
The interrupt is used to notify the driver that the
master volume has been changed.
When the AC’97 is not connected or it is placed in power down mode, the shadow register values will remain
in the same even if the VOLDW# and VOLUP# pins are at LOW level.
February 3, 1999
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YMF744B
6. Digital Audio Interface
DS-1S supports each system of the SPDIF input/output port compliant with the IEC958 specification.
6-1. SPDIF IN
DS-1S provides the SPDIF input capability by switch-over operation of the zoomed video port.
SPDIF
input sampling frequency is 32.0kHz, 44.1kHz or 48.0kHz.
In DS-1S, sampling rate of the SPDIF signal incoming from the SPDIFIN pin is converted to 48.0kHz in the
frequency rate conversion stage in order to process all the signals at 48.0kHz frequency.
If input sampling
frequency is 48.0kHz, however, this is resampled at 96.0kHz, then decimated into 48.0kHz frequency.
The
input signal applied to the SPDIFIN pin can be also provided as outputs to the SPDIFOUT pin.
6-2. SPDIF OUT
SPDIF output is selected from three types of data indicated below:
A : Dolby digital (AC-3) encoded data
B : Output data (to be provided to the DAC slot on the AC-link) after digital mixing
C : Input data applied to the SPDIFIN pin
When the above A and B data are supplied as outputs, output sampling frequency is fixed at 48 kHz, and
when the above C data is supplied as an output, output sampling frequency is dependent on the frequency
available from the SPDIFIN input pin.
Control and category codes of the channel status are provided as sampling rate converter, copyright
protection available and commercially available recorded software in accordance with the serial copy
management system.
generation ones.
Such a code arrangement allows output data to be digitally copied only to the next
When input signal to the SPDIFIN pin is provided as output, no modification is made for
the channel status, etc., and output data is code-dependent available from the SPDIFIN pin.
February 3, 1999
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YMF744B
7. Zoomed Video Port
Zoomed Video Port is defined in the PC Card Standard (PCMCIA) applicable to the notebook PC or other
systems.
This port is used to directly output video and/or audio signals onto the PCMCIA bus for D/A
conversion process, and connect them directly to the video and/or audio signal processing chips on the PC
system.
Its major applications include MPEG decoder card and video capture card, etc.
Because the video and/or audio signals on the Zoomed Video Port have been output in synchronized
condition, DS-1S only converts input audio signal into analog signal through D/A converter.
Audio signals to be transferred on the Zoomed Video Port include bit clock (SCLK), L/R clock (LRCK) and
serial data (DATA), and they are provided as outputs in the format defined below.
This is generally called
2
I S format.
SCLK
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LRCK
LEFT Channel
RIGHT Channel
In the Zoomed Video Port, synchronization with a master clock supplied from the bus is inherently required.
However, DS-1S can asynchronously process audio signal input via the Zoomed Video Port, eliminating the
need for master clock.
Sampling rate of the audio signals input via the Zoomed Video Port is resampled to 96.0kHz sampling
frequency at the stage followed by the SRC block, then converted to 48.0kHz sampling rate in the SRC block
stage.
Sampling rates to be supported on the Zoomed Video Port include 22.05kHz, 32.0kHz, 44.1kHz and
48.0kHz.
Interface connection arrangement between the DS-1S and the Zoomed Video Port is as illustrated below.
DS-1S
ZVBCLK
ZVLRCK
ZVSDI
ZV Port
80
SCLK
79
LRCK
78
DATA
MCLK
Open
The Zoomed Video Port can be used to be selected between the SPDIFIN input.
February 3, 1999
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YMF744B
8. Multiple AC’97 & Multi-Channel
DS-1S allows connection with up to two AC’97s, and plays back up to 4-channel PCM data.
Therefore, the
following applications can be realized.
8-1. AC’97 Digital Docking
AC’97 digital docking can be realized by mounting the secondary AC’97 on the docking station side.
Typical example of digital docking connection between DS-1S and AC’97s is represented in the circuit
diagram below.
CMCLK
XTL_IN
CBCLK
BIT_CLK
SYNC
CSYNC
CSDO
SDATA_OUT
CSDI0
SDATA_IN
Primary
Audio CODEC
RESET#
RST#
DS-1S
GPIO2
CSDI2
DOCKEN#
Isolation Buffer
PC Side
DVDD
Docking Station
XTL_IN
BIT_CLK
SYNC
SDATA_OUT
RESET#
Secondary
Audio CODEC
(AC'97 Rev2.1)
SDATA_IN
CODEC ID=01
When digital docking interface is made with the main side (PC side) powered on, but docking station side
powered off, it may be not desirable for the secondary AC’97 that each output signal from the AC-Link is
applied to the secondary AC’97 that remains in powered off state.
In order to avoid such a situation, it is
necessary to place an additional isolation buffer on the PC side (or docking station side).
8-2. 4-Channel Speaker System
4-channel speaker system can be realized by the connection of DS-1S with two 2-channel AC’97s as
described at “8-1. AC’97 Digital Docking” or using the AC’97 that includes 4-channel D/A converters.
Then, 4-channel PCM data can be played back at one time.
February 3, 1999
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YMF744B
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Item
Symbol
Min.
Max.
Unit
VDD3
-0.3
4.6
V
Input Voltage
VIN
-0.3
7.0
V
Operating Ambient Temperature
TOP
0
70
°C
Storage Temperature
TSTG
-50
125
°C
Power Supply Voltage
(PVDD, VDD, CVDD, LVDD)
Note : PVSS=VSS=0[V]
2. Recommended Operating Conditions
Item
Power Supply Voltage
(PVDD, VDD, CVDD, LVDD)
Operating Ambient Temperature
Symbol
Min.
Typ.
Max.
Unit
VDD3
3.00
3.30
3.60
V
TOP
0
25
70
°C
Note : PVSS=VSS=0[V]
February 3, 1999
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YMF744B
3. DC Characteristics
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
-0.5
-
5.75
V
High Level Input Voltage 1
VIN
High Level Input Voltage 1
VIH1
*1
0.5VDD3
-
5.75
V
Low Level Input Voltage 1
VIL1
*1
-0.5
-
0.3VDD3
V
High Level Input Voltage 2
VIH2
*2
0.7VDD3
-
5.75
V
Low Level Input Voltage 2
VIL2
*2
-0.5
-
0.3VDD3
V
High Level Input Voltage 3
VIH3
*3
0.65VDD3
-
5.75
V
Low Level Input Voltage 3
VIL3
*3
-0.5
-
0.35VDD3
V
High Level Input Voltage 4
VIH4
*4
2.0
-
5.75
V
Low Level Input Voltage 4
VIL4
*4
-0.5
-
0.8
V
0< VIN < VDD5
-10
-
10
µA
Input Leakage Current
IIL
High Level Output Voltage 1
VOH1
*5, IOH1 = -0.5mA
0.9VDD3
-
-
V
Low Level Output Voltage 1
VOL1
*5, IOL1 = 1.5mA
-
-
0.1VDD3
V
High Level Output Voltage 2
VOH2
*6, IOH2 = -80µA
0.8VDD3
-
-
V
Low Level Output Voltage 2
VOL2
*6, IOL2 = 2.0mA
-
-
0.2VDD3
V
High Level Output Voltage 3
VOH3
*7, IOH3 = -2.0mA
0.9VDD3
-
-
V
Low Level Output Voltage 3
VOL3
*7, IOL3 = 6.0mA
-
-
0.1VDD3
V
High Level Output Voltage 4
VOH4
*8, IOH4 = -0.7mA
2.4
-
-
V
Low Level Output Voltage 4
VOL4
*8, IOL4 = 2.0mA
-
-
0.4
V
High Level Output Voltage 5
VOH5
*9, IOH5 = -4.0mA
2.4
-
-
V
Low Level Output Voltage 5
VOL5
*9, IOL5 = 12.0mA
-
-
0.4
V
Input Pin Capacitance
CIN
5
-
15
pF
Clock Pin Capacitance
CCLK
5
-
15
pF
IDSEL Pin Capacitance
CIDSEL
5
-
15
pF
Output Leakage Current
IOL
-10
-
10
µA
Normal
-
TBD
TBD
mA
Power Save (*10)
-
TBD
TBD
mA
Power Supply Current
Note : Top = 0~70°C, PVDD=3.3±0.3[V], VDD=3.3±0.3[V], CVDD=3.3±0.3[V], LVDD=3.3±0.3[V]
*1: Applicable to all PCI Iuput/Output pins and Iunput pins.
*2: Applicable to XI24 pin.
*3: Applicable to CBCLK, CSDI0 and CSDI2 pins.
*4: Applicable to ZVBCLK, ZVLRCK, ZVSDI, GP[7:4], RXD, VOLUP#, VOLDW#, GPIO[2:0], DOCKEN#,
ROMDI, SPDIFIN and TEST# pins.
*5: Applicable to all PCI Input/Output pins and output pins.
*6: Applicable to XO24 pin.
*7: Applicable to CRST#, CSYNC, CSDO and CMCLK pins.
*8: Applicable to SPDIFOUT, ROMSK, ROMDO, ROMCS, TXD and GPIO[2:0] pins.
*9: Applicable to IRQ5, IRQ7, IRQ9, IRQ10 and IRQ11 pins.
*10: All DS-1S Power Control bits are set to “1”.
February 3, 1999
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YMF744B
4. AC Characteristics
4-1. Master Clock
(Fig.1)
Item
Symbol
Min.
Typ.
Max.
Unit
XI24 Cycle Time
tXICYC
-
40.69
-
ns
XI24 High Time
tXIHIGH
13
-
24
ns
XI24 Low Time
tXILOW
13
-
24
ns
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V
2.3 V
1.65 V
XI24
1.0 V
t XIHIGH
t XILOW
t XICYC
Fig.1: XI24 Master Clock timing
4-2. Reset
(Fig.2)
Item
Reset Active Time after Power Stable
Power Stable to Reset Rising Edge
Reset Slew Rate
Symbol
Min.
Typ.
Max.
Unit
tRST
1
-
-
ms
tRSTOFF
10
-
-
ms
-
50
-
-
mV/ns
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF
3.0 V
PVDD, LVDD,
VDD, CVDD
t RSTOFF
t RST
RST#
0.8 V
Fig.2: PCI Reset timing
February 3, 1999
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YMF744B
4-3. PCI Interface
(Fig.3, 4)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
PCICLK Cycle Time
tPCYC
30
-
-
ns
PCICLK High Time
tPHIGH
11
-
-
ns
PCICLK Low Time
tPLOW
11
-
-
ns
PCICLK Slew Rate
-
1
-
4
V/ns
2
-
11
ns
2
-
12
ns
tPVAL
PCICLK to Signal Valid Delay
(Bused signal)
tPVAL(PTP) (Point to Point)
Float to Active Delay
tPON
2
-
-
ns
Active to Float Delay
tPOFF
-
-
28
ns
(Bused signal)
7
-
-
ns
*11 (Point to Point)
10
-
-
ns
*12 (Point to Point)
12
-
-
ns
0
-
-
ns
tPSU
Input Setup Time to PCICLK
tPSU(PTP)
Input Hold Time for PCICLK
tPH
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=10 pF
*11: This characteristic is applicable to REQ# and PCREQ# signal.
*12: This characteristic is applicable to GNT# and PCGNT# signal.
0.5 VDD3
0.4 VDD3
PCICLK
0.3 VDD3
t PHIGH
t PLOW
t PCYC
Fig.3: PCI Clock timing
1.5 V
PCICLK
t PVAL
1.5 V
OUTPUT
t PON
Tri-State
OUTPUT
t PSU
t POFF
t PH
1.5 V
INPUT
Fig.4: PCI Bus Signals timing
February 3, 1999
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YMF744B
4-4. AC’97 Master Clock
(Fig.5)
Item
Symbol
Min.
Typ.
Max.
Unit
CMCLK Cycle Time
tCMCYC
-
40.69
-
ns
CMCLK High Time
tCMHIGH
8
-
-
ns
CMCLK Low Time
tCMLOW
8
-
ns
CMCLK Rising Time
tCMR
-
4.6
-
ns
CMCLK Falling Time
tCMF
-
2.1
-
ns
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF
t CMR
t CMF
0.8 VDD3
0.5 VDD3
CMCLK
0.2 VDD3
t CMHIGH
t CMLOW
t CMCYC
Fig.5: Master Clock timing for AC’97
February 3, 1999
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YMF744B
4-5. AC-link
(Fig.6)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
CBCLK Cycle Time
tCBICYC
-
81.4
-
ns
CBCLK High Time
tCBIHIGH
35
40.7
45
ns
CBCLK Low Time
tCBILOW
35
40.7
45
ns
CSYNC Cycle Time
tCSYCYC
-
20.8
-
ns
CSYNC High Time
tCSYHIGH
-
1.3
-
µs
CSYNC Low Time
tCSYLOW
-
19.5
-
µs
CBCLK to Signal Valid Delay
tCVAL
*13
-
-
20
ns
Output Hold Time for CBCLK
tCOH
*13
0
-
-
ns
Input Setup Time to CBCLK
tCISU
*14
15
-
-
ns
Input Hold Time for CBCLK
tCIH
*14
5
-
-
ns
-
1.3
-
µs
Warm Reset Width
Note) Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF
*13: This characteristic is applicable to CSYNC and CSDO signal.
*14: This characteristic is applicable to CSDI signal.
t CBICYC
2.0 V
CBCLK
1.5 V
t CBIHIGH
0.8 V
t CBILOW
t COH
t CSYLOW
t CVAL
2.0 V
SYNC
1.5 V
0.8 V
t CSYHIGH
t CSYCYC
t CVAL
t COH
2.0 V
CSDO
0.8 V
t CISU
t CIH
2.0 V
CSDI
0.8 V
Fig.6: AC-link timing
February 3, 1999
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YMF744B
4-6. Zoomed Video Port
Item
(Fig.7)
Symbol
Min.
Typ.
Max.
Unit
ZVLRCK Delay Time
tSLRD
2
-
-
ns
ZVLRCK Setup Time
tSLRS
32
-
-
ns
ZVBCLK Low Time
tSCLKL
22
-
-
ns
ZVBCLK High Time
tSCLKH
22
-
-
ns
ZVSDI Setup Time
tSDS
32
-
-
ns
ZVSDI Hold Time
tSDH
2
-
-
ns
Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF
ZVLRCK
tSLRD
tSLRS
ZVSCLK
tSDS
tSDH
tSCLKH
t SCLKL
ZVSDI
Fig.7: Zoomed Video Port timing
February 3, 1999
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YMF744B
EXTERNAL DIMENSIONS
YMF744B-V
22.00±0.40
20.00±0.30
0.15Typ. or 0.17Typ.
(LEAD THICKNESS)
65
64
128
39
14.00±0.30
103
1
38
0.20±0.10
1.40±0.20
1.70MAX.
P-0.50Typ.
0 Min. (STAND OFF)
16.00±0.40
102
(1.00)
0-15˚
0.50±0.30
Unit : mm
The shape of the molded corner may slightly different from the shape in this diagram.
The figure in the parenthesis (
) should be used as a reference.
Plastic body dimensions do not include burr of resin.
UNIT : mm
Note : The LSIs for surface mount need especial consideration on storage and soldering conditions.
For detailed information, please contact your nearest agent of Yamaha.
February 3, 1999
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YMF744B
YMF744B-R
16.00±0.40
14.00±0.30
65
64
128
33
14.00±0.30
97
1
32
P-0.40Typ.
1.40±0.20
1.70MAX.
0.16±0.10
0 Min. (STAND OFF)
16.00±0.40
96
(1.0)
0-10˚
0.50±0.20
LEAD THICKNESS : 0.125Typ. or 0.15Typ.
Unit : mm
The shape of the molded corner may slightly different from the shape in this diagram.
The figure in the parenthesis (
) should be used as a reference.
Plastic body dimensions do not include burr of resin.
UNIT : mm
Note : The LSIs for surface mount need especial consideration on storage and soldering conditions.
For detailed information, please contact your nearest agent of Yamaha.
February 3, 1999
-59-
YMF744B
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without
notice. The information contained in this document has been carefully checked and is
believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and
makes no commitment to update or to keep current the information contained in this
document.
2. These Yamaha Products are designed only for commercial and normal industrial
applications, and are not suitable for other uses, such as medical life support equipment,
nuclear facilities, critical care equipment or any other application the failure of which could
lead to death, personal injury or environmental or property damage. Use of the Products in
any such application is at the customer's sole risk and expense.
3. YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL, CONSEQUENTIAL OR
SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR
IMPROPER USE OR OPERATION OF THE PRODUCTS.
4. YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS
ARE SUBJECT TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR
ANYTHIRD PARTY, AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION
OF NON-INFRINGEMENT WITH RESPECT TO THE PRODUCTS. YAMAHA
SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD
PARTY ARISING FROM OR RELATED TO THE PRODUCTS' INFRINGEMENT OF ANY
THIRD PARTY'S INTELLECTUAL PROPERTY RIGHTS, INCLUDING THE PATENT,
COPYRIGHT, TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY.
5. EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE
CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS. YAMAHA
ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR
OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE
EXAMPLES DESCRIBED HEREIN. YAMAHA MAKES NO WARRANTY WITH RESPECT
TO THE PRODUCTS, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO THE
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR USE AND
TITLE.
Note) The specifications of this product are subject to improvement change without prior notice.
AGENCY
YAMAHA CORPORATION
Address inquires to :
Semi-conductor Sales Department
- Head Office
- Tokyo Office
- Osaka Office
- U.S.A. Office
203, MatsunokiJima, Toyooka-mura.
Iwata-gun, Shizuoka-ken, 438-0192
Tel. +81-539-62-4918 Fax. +81-539-62-5054
2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568
Tel. +81-3-5488-5431 Fax. +81-3-5488-5088
1-13-17, Namba Naka, Naniwa-ku,
Osaka City, Osaka, 556-0011
Tel. +81-6-6633-3690 Fax. +81-6-6633-3691
YAMAHA System Technology.
100 Century Center Court, San Jose, CA 95112
Tel. +1-408-467-2300 Fax. +1-408-437-8791
February 3, 1999
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