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Frame Status FIFO Circuitry
RR1
Reset on Flag Detect
SCC Status Reg
Residue Bits (3)
Overrun, CRC Error
Byte Counter
Increment on Byte Detection
Enable Count in SDLC
5 Bits
End of Frame Signal
Status Read Comp
14 Bits
FIFO Array
10 Deep by 19 Bits Wide
Tail Pointer
4-Bit Counter
Head Pointer
4-Bit Counter
4-Bit Comparator
Over
EOF = 1
5 Bits
6 Bits
8 Bits
EN
6-Bit MUX
2 Bits
6 Bits
RR1
Equal
Bit 7 Bit 6
Bits 5-0
RR6
FIFO Enable
RR7 D5-D0 + RR6 D7-D0
Byte Counter Contains 14 bits
for a 16 KByte maximum count
Interface
to SCC
WR(15) Bit 2
Set Enables
Status FIFO
RR7 D6
FIFO Data available status bit Status Bit set to 1
When reading from FIFO
RR7 D7
FIFO Overflow Status Bit
MSB pf RR(7) is set on Status FIFO overflow
In SDLC Mode the following definitions apply
– All Sent bypasses MUX and equals contents of SCC Status Register
– Parity Bits bypasses MUX and does the same
– EOF is set to 1 whenever reading from the FIFO
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Increments Counter
Don’t Load
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Reset Byte
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A
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7
0
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Internal Byte Strobe
Increments Counter
Reset
Byte Counter
Load Counter
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Increment PTR
Reset
Byte Counter
Reset
Byte Counter
Load Counter
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Increment PTR
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Write Register 0 (non-multiplexed bus mode)
Write Register 1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Ext Int Enable
0 0 0 Register 0
0 0 1 Register 1
0 1 0 Register 2
0 1 1 Register 3
1 0 0 Register 4
1 0 1 Register 5
1 1 0 Register 6
1 1 1 Register 7
0 0 0 Register 8
0 0 1 Register 9
0 1 0 Register 10
0 1 1 Register 11
*
1 0 0 Register 12
1 0 1 Register 13
1 1 0 Register 14
1
1 Register 15
Null Code
Point High
Reset Ext/Status Interrupts
Send Abort (SDLC)
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
0
0
1
1
0
1
0
1
Tx Int Enable
Parity is Special Condition
0
0
1
1
0
1
0
1
Rx Int Disable
Rx Int on First Character or Special Condition
Int on all Rx Characters or Special Condition
Rx Int on Special Condition Only
WAIT/DMA Request on
Receive /Transmit
WAIT/DMA Request Function
WAIT/DMA Request
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Null Code
Reset Rx CRC Checker
Reset Tx CRC Generator
Reset Tx Underrun/EOM Latch
Write Register 2
D7 D6 D5 D4 D3 D2 D1 D0
V0
V1
V2
V3
V4
* With Point High Command
Interrupt
Vector
V5
V6
Write Register 0 (multiplexed bus mode)
V7
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 3
0
0
1
1
0
1
0
1
Null Code
Null Code
Select Shift Left Mode
Select Shift Right Mode
D7 D6 D5 D4 D3 D2 D1 D0
*
Rx Enable
Sync Character Load Inhibit
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Null Code
Null Code
Reset Ext/Status Interrupts
Send Abort
Enable Int on Next Rx Character
Reset Tx Int Pending
Error Reset
Reset Highest IUS
Null Code
Reset Rx CRC Checker
Reset Tx CRC Checker
Reset Tx Underrun/EOM Latch
Address Search Mode (SDLC)
Rx CRC Enable
Enter Hunt Mode
Auto Enables
0
0
1
1
0
1
0
1
Rx 5 Bits/Character
Rx 7 Bits/Character
Rx 6 Bits/Character
Rx 8 Bits/Character
* B Channel Only
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Write Register 4
Write Register 5
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
Parity Enable
Tx CRC Enable
Parity EVEN/ODD
RTS
SDLC/CRC-16
Sync Modes Enable
1 Stop Bit/Character
1 1/2 Stop Bits/Character
2 Stop Bits/Character
8-Bit Sync Character
16-Bit Sync Character
SDLC Mode (01111110 Flag)
External Sync Mode
Tx Enable
Send Break
0
0
1
1
0
1
0
1
Tx 5 Bits (or Less)/Character
Tx 7 Bits/Character
Tx 6 Bits/Character
Tx 8 Bits/Character
DTR
0
0
1
1
0 X1 Clock Mode
1 X16 Clock Mode
0 X32 Clock Mode
1 X64 Clock Mode
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Write Register 6
D7 D6 D5 D4 D3 D2 D1 D0
Sync7
Sync1
Sync7
Sync3
ADR7
ADR7
Sync6
Sync0
Sync6
Sync2
ADR6
ADR6
Sync5
Sync5
Sync5
Sync1
ADR5
ADR5
Sync4
Sync4
Sync4
Sync0
ADR4
ADR4
Sync3
Sync3
Sync3
1
ADR3
x
Sync2
Sync2
Sync2
1
ADR2
x
Sync1
Sync1
Sync1
1
ADR1
x
Sync0
Sync0
Sync0
1
ADR0
x
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
SDLC (Address Range)
Write Register 7
D7 D6 D5 D4 D3 D2 D1 D0
Sync7 Sync6
Sync5 Sync4
Sync15 Sync14
Sync11 Sync10
1
0
Sync5
Sync3
Sync13
Sync9
1
Sync4
Sync2
Sync12
Sync8
1
Sync3
Sync1
Sync11
Sync7
1
Sync2 Sync1 Sync0
x
Sync0
x
Sync10 Sync9 Sync8
Sync6 Sync5 Sync4
1
1
0
Monosync, 8 Bits
Monosync, 6 Bits
Bisync, 16 Bits
Bisync, 12 Bits
SDLC
WR 7’ Prime (85C30 only)
D7 D6 D5 D4 D3 D2 D1 D0
Auto Tx Flag
Auto EOM Reset
Auto RTS Deactivation
Force TxD High
DTR/REQ Fast Mode
Complete CRC Reception
Extended Read Enable
Reserved (Program as 0)
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Write Register 9
Write Register 9
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
0
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
VIS
TC0
NV
TC1
DLC
TC2
MIE
TC3
Status High/Status Low
TC4
Software INTACK Enable
TC5
Lower Byte of
Time Constant
TC6
No Reset
Channel Reset B
Channel Reset A
Force Hardware Reset
TC7
Write Register 13
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 9
D7 D6 D5 D4 D3 D2 D1 D0
TC8
TC9
0
0
1
1
6-Bit/8-Bit Sync
TC10
Loop Mode
TC11
Abort/Flag on Underrun
TC12
Mark/Flag Idle
TC13
Go Active on Poll
TC14
Upper Byte of
Time Constant
TC15
0 NRZ
1 NRZI
0 FM1 (Transition = 1)
1 FM1 (Transition = 0)
Write Register 14
D7 D6 D5 D4 D3 D2 D1 D0
CRC Preset I/O
BR Generator Enable
Write Register 11
BR Generator Source
D7 D6 D5 D4 D3 D2 D1 D0
DTR/Request Function
Auto Echo
0
0
1
1
0
1
0
1
TRxC Out = Xtal Output
TRxC Out = Transmit Clock
TRxC Out = BR Generator Output
TRxC Out = DPLL Output
TRxC O/I
0
0
1
1
0 Transmit Clock = RTxC Pin
1 Transmit Clock = TRxC Pin
0 Transmit Clock = BR Generator Output
1 Transmit Clock = DPLL Output
Local Loopback
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Null Command
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Reset Missing Clock
Disable DPLL
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Set Source = RTxC
Set FM Mode
Set NRZI Mode
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0
0
1
1
0 Receive Clock = RTxC Pin
1 Receive Clock = TRxC Pin
0 Receive Clock = BR Generator Output
1 Receive Clock = DPLL Output
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RTxC Xtal/No Xtal
0
Zero Count IE
SDLC FIFO Enable
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
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Rx Character Available
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Zero Count
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DCD
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0
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0
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Read Register 10
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All Sent
Residue Code 2
0
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On Loop
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0
Parity Error
0
Rx Overrun Error
Loop Sending
CRC/Framing Error
0
End of Frame (SDLC)
Two Clocks Missing
One Clocks Missing
Read Register 2
Read Register 12
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
V0
TC0
V1
TC1
V2
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Interrupt
Vector *
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TC3
V5
TC4
V6
TC5
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Read Register 15
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0
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TC10
TC11
TC12
0
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of Time Constant
TC13
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Sync/Hunt IE
CTS IE
TC14
Tx Underrun/EOM IE
TC15
Break/Abort IE
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