Z86247 CPS DC-9027-00 PRELIMINARY CUSTOMERPROCUREMENTSPECIFICATION Z86247 40-PINLOW-COSTDIGITAL TELEVISIONCONTROLLER(4LDTC) GENERAL DESCRIPTION The Z86247 40-pin Low-Cost Digital Television Controller (4LDTC) introduces a new level of sophistication to singlechip architecture. The Z86247 is a member of the Z8 ® single-chip microcontroller family with 8 Kbytes of ROM and 236 bytes of RAM. The device is offered in a 40-pin package and is CMOS compatible. The 4LDTC offers mask programmed ROM which enables the Z8 microcontroller to be used in a high volume production application device embedded with a custom program (customer supplied program) and combines together with the Z86C27 (DTC) and Z86127 (LDTC) to provide support for high end, mid range and low end TV applications. Zilog’s 4LDTC offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The device provides an ideal performance and reliability solution for consumer and industrial television applications. The Z86247 architecture is characterized by utilizing Zilog’s advanced Superintegration™ design methodology. The device has an 8-bit internal data path controlled by a Z8 microcontroller and On Screen Display (OSD) logic circuits and Pulse Width Modulators (PWM). On-chip peripherals include two register mapped I/O ports (Ports 2 and Port 3), interrupt control logic (one software, two external and three internal interrupts) and a standby mode recovery input port (Port 3, pin P30). The OSD control circuits support 8 rows by 20 columns of characters. The character color is specified by row. One of the eight rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying high resolution (11x15 dot pattern) characters. DC 9027-00 (7-27-94) A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Three 6-bit PWM ports are used for controlling audio signal levels. Three 8-bit PWM ports used to vary picture levels. The 4LDTC applications demand powerful I/O capabilities. The Z86247 fulfills this with 24 pins dedicated to input or output. These lines are grouped into three ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory. There are three basic address spaces available to support this wide range of configurations: Program Memory, Video RAM, and Register File. The Register File is composed of 236 bytes of general purpose registers, two I/O Port registers, 15 control and status registers and three reserved registers. To unburden the program from coping with the real-time problems such as counting/timing and data communication, the 4LDTC offers two on-chip counter/timers with a large number of user selectable modes (Figure 1). Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 Z86247 CPS DC-9027-00 GENERAL DESCRIPTION (Continued) XTAL1 XTAL2 /RESET RESET Oscillator WDT Counter Timer Counter Timer P30 P31 P34 P35 P36 Port 3/ Interrupt P60 P61 P62 P63 P64 P65 AFCIN Port 6 (Control) 8 KByte Program ROM Port 2 Z8 CPU Core 256 Byte Register File Port 0 Port 1 A8-15 PWM 1 14 -bit PWM 1 PWM 6 to PWM 8 6-bit PWM 6 PWM 7 PWM 8 PWM 9 to PWM11 PWM 9 PWM 10 PWM 11 On Screen Display OSCIN OSCOUT HSYNC VSYNC VRED VGREEN VBLUE VBLANK AD0-7 128 Byte Character RAM 4 KByte Character ROM Functional Block Diagram 2 P27 P26 P25 P24 P23 P22 P21 P20 Z86247 CPS DC-9027-00 PIN CONFIGURATION PWM1 1 40 PWM6 P35 2 39 PWM7 P36 P34 3 38 PWM8 4 37 PWM9 P31 5 36 PWM10 P30 6 35 PWM11 XTAL1 XTAL2 7 34 P27 8 33 P26 /RESET 9 32 P25 31 P24 Z86247 (LDTC) P60 10 GND 11 30 P23 P61 12 29 P62 VCC 13 28 P22 P21 14 27 P20 P63 15 26 VBLANK P64 16 25 VBLUE P65 17 24 VGREEN AFCIN OSCIN 18 19 23 VRED 22 OSCOUT 20 21 VSYNC HSYNC 40-Pin Mask-ROM Plastic DIP 3 Z86247 CPS DC-9027-00 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameters Min Max Units Notes VCC VI VI VO IOH Power Supply Voltage* Input Voltage Input Voltage Output Voltage Output Current High –0.3 –0.3 –0.3 –0.3 +7 VCC +0.3 VCC +0.3 VCC +8.0 –10 V V V V mA [1] [2,3] 1 pin IOH IOL IOL TA TSTG Output Current High Output Current Low Output Current Low Operating Temperature Storage Temperature –100 20 200 mA mA mA All total 1 pin All total +150 C † –65 Notes: [1] Port 2 open-drain [2] PWM open-drain outputs [3] PWM breakdown is 13.2V (normal operation). Will withstand 16V max. (non-momentary operating). * Voltage on all pins with respect to GND. † See Ordering Information STANDARD TEST CONDITIONS VDD The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram). RLL From Output Under Test 150 pF Test Load Diagram 4 RLH Z86247 CPS DC-9027-00 CAPACITANCE TA=25°C; VCC=GND=0V; Freq=1.0 MHz; unmeasured pins to GND. Parameter Input capacitance Output capacitance I/O capacitance AFCIN input capacitance Max Units 10 20 25 10 pF pF pF pF DC CHARACTERISTICS TA=0°C to +70°C; V CC=+4.5V to +5.5V; FOSC=4 MHz TA=0°C to +70°C Min Max Sym Parameter VIL VILC VIH Input Voltage Low Input XTAL/Osc In Low Input Voltage XTAL/Osc In High VIHC VHY VPU Input XTAL/Osc In High Schmitt Hysteresis Maximum Pull-Up Voltage VOL Output Voltage Low V00-01 V01-11 VOH AFC Level 01 In AFC Level 11 In Output Voltage High 0.5 VCC V CC–0.4 IIR IIL IOL Reset Input Current Input Leakage Tri-State Leakage –3.0 –3.0 ICC ICC1 ICC2 Supply Current 0 0.7 VCC 0.8 VCC 0.1 VCC Typical @ 25°C Units Conditions 0.2 VCC 0.07 VCC VCC 1.48 0.98 3.2 V V V VCC 3.0 0.8 V V V External Clock Generator Driven 12 External Clock Generator Driven External Clock Generator Driven [1] 0.4 0.4 0.16 0.19 V V IOL=1.00 mA IOL=0.75 mA [1] 0.45 VCC 0.75 VCC 1.9 3.12 4.75 V V V IOH=–0.75 mA –80 3.0 3.0 –46 0.01 0.02 µA µA µA VRL=0V 0V,VCC 0V,VCC 20 6 10 13.2 3.2 2.0 mA mA µA All inputs at rail All inputs at rail All inputs at rail Note: [1] PWM open-drain 5 Z86247 CPS DC-9027-00 AC CHARACTERISTICS Timing Diagrams 1 3 XTAL1 3 2 2 External Clock 7 5 Tin 4 6 Counter Timer IRQn 8 9 Interrupt Request 6 Z86247 CPS DC-9027-00 AC CHARACTERISTICS Timing Diagrams (Continued) Vcc 10 11 Internal /RESET 12 External /RESET Power-On Reset HSYNC 13 14 OSC2 On-Screen Display 7 Z86247 CPS DC-9027-00 AC CHARACTERISTICS TA=0° C to +70° C; VCC=+4.5V to +5.5V; FOSC=4 MHz No Symbol Parameter Min Max Unit 1 2 3 4 TpC TrC,TfC TwC TwTinL Input Clock Period Clock Input Rise and Fall Input Clock Width Timer Input Low Width 250 1000 15 ns ns ns ns 5 6 7 8a TwTinH TpTin TrTin,TfTin TwIL Timer Input High Width Timer Input Period Timer Input Rise and Fall Int Req Input Low 3TpC 8TpC 100 ns ns 8b 9 10 11 TwIL TwIH TdPOR TdLVIRES 100 ms ns 12 13 14 15 TwRES TdHsOI TdHsOh TdWDT Int Request Input High Power On Reset Delay Low Voltage Detect to Internal RESET Condition Reset Minimum Width Hsync Start to Vosc Stop Hsync End to Vosc Start WDT Refresh Time 70 70 70 3TpC 3TpC 25 200 5TpC 2TpV 3TpV 1TpV 12 ms Note: Refer to DC Characteristics for details on switching levels. Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-con- Low Margin: Customer is advised that this product does not meet Zilog’s internal guardbanded test policies for the specification requested and is supplied on an exception basis. © 1994 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 8 formance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056