ZILOG Z86C44

PRELIMINARY PRODUCT SPECIFICATION
Z86C34/C35/C36
Z86C44/C45/C46
CMOS Z8® MCUS WITH ASCI UART
OFFER EFFICIENT, COST-EFFECTIVE
DESIGN FLEXIBILITY
FEATURES
Device
ROM
(KB)
RAM*
(Bytes)
Speed
(MHz)
Z86C34
Z86C35
Z86C36
Z86C44
Z86C45
Z86C46
16
32
64
16
32
64
237
237
237
236
236
236
16
16
16
16
16
16
Note: *General-Purpose.
•
28-Pin DIP, 28-Pin SOIC and PLCC Packages (C34,
C35, C36)
•
40-Pin DIP, 44-Pin PLCC and QFP Packages (C44,
C45, C46)
•
•
•
3.0- to 5.5-Volt Operating Range
Clock Free Watch-Dog Timer (WDT) Reset
•
•
•
•
Expanded Register File (ERF)
Full-Duplex UART (ASCI)
Dedicated 16-Bit Baud Rate Generator
32 Input/Output Lines (C44/C45/C46)
24 Input/Output Lines (C34/C35/C36)
•
Vectored, Prioritized Interrupts with Programmable Polarity
•
•
Two Analog Comparators
Two Programmable 8-Bit Counter/Timers, Each with
Two 6-Bit Programmable Prescaler
•
•
Watch-Dog Timer (WDT)/Power-On Reset (POR)
•
•
RAM and ROM Protect
On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock
Optional 32-kHz Oscillator
Operating Temperature Ranges:
Standard: 0 °C to 70 °C
Extended: –40 °C to +105 °C
GENERAL DESCRIPTION
ZiLOG’s Z8® MCU single-chip family now includes the
Z86C34/C35/C36/C44/C45/C46 product line, featuring enhanced wake-up circuitry, programmable Watch-Dog Timers (WDT), and low-noise/EMI options. Each of the new enhancements to the Z8 offer a more efficient, cost-effective
design and provide the user with increased design flexibility
over the standard Z8 microcontroller core. The low-power
consumption CMOS microcontroller offers fast execution,
efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion.
DS007601-Z8X0499
The Z8 subfamily features an Expanded Register File (ERF)
to allow access to register-mapped peripheral and I/O circuits. Four basic address spaces are available to support this
wide range of configurations: Program Memory, Register
File, Data Memory, and ERF. The Register File is composed
of 236/237 bytes of general-purpose registers, four I/O port
registers, and 15 control and status registers. The ERF consists of twelve control registers.
For applications demanding powerful I/O capabilities, the
Z86C34/C35/C36 offers 24 pins, and the Z86C44/C45/C46
offers 32 pins dedicated to input and output. These lines are
1
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
GENERAL DESCRIPTION (Continued)
configurable under software control to provide timing, status signals, parallel I/O with or without handshake, and address/data bus for interfacing external memory.
Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for
which BYTE is active Low.
To unburden the system from coping with real-time tasks
such as counting/timing and data communication, the Z8
offer two on-chip counter/timers with a large number of
user-selectable modes.
Power connections follow these conventional descriptions:
With ROM/ROMless selectivity, the Z86C44/C45/C46
provide both external memory and preprogrammed ROM,
which enables this Z8® MCU to be used in high-volume applications, or where code flexibility is required.
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
(C44/C45/C46 Only)
Output
Input
VCC
GND
XTAL AS DS R/W RESET
Port 3
Machine
Timing & Inst.
Control
Counter/
Timers (2)
RESET
WDT, POR
ALU
Interrupt
Control
Two Analog
Comparators
Full-Duplex
UART
FLAG
Program
Memory
Register
Pointer
Register File
Program
Counter
Port 0
Port 1
16-Bit Baud
Rate Generator
Port 2
4
I/O
(Bit Programmable)
4
Address or I/O
(Nibble Programmable)
8
Address/Data or I/O
(Byte Programmable)
(C44/C45/C46 Only)
Figure 1. Functional Block Diagram
2
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN DESCRIPTION
28
Z86C34/C35/C36
14
15
P24
P23
P22
P21
P20
P03
GND
P02
P01
P00
P30
P36
P37
P35
P04
P27
P26
P25
P24
P23
P22
1
4
P05
P06
P07
VCC
XTAL2
XTAL1
P31
5
1
26
25
Z86C34/C35/C36
11
12
19
18
P21
P20
P03
GND
P02
P01
P00
P32
P33
P34
P35
P37
P36
P30
P25
P26
P27
P04
P05
P06
P07
VCC
XTAL2
XTAL1
P31
P32
P33
P34
Figure 2. 28-Pin DIP/SOIC Pin Configuration
Figure 3. 28-Pin PLCC Pin Configuration
Table 1. 28-Pin DIP/SOIC/PLCC Pin Identification
Pin #
Symbol
Function
Direction
1–3
4–7
8
P25–27
P04–07
VCC
Port 2, Bits 5,6,7
Port 0, Bits 4,5,6,7
Power Supply
In/Output
In/Output
9
10
11–13
14–15
16
17
18
19–21
22
23
24–28
XTAL2
XTAL1
P31–33
P34–35
P37
P36
P30
P00–02
GND
P03
P20–24
Crystal Oscillator
Crystal Oscillator
Port 3, Bits 1,2,3
Port 3, Bits 4,5
Port 3, Bit 7
Port 3, Bit 6
Port 3, Bit 0
Port 0, Bits 0,1,2
Ground
Port 0, Bit 3
Port 2, Bits 0,1,2,3,4
Output
Input
Fixed Input
Fixed Output
Fixed Output
Fixed Output
Fixed Input
In/Output
DS007601-Z8X0499
PRELIMINARY
In/Output
In/Output
3
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN DESCRIPTION (Continued)
R/W
P25
P26
P27
P04
P05
P06
P14
P15
P07
VCC
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
AS
1
40
Z86C44/C45/C46
20
21
DS
P24
P23
P22
P21
P20
P03
P13
P12
GND
P02
P11
P10
P01
P00
P30
P36
P37
P35
RESET
Figure 4. 40-Pin DIP Configuration
Table 2. 40-Pin Dual-In-Line Package Pin Identification
Table 2. 40-Pin Dual-In-Line Package Pin Identification
Pin #
Symbol
Function
Direction
Pin #
Symbol
Function
Direction
1
2–4
5–7
8–9
10
11
R/W
P25–27
P04–06
P14–15
P07
VCC
READ/WRITE
Port 2, Bits 5,6,7
Port 0, Bits 4,5,6
Port 1, Bits 4,5
Port 0, Bit 7
Power Supply
Output
In/Output
In/Output
In/Output
In/Output
12–13
14
15
16–18
19
20
P16–17
XTAL2
XTAL1
P31–33
P34
AS
Port 1, Bits 6,7
Crystal Oscillator
Crystal Oscillator
Port 3, Bits 1,2,3
Port 3, Bit 4
Address Strobe
In/Output
Output
Input
Input
Output
Output
21
22
23
24
25
26–27
28–29
30
31
32–33
34
35–39
40
RESET
P35
P37
P36
P30
P00–01
P10–11
P02
GND
P12–13
P03
P20–24
DS
Reset
Port 3, Bit 5
Port 3, Bit 7
Port 3, Bit 6
Port 3, Bit 0
Port 0, Bit 0,1
Port 1, Bit 0,1
Port 0, Bit 2
Ground
Port 1, Bit 2,3
Port 0, Bit 3
Port 2, Bit 0,1,2,3,4
Data Strobe
Input
Output
Output
Output
Input
In/Output
In/Output
In/Output
4
PRELIMINARY
In/Output
In/Output
In/Output
Output
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
P20
P03
P13
P12
GND
GND
P02
P11
P10
P01
P00
ZiLOG
6
1
40
39
7
Z86C44/C45/C46
17
29
28
18
P30
P36
P37
P35
RESET
R/RL
AS
P34
P33
P32
P31
P05
P06
P14
P15
P07
VCC
VCC
P16
P17
XTAL2
XTAL1
P21
P22
P23
P24
DS
NC
R/W
P25
P26
P27
P04
Figure 5. 44-Pin PLCC Pin Configuration
Table 3. 44-Pin PLCC Pin Identification
Pin #
Symbol
Function
1–2
3–4
5
6–10
11
12
13
14–16
17–19
20–21
22
23–24
GND
P12–13
P03
P20–24
DS
NC
R/W
P25–27
P04–06
P14–15
P07
VCC
Ground
Port 1, Bits 2,3
Port 0, Bit 3
Port 2, Bits 0,1,2,3,4
Data Strobe
Not Connected
READ/WRITE
Port 2, Bits 5,6,7
Port 0, Bits 4,5,6
Port 1, Bits 4,5
Port 0, Bit 7
Power Supply
25–26
P16–17
Port 1, Bits 6,7
DS007601-Z8X0499
Direction
In/Output
In/Output
In/Output
Output
Output
In/Output
In/Output
In/Output
In/Output
In/Output
Table 3. 44-Pin PLCC Pin Identification
Pin #
Symbol
Function
Direction
27
28
29–31
32
33
34
35
36
37
38
39
40–41
42–43
44
XTAL2
XTAL1
P31–33
P34
AS
R/RL
RESET
P35
P37
P36
P30
P00–01
P10–11
P02
Crystal Oscillator
Crystal Oscillator
Port 3, Bits 1,2,3
Port 3, Bit 4
Address Strobe
ROM/ROMless Control
Reset
Port 3, Bit 5
Port 3, Bit 7
Port 3, Bit 6
Port 3, Bit 0
Port 0, Bits 0,1
Port 1, Bits 0,1
Port 0, Bit 2
Output
Input
Input
Output
Output
Input
Input
Output
Output
Output
Input
In/Output
In/Output
In/Output
PRELIMINARY
5
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
P20
P03
P13
P12
GND
GND
P02
P11
P10
P01
P00
PIN DESCRIPTION (Continued)
33
34
23
22
Z86C44/C45/C46
44
1
12
11
P30
P36
P37
P35
RESET
R/RL
AS
P34
P33
P32
P31
P05
P06
P14
P15
P07
VCC
VCC
P16
P17
XTAL2
XTAL1
P21
P22
P23
P24
DS
NC
R/W
P25
P26
P27
P04
Figure 6. 44-Pin QFP Pin Configuration
Table 4. 44-Pin QFP Pin Identification
Table 4. 44-Pin QFP Pin Identification
Pin #
Symbol
Function
Direction
Pin #
Symbol
Function
Direction
1–2
3–4
5
6–7
P05–06
P14–15
P07
VCC
Port 0, Bits 5,6
Port 1, Bits 4,5
Port 0, Bit 7
Power Supply
In/Output
In/Output
In/Output
8–9
10
11
12–14
15
16
17
18
19
20
P16–17
XTAL2
XTAL1
P31–33
P34
AS
R/RL
RESET
P35
P37
Port 1 Bits 6,7
Crystal Oscillator
Crystal Oscillator
Port 3, Bits 1,2,3
Port 3, Bit 4
Address Strobe
ROM/ROMless Control
Reset
Port 3, Bit 5
Port 3, Bit 7
In/Output
Output
Input
Input
Output
Output
Input
Input
Output
Output
21
22
23–24
25–26
27
28–29
30–31
32
33–37
38
39
40
P36
P30
P00–01
P10–11
P02
GND
P12–13
P03
P20–24
DS
NC
R/W
Port 3, Bit 6
Port 3, Bit 0
Port 0, Bits 0,1
Port 1, Bits 0,1
Port 0, Bit 2
Ground
Port 1, Bits 2,3
Port 0, Bit 3
Port 2, Bits 0,1,2,3,4
Data Strobe
Not Connected
READ/WRITE
Output
Input
In/Output
In/Output
In/Output
6
PRELIMINARY
In/Output
In/Output
In/Output
Output
Output
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Units
Notes
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to VSS
–40
–65
–0.6
+105
+150
+7
C
C
V
1
Voltage on VDD Pin with Respect to VSS
–0.3
+7
V
Voltage on XTAL1 and RESET Pins with Respect to VSS
–0.6
VDD+1
V
Total Power Dissipation
Maximum Allowable Current out of VSS
1.21
220
W
mA
Maximum Allowable Current into VDD
180
mA
+600
+600
25
25
µA
µA
mA
mA
Maximum Allowable Current into an Input Pin
Maximum Allowable Current into an Open-Drain Pin
Maximum Allowable Output Current Sunk by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
–600
–600
2
3
4
Notes:
1. Applies to all pins except XTAL pins and where otherwise noted.
2. There is no input protection diode from pin to VDD and current into pin is limited to ±600 µA.
3. Excludes XTAL pins.
4. Device pin is not at an output Low state.
Stresses greater than those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended
period may affect device reliability.
DS007601-Z8X0499
Total power dissipation should not exceed 1.21 W for the
package. Power dissipation is calculated as follows:
Total Power Dissipation = VDD x [IDD – (sum of IOH),
PRELIMINARY
+ sum of [(VDD – VOH) x IOH]
+ sum of (VOL x IOL)
7
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
STANDARD TEST CONDITIONS
The characteristics listed in following pages apply for standard test conditions as noted. All voltages are referenced
to GND. Positive current flows into the referenced pin (see
Figure 7.)
From Output
Under Test
150 pF
Figure 7. Test Load Diagram
CAPACITANCE
TA = 25ºC, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins to GND
Parameter
Input capacitance
Output capacitance
I/O capacitance
8
Min
Max
0
0
0
12 pF
12 pF
12 pF
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
DC ELECTRICAL CHARACTERISTICS
Table 5. DC Characteristics
TA =
0°C to +70°C
Min
Max
Min
Max
Typical2
@25°C
3.0V
0.7 VCC
VCC+0.3
0.7 VCC
VCC+0.3
1.8
V
5.5V
0.7 VCC
VCC+0.3
0.7 VCC
VCC+0.3
2.6
V
3.0V
GND–0.3
0.2 VCC
GND–0.3
0.2 VCC
1.2
V
5.5V
GND–0.3
0.2 VCC
GND–0.3
0.2 VCC
2.1
V
Input High
Voltage
3.0V
0.7 VCC
VCC+0.3
0.7 VCC
VCC+0.3
1.8
V
5.5V
0.7 VCC
VCC+0.3
0.7 VCC
VCC+0.3
2.6
V
Input Low
Voltage
3.0V
GND–0.3
0.2 VCC
GND–0.3
0.2 VCC
1.1
V
5.5V
GND–0.3
0.2 VCC
GND–0.3
0.2 VCC
1.6
V
Output
High
Voltage
(Low-EMI
Mode)
Output
High
Voltage
Output Low
Voltage
(Low-EMI
Mode)
Output Low
Voltage
3.0V
VCC–0.4
VCC–0.4
3.1
V
IOH = –0.5 mA
5.0V
VCC–0.4
VCC–0.4
4.8
V
IOH = –0.5 mA
3.0V
VCC–0.4
VCC–0.4
3.1
V
IOH = –2.0 mA
3
5.5V
VCC–0.4
VCC–0.4
4.8
V
IOH = –2.0 mA
3
Sym
Parameter
VCC
VCH
Clock Input
High
Voltage
VCL
VIH
VIL
VOH
VOH1
VOL
VOL1
TA =
–40°C to +105°C
Clock Input
Low
Voltage
1
Units Conditions
Notes
Driven by
External Clock
Generator
Driven by
External Clock
Generator
Driven by
External Clock
Generator
Driven by
External Clock
Generator
3.0V
0.6
0.6
0.2
V
IOL = 1.0 mA
5.0V
0.4
0.4
0.1
V
IOL = 1.0 mA
3.0V
0.6
0.6
0.2
V
IOL = +4.0 mA
3
5.5V
0.4
0.4
0.1
V
IOL = +4.0 mA
3
Notes:
1. The VCC voltage specification of 3.0V guarantees 3.3V ±0.3V with typicals at VCC = 3.3V, and the VCC voltage
specification of 5.5V guarantees 5.0V ±0.5V with typicals at VCC = 5.0V.
2. Typicals are at VCC = 5.0V and 3.3V.
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at VCC.
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0ºC to 70ºC (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region.
12. –40˚C to 150˚C (extended temperature).
DS007601-Z8X0499
PRELIMINARY
9
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
DC ELECTRICAL CHARACTERISTICS (Continued)
Table 5. DC Characteristics (Continued)
TA =
0°C to +70°C
1
Max
Typical2
@25°C
1.2
1.2
0.3
V
IOL = +6 mA
3
1.2
1.2
0.4
V
IOL = +12 mA
3
.8 VCC
VCC
1.8
V
4
VCC
.8 VCC
VCC
2.6
V
4
GND–0.3
0.2 VCC
GND–0.3
0.2 VCC
1.1
V
4
GND–0.3
0.2 VCC
GND–0.3
0.2 VCC
1.6
V
4
Sym
Parameter
VCC
VOL2
Output Low
Voltage
3.0V
5.5V
Reset Input
High
Voltage
Reset Input
Low
Voltage
Reset
Output Low
Voltage
Comparator
Input Offset
Voltage
Input
Leakage
3.0V
.8 VCC
VCC
5.5V
.8 VCC
3.0V
5.5V
VRH
VRl
VOLR
VOFFSET
IIL
TA =
–40°C to +105°C
Min
Max
Min
Units Conditions
3.0V
0.6
0.6
0.3
V
IOL = +1.0 mA
4
5.5V
0.6
0.6
0.3
V
IOL = +1.0 mA
4
3.0V
5.5V
25
25
25
25
10
10
mV
mV
5
5
3.0V
–1
2
–1
2
0.004
µA
VIN = 0V, VCC
5.5V
–1
2
–1
2
0.004
µA
VIN = 0V, VCC
Output
Leakage
3.0V
–1
1
–1
2
0.004
µA
VIN = 0V, VCC
5.5V
–1
1
–1
2
0.004
µA
VIN = 0V, VCC
IIR
Reset Input
Current
–20
–20
Supply
Current
–130
–180
20
25
15
20
–18
–18
ICC
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
–130
–180
20
25
15
20
–60
–85
7
20
5
15
µA
µA
mA
mA
mA
mA
@ 16 MHz
@ 16 MHz
@ 12 MHz
@ 12 MHz
IOL
Notes
6
6
6
6
Notes:
1. The VCC voltage specification of 3.0V guarantees 3.3V ±0.3V with typicals at VCC = 3.3V, and the VCC voltage
specification of 5.5V guarantees 5.0V ±0.5V with typicals at VCC = 5.0V.
2. Typicals are at VCC = 5.0V and 3.3V.
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at VCC.
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0ºC to 70ºC (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region.
12. –40˚C to 150˚C (extended temperature).
10
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Table 5. DC Characteristics (Continued)
TA =
0°C to +70°C
Max
Typical2
@25°C
4.5
4.5
2.0
5.5V
8
8
3.7
3.0V
3.4
3.4
1.5
5.5V
7.0
7.0
2.9
3.0V
8
8
2
5.5V
10
10
4
3.0V
500
600
310
5.5V
800
1000
600
Sym
Parameter
VCC1
ICC1
Standby
Current
(HALT
Mode)
3.0V
ICC2
VICR
IALL
IALH
Standby
Current
(STOP
Mode)
Input
Common
Mode
Voltage
Range
Auto Latch
Low
Current
Auto Latch
High
Current
TA =
–40°C to +105°C
Min
Max
Min
Units Conditions
mA VIN = 0V, VCC
@ 16 MHz
mA VIN = 0V, VCC
@ 16 MHz
mA Clock Divideby-16 @ 16
MHz
mA Clock Divideby-16 @ 16
MHz
µA VIN = 0V, VCC
WDT is not
Running
µA VIN = 0V, VCC
WDT is not
Running
µA VIN = 0V, VCC
WDT is
Running
µA VIN = 0V, VCC
WDT is
Running
Notes
6
6
6
6
7,8
7,8
7,8,9
7,8,9
3.0V
0
VCC–1.0V
0
VCC–1.5V
V
5
5.5V
0
VCC–1.0V
0
VCC–1.5V
V
5
3.0V
0.7
8
0.7
10
3
µA
0V < VIN < VCC
10
5.5V
1.4
15
1.4
20
5
µA
0V < VIN < VCC
10
3.0V
–0.6
–5
–0.6
–7
–3
µA
0V < VIN < VCC
10
5.5V
–1.0
–8
–1.0
–10
–6
µA
0V < VIN < VCC
10
Notes:
1. The VCC voltage specification of 3.0V guarantees 3.3V ±0.3V with typicals at VCC = 3.3V, and the VCC voltage
specification of 5.5V guarantees 5.0V ±0.5V with typicals at VCC = 5.0V.
2. Typicals are at VCC = 5.0V and 3.3V.
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at VCC.
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0ºC to 70ºC (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region.
12. –40˚C to 150˚C (extended temperature).
DS007601-Z8X0499
PRELIMINARY
11
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
DC ELECTRICAL CHARACTERISTICS (Continued)
Table 5. DC Characteristics (Continued)
TA =
0°C to +70°C
Sym
Parameter
VLV
VCC Low
Voltage
Protection
Voltage
VCC
1
Min
2.2
Max
TA =
–40°C to +105°C
Min
Max
Typical2
@25°C
2.0
3.3
2.8
3.1
2.8
Units Conditions
V
4 MHz max
Int. CLK Freq.
6 MHz max
Int. CLK Freq.
Notes
11,12
9,11
Notes:
1. The VCC voltage specification of 3.0V guarantees 3.3V ±0.3V with typicals at VCC = 3.3V, and the VCC voltage
specification of 5.5V guarantees 5.0V ±0.5V with typicals at VCC = 5.0V.
2. Typicals are at VCC = 5.0V and 3.3V.
3. Standard Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at VCC.
8. Clock must be forced Low, when XTAL 1 is clock-driven and XTAL2 is floating.
9. 0ºC to 70ºC (standard temperature).
10. Auto Latch (Mask Option) selected.
11. The VLV voltage increases as the temperature decreases and overlaps lower VCC operating region.
12. –40˚C to 150˚C (extended temperature).
12
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS
External I/O or Memory READ and WRITE Timing
R/W
13
12
19
Port 0, DM
16
Port 1
20
3
18
D7–D0 IN
A7–A0
2
1
9
AS
8
11
4
5
DS
(Read)
6
17
10
Port1
D7–D0 OUT
A7–A0
14
15
7
DS
(Write)
Figure 8. External I/O or Memory READ and WRITE Timing
DS007601-Z8X0499
PRELIMINARY
13
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS (Continued)
Table 6. External I/O or Memory READ and WRITE Timing (C44/C45/C46 Only)
(SCLK/TCLK = XTAL/2)
TA = –0ºC to 70ºC
12 MHz
No
Symbol
Parameter
1
TdA(AS)
Address Valid to AS
Rise Delay
2
TdAS(A)
AS Rise to Address
Float Delay
3
TdAS(DR)
AS Rise to Read
Data Req’d Valid
4
TwAS
AS Low Width
5
TdAS(DS)
Address Float to DS
Fall
6
TwDSR
DS (Read) Low
Width
7
TwDSW
DS (WRITE) Low
Width
8
TdDSR(DR)
DS Fall to Read Data
Req’d Valid
9
ThDR(DS)
Read Data to DS
Rise Hold Time
10
TdDS(A)
DS Rise to Address
Active Delay
11
TdDS(AS)
DS Rise to AS Fall
Delay
12
TdR/W(AS)
R/W Valid to AS Rise
Delay
13
TdDS(R/W)
DS Rise to R/W Not
Valid
14
TdDW(DSW) WRITE Data Valid to
DS Fall (WRITE)
Delay
TdDS(DW) DS Rise to WRITE
Data Not Valid Delay
15
16
TdA(DR)
Address Valid to
Read Data Req’d
Valid
VCC
1
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
Min
Max
35
35
45
45
16 MHz
Min
Max
25
25
35
35
250
250
55
55
0
0
200
200
110
110
TA = –40ºC to +105ºC
12 MHz
Min
35
35
45
45
180
180
40
40
0
0
135
135
80
80
150
150
Max
16 MHz
Min
25
25
35
35
250
250
55
55
0
0
200
200
110
110
75
75
180
180
40
40
0
0
135
135
80
80
150
150
75
75
0
0
45
55
30
45
45
45
45
45
55
55
0
0
50
50
35
35
25
25
35
35
25
25
0
0
45
55
30
45
45
45
45
45
55
55
0
0
50
50
35
55
25
25
35
35
25
25
45
45
35
35
45
45
35
35
310
310
230
230
Max Units Notes
310
310
230
230
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
2
2
2,3
2
2
2
2,3
2,3
2,3
2,3
2,3
2,3
2
2
2
2
2
2
2
2
2
2
2
2
ns
ns
ns
ns
2
2
2,3
2,3
Notes:
1. The VCC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V
± 0.5V.
2. Timing numbers provided are for minimum TpC.
3. When using extended memory timing add 2 TpC.
14
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Table 6. External I/O or Memory READ and WRITE Timing (C44/C45/C46 Only)
(SCLK/TCLK = XTAL/2) (Continued)
TA = –0ºC to 70ºC
12 MHz
No
Symbol
Parameter
17
TdAS(DS)
AS Rise to DS Fall
Delay
18
TdDM(AS)
DM Valid to AS Fall
Delay
19
TdDs(DM)
DS Rise to DM Valid
Delay
20
ThDS(AS)
DS Valid to Address
Valid Hold Time
VCC1 Min
3.0
5.5
3.0
5.5
3.0
5.5
3.0
5.5
65
65
35
35
45
45
45
45
Max
16 MHz
Min
45
45
30
30
35
35
35
35
Max
TA = –40ºC to +105ºC
12 MHz
Min
65
65
35
35
45
45
45
45
Max
16 MHz
Min
45
45
30
30
35
35
35
35
Max Units Notes
ns
ns
ns
ns
ns
ns
ns
ns
2
2
2
2
2
2
2
2
Notes:
1. The VCC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V
± 0.5V.
2. Timing numbers provided are for minimum TpC.
3. When using extended memory timing add 2 TpC.
DS007601-Z8X0499
PRELIMINARY
15
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS (Continued)
Additional Timing Diagram
3
1
Clock
2
7
2
3
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 9. Additional Timing
16
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Table 7. Additional Timing (SCLK/TCLK = XTAL/2)
TA = 0ºC to +70ºC
12 MHz
No Symbol
Parameter
1
TpC
Input Clock
Period
2
TrC,TfC
3
TwC
Clock Input
Rise & Fall
Times
Input Clock
Width
4
TwTinL
Timer Input
Low Width
5
TwTinH
Timer Input
High Width
6
TpTin
Timer Input
Period
7
TrTin,
TfTin
Timer Input
Rise & Fall
Timer
Int. Request
Low Time
8A TwIL
8B TwIL
Int. Request
Low Time
9
Int. Request
Input High
Time
Stop-Mode
Recovery
Width Spec
Oscillator
Startup Time
TwIH
10 Twsm
11 Tost
1
VCC
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
TA = –40ºC to +105ºC
16 MHz
12 MHz
16 MHz
Min
Max
Min
Max
Min
Max
Min
83
83
250
250
DC
DC
DC
DC
15
15
62.5
62.5
250
250
DC
DC
DC
DC
15
15
83
83
250
250
DC
DC
DC
DC
15
15
62.5
62.5
250
250
2,3,4
2,3,4
2,3
2,3
2,3
2,3
ns
ns
ns
ns
ns
ns
2,3,4
2,3,4
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
100
70
5TpC
5TpC
5TpC
5TpC
100
70
5TpC
5TpC
5TpC
5TpC
100
70
5TpC
5TpC
5TpC
5TpC
100
70
5TpC
5TpC
5TpC
5TpC
ns
ns
2,3,5
2,3,5
2,3,6
2,3,6
2,3,5
2,3,5
3.0V
5.5V
12
12
12
12
12
12
12
12
ns
ns
7
7
5TpC
5TpC
100
100
31
31
125
125
100
70
5TpC
5TpC
8TpC
8TpC
ns
ns
ns
ns
ns
ns
41
41
125
125
100
70
5TpC
5TpC
8TpC
8TpC
100
100
41
41
125
125
100
70
5TpC
5TpC
8TpC
8TpC
DC
DC
DC
DC
15
15
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
31
31
125
125
100
70
5TpC
5TpC
8TpC
8TpC
Max Units Notes D1,D0
100
100
5TpC
5TpC
5TpC
5TpC
100
100
5TpC
5TpC
ns
ns
7,8
7,8
Notes:
1. The VCC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V
± 0.5V.
2. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
3. SMR D1 = 0.
4. Maximum frequency for external XTAL clock is 4 MHz when using low-EMI Oscillator mode PCON Reg.D7 = 0.
5. Interrupt request via Port 3 (P31–P33).
6. Interrupt request via Port 3 (P30).
7. SMR–D5 = 1, POR STOP Mode Delay is on.
8. For RC and LC oscillator, and for oscillator driven by clock driver.
9. Register WDTMR.
DS007601-Z8X0499
PRELIMINARY
17
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS (Continued)
Table 7. Additional Timing (SCLK/TCLK = XTAL/2) (Continued)
TA = 0ºC to +70ºC
12 MHz
No Symbol
Parameter
12 Twdt
Watch-Dog
Timer Delay
Timer before
time-out
13 TPOR
Power-On
Reset Delay
1
VCC
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
Min
7
3.5
14
7
28
14
112
56
3
1.5
TA = –40ºC to +105ºC
16 MHz
Max
Min
24
13
7
3.5
14
7
28
14
112
56
3
1.5
12 MHz
Max
Min
24
13
7
3.5
14
7
28
14
112
56
3
1
16 MHz
Max
Min
25
14
7
3.5
14
7
28
14
112
56
3
1
Max Units Notes D1,D0
25
14
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
9
9
9
9
9
9
9
9
0,0
0,0
0,1
0,1
1,0
1,0
1,1
1,1
Notes:
1. The VCC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V
± 0.5V.
2. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
3. SMR D1 = 0.
4. Maximum frequency for external XTAL clock is 4 MHz when using low-EMI Oscillator mode PCON Reg.D7 = 0.
5. Interrupt request via Port 3 (P31–P33).
6. Interrupt request via Port 3 (P30).
7. SMR–D5 = 1, POR STOP Mode Delay is on.
8. For RC and LC oscillator, and for oscillator driven by clock driver.
9. Register WDTMR.
18
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Table 8. Additional Timing
(Divide-By-One Mode, SCLK/TCLK = XTAL)
VCC1
No
Symbol Parameter
1
TpC
Input Clock Period
2
TrC,TfC
Clock Input Rise
& Fall Times
3
TwC
Input Clock Width
4
TwTinL
Timer Input Low Width
5
TwTinH
Timer Input High Width
6
TpTin
Timer Input Period
7
TrTin,
TfTin
Timer Input Rise
& Fall Timer
8A
TwIL
Int. Request Low Time
8B
TwIL
Int. Request Low Time
9
TwIH
Int. Request Input
High Time
10
Twsm
Stop-Mode Recovery
Width Spec
11
Tost
Oscillator Startup Time
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
TA = 0ºC to
+70ºC
TA = 40ºC to
+105ºC
8 MHz
Min
Max
8 MHz
Min
Max
250
250
125
125
250
250
125
125
DC
DC
DC
DC
25
25
125
125
62
62
100
70
3TpC
3TpC
4TpC
4TpC
Units
Notes
DC
DC
DC
DC
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
100
ns
ns
ns
ns
2,3,4
2,3,4
2,3
2,3
2,3
2,3
2,3,4
2,3,4
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3,5
2,3,5
2,3,6
2,3,6
2,3,5
2,3,5
7
7
7,8
7,8
125
125
62
62
100
70
3TpC
3TpC
4TpC
4TpC
100
100
100
70
3TpC
3TpC
3TpC
3TpC
12
12
100
70
3TpC
3TpC
3TpC
2TpC
12
12
5TpC
5TpC
ns
ns
5TpC
5TpC
Notes:
1. The VCC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the VCC voltage specification of 5.5V guarantees 5.0V
± 0.5V.
2. Timing Reference uses 0.7 VCC for a logic “1” and 0.2 VCC for a logic “0”.
3. SMR D1 = 0.
4. Maximum frequency for external XTAL clock is 4 MHz when using low-EMI Oscillator mode PCON Reg.D7 = 0.
5. Interrupt request via Port 3 (P31–P33).
6. Interrupt request via Port 3 (P30).
7. SMR–D5 = 1, POR STOP Mode Delay is on.
8. For RC and LC oscillator, and for oscillator driven by clock driver.
DS007601-Z8X0499
PRELIMINARY
19
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
AC ELECTRICAL CHARACTERISTICS (Continued)
Handshake Timing Diagrams
Data In Valid
Data In
Next Data In Valid
2
1
3
Delayed DAV
DAV
(Input)
6
5
4
RDY
(Output)
Delayed RDY
Figure 10. Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
DAV
(Output)
Delayed DAV
8
9
11
10
RDY
(Input)
Delayed
RDY
Figure 11. Output Handshake Timing
20
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Table 9. Handshake Timing1
TA = 0°C to +70°C
12 MHz
2
No Symbol
Parameter
VCC
1
TsDI(DAV)
Data In Setup Time
2
ThDI(RDY)
Data In Hold Time
3
TwDAV
Data Available Width
4
TdDAVI(RDY)
DAV Fall to RDY Fall
Delay
5
TdDAVId(RDY) DAV Out to DAV Fall
Delay
6
RDY0d(DAV)
RDY Rise to DAV Fall
Delay
7
TdD0(DAV)
Data Out to DAV Fall
Delay
8
TdDAV0(RDY)
DAV Fall to RDY Fall
Delay
9
TdRDY0(DAV)
RDY Fall to DAV Rise
Delay
10
TwRDY
RDY Width
11
TdRDY0d(DAV) RDY Rise to DAV Fall
Delay
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
3.0V
5.5V
16 MHz
TA = –40°C to +105°C
12 MHz
16 MHz
Min Max Min Max Min Max Min Max
0
0
0
0
155
110
0
0
0
0
155
110
0
0
120
80
0
0
0
0
155
110
0
0
120
80
0
0
42
42
0
0
0
0
31
31
0
0
160
115
110
80
0
0
120
80
0
0
42
42
0
0
160
115
110
80
110
80
0
0
0
0
155
110
0
0
31
31
0
0
160
115
110
80
110
80
0
0
120
80
160
115
110
80
110
80
110
80
Data
Direction
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Note:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. The VCC voltage specification of 3.0V guarantees 3.3V ±0.3V. The VCC voltage specification of 5.5V guarantees 5.0V ±0.5V.
DS007601-Z8X0499
PRELIMINARY
21
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN FUNCTIONS
R/RL (input, active Low). The ROM/ROMless pin, when
connected to GND, disables the internal ROM and forces
the device to function as a ROMless Z8. (Not available for
devices in the 28-pin package.)
Notes: When left unconnected or pulled High to VCC, the
device functions normally as a Z8 ROM version.
When using in ROM Mode in a high-EMI (noisy)
environment, the ROMless pins should be connected
directly to VCC.
DS (output, active Low). Data Strobe is activated one
time for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of DS.
For WRITE operations, the falling edge of DS indicates that
output data is valid. (Not available for devices in the 28pin package.)
22
AS (output, active Low). Address Strobe is pulsed one
time at the beginning of each machine cycle for external
memory transfer. Address output is from Port 0/Port 1 for
all external programs. Memory address transfers are valid
at the trailing edge of AS. Under program control, AS is
placed in the high-impedance state along with Ports 0 and
1, Data Strobe, and READ/WRITE. (Not available for devices in the 28-pin package.)
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, or RC net-
work, or an external single-phase clock to the on-chip oscillator input.
XTAL2 Crystal 2 (time-based output). This pin connects
a parallel-resonant crystal, ceramic resonant, LC, or RC network to the on-chip oscillator output.
R/W (output, WRITE Low). The READ/WRITE signal is
Low when the Z8 is writing to the external program or data
memory. (Not available for devices in the 28-pin package.)
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Port 0 (P00–P07). Port 0 is an 8-bit, bidirectional, CMOScompatible port. These eight I/O lines are configured under
software control as a nibble I/O port (P03–P00 input/output
and P07–P04 input/output), or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble-programmed as outputs and can be globally programmed as either push-pull or open-drain. LowEMI output buffers can be globally programmed by the software. Port 0 is placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control DAV0 and RDY0. Handshake signal direction
is dictated by the I/O direction (input or output) of Port 0
of the upper nibble P04–P07. The lower nibble must indicate the same direction as the upper nibble.
For external memory references, Port 0 provides address
bits A11–A8 (lower nibble) or A15–A8 (lower and upper
nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port
0 can be programmed independently as I/O while the lower
nibble is used for addressing. If one or both nibbles are required for I/O operation, they are configured by writing to
the Port 0 mode register.
In ROMless mode, after a hardware RESET, Port 0 is configured as address lines A15–A8, and extended timing is set
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this extended timing mode. (In ROM mode, Port 0 is defined as
input after RESET.)
Port 0 can be placed in a high-impedance state along with
Port 1, AS, DS and R/W, allowing the Z8 to share common resources in multiprocessor and DMA applications (Figure 12).
4
Port 0
(I/O or A15–A8)
Z8
4
Handshake Controls
DAV0 and RDY0
(P32 and P35)
Open-Drain
Pull-Up
Transistor Enable
(Mask Option)
OE
PAD
Out
1.5
2.3 Hysteresis @ VCC = 5.0V
In
Auto Latch
(mask option)
R ≈ 500KΩ
Figure 12. Port 0 Configuration
DS007601-Z8X0499
PRELIMINARY
23
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN FUNCTIONS (Continued)
Port 1 (P17–P10). Port 1 is an 8-bit, bidirectional, CMOS-
compatible port (Figure 13), with multiplexed Address
(A7–A0) and Data (D7–D0) ports. For the ROM device,
these eight I/O lines are programmed as inputs or outputs,
or can be configured under software control as an Address/Data port for interfacing external memory. The input
buffers are Schmitt-triggered and byte-programmed as outputs and can be globally programmed as either push-pull
or open-drain. Low-EMI output buffers can be globally programmed by the software.
Note: Port 1 is not available on the devices in the 28-pin package, and P01M Register must set Bit D4,D3 as 00. LowEMI mode is not supported on the emulator for Port1.
PCON register D4 must be 1.
8
Port 1 may be placed under handshake control. In this configuration, Port 3, lines P33 and P34 are used as the handshake controls RDY1 and DAV1 (Ready and Data Available). Memory locations greater than the internal ROM
address are referenced through Port 1, except for Z86C46.
To interface external memory, Port 1 must be programmed
for the multiplexed Address/Data mode. If more than 256
external locations are required, Port 0 outputs the additional
lines.
Port 1 can be placed in the high-impedance state along with
Port 0, AS, DS, and R/W, allowing the Z8 to share common
resources in multiprocessor and DMA applications.
Port 1
(I/O or AD7–AD0)
Z8
Handshake Controls
DAV1 and RDY1
(P33 and P34)
Pull-Up
Transistor Enable
(Mask Option)
Open Drain
OE
PAD
Out
1.5
2.3 Hysteresis @ VCC = 5.0V
In
Auto Latch
(mask option)
R ≈ 500 KΩ
Figure 13. Port 1 Configuration
24
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Port 2 (P27–P20). Port 2 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines are configured
under software control as an input or output, independently.
Port 2 is always available for I/O operation. The input buffers are Schmitt-triggered. Bits programmed as outputs may
be globally programmed as either push-pull or open-drain.
Low-EMI output buffers can be globally programmed by
the software.
Port 2 may be placed under handshake control. In this Handshake Mode, Port 3 lines P31 and P36 are used as the handshake controls lines DAV2 and RDY2. The handshake signal
assignment for Port 3 lines P31 and P36 is dictated by the direction (input or output) assigned to Bit 7, Port 2 (Figure 14).
Port 2 (I/O)
Z8
Handshake Controls
DAV2 and RDY2
(P31 and P36)
Open Drain
Pull-Up
Transistor Enable
(Mask Option)
OE
PAD
Out
1.5
2.3 Hysteresis @ VCC = 5.0V.
In
Auto Latch
(mask option)
R ≈ 500 KΩ
Figure 14. Port 2 Configuration
DS007601-Z8X0499
PRELIMINARY
25
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN FUNCTIONS (Continued)
Port 3 (P37–P30). Port 3 is an 8-bit, CMOS-compatible
port, with four fixed inputs (P33–P30) and four fixed outputs (P34–P37). It is configured under software control for
Input/Output, Counter/Timers, interrupt, port handshake,
and Data Memory functions. Port 3, bit 0 input is Schmitttriggered, and pins P31, P32, and P33 are standard CMOS
inputs (no Auto Latches). Pins P34, P35, P36, P37 are pushpull output lines. Low-EMI output buffers can be globally
programmed by the software.
Two onboard comparators can process analog signals on
P31 and P32 with reference to the voltage on P33. The analog function is enabled by programming Port 3 Mode Register (P3M bit 1). For Interrupt functions, Port 3, bit 0 and
pin 3 are falling edge interrupt inputs. P31 and P32 are programmable as rising, falling, or both edge triggered interrupts (IRQ register Bits 6 and 7). P33 is the comparator reference voltage input when in Analog mode. Access to
Counter/Timers 1 is made through P31 (TIN) and P36
(TOUT). Handshake lines for Ports 0, 1, and 2 are available
on P31 through P36.
Port 3 also provides the following control functions: handshake for Ports 0, 1, and 2 (DAV and RDY); four external
interrupt request signals (IRQ3–IRQ0); timer input and output signals (TIN and TOUT); Data Memory Select (DM, see
Table 10 and Figure 15).
P34 output can be software-programmed to function as a
Data Memory Select (DM). The Port 3 mode register (P3M)
Bit D3,D4 selects this function. When accessing external
Data Memory, the P34 goes active Low; when accessing
external Program Memory, the P34 goes High.
An onboard UART (ASCI) can be enabled by software by
setting the RE and TE bits of the ASCI Control Register A
(CNTLA). When enabled, P30 is the receive input and P37
is the transmit output.
Table 10. Port 3 Pin Assignments
Pin
I/O
P30
P31
IN
IN
P32
P33
P34
P35
P36
IN
IN
OUT
OUT
OUT
P37
OUT
CTC1
TIN
Analog
Int.
AN1
IRQ3
IRQ2
AN2
REF
AN1–OUT
IRQ0
IRQ1
P0 HS
P1 HS
P2 HS
Ext
UART
RX
D/R
D/R
D/R
R/D
DM
R/D
TOUT
R/D
AN2–OUT
TX
Notes:
HS = Handshake Signals
D = DAV
R = RDY
Comparator Inputs and Outputs. Port 3, pins P31 and
P32 each feature a comparator front end. The comparator
reference voltage, pin P33, is common to both comparators.
In analog mode, the P31 and P32 are the positive inputs to
the comparators and P33 is the reference voltage supplied
to both comparators. In digital mode, pin P33 can be used
as a P33 register input or IRQ1 source. P34 and P37 outputs
Note: The user must add a two-NOP delay after selecting the
P3M bit D1 to 1 before the comparator output is valid.
IRQ0, IRQ1, and IRQ2 should be cleared in the IRQ register when the comparator is enabled or disabled.
the comparator outputs by software-programming the
PCON Register Bit D0 to 1 (see Figure 16).
26
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
P30
P31
P32
P33
Z8
P34
Port 3
(I/O or Control)
P35
P36
P37
Auto Latch
(mask option)
R ≈ 500KΩ
P30 Data
Latch IRQ3
P30
R247 = P3M
D1
1 = Analog
0 = Digital
DIG.
P31 (AN1)
IRQ2,TIN, P31 Data Latch
+
AN.
–
P32 (AN2)
IRQ0, P32 Data Latch
+
P33 (REF)
–
IRQ1, P33 Data Latch
From Stop-Mode
Recovery Source
Figure 15. Port 3 Configuration
DS007601-Z8X0499
PRELIMINARY
27
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PIN FUNCTIONS (Continued)
P34
P34 OUT
P31
PAD
+
–
REF (P33)
P37
P37 OUT
P32
PAD
+
–
REF (P33)
PCON
D0
0 P34, P37 Standard Output
1 P34, P37 Comparator Output
Figure 16. Port 3 Configuration
Auto Latch. The Auto Latch places valid CMOS levels on
all CMOS inputs (except P33–P31) that are not externally
driven. Whether this level is 0 or 1 cannot be determined.
A valid CMOS level, rather than a floating node, reduces
excessive supply current flow in the input buffer. Auto
Latches are available on Port 0, Port 1, Port 2, and P30.
There are no Auto Latches on P31, P32, and P33.
Note: Deletion of all Port Auto Latches is available as a ROM
Mask option. The Auto Latch Delete option is selected
by the customer when the ROM code is submitted.
RESET (input, active Low). Initializes the MCU. Reset is
accomplished either through Power-On Reset, Watch-Dog
Timer reset, Stop-Mode Recovery, or external reset. During
Power-On Reset and Watch-Dog Reset, the internally-generated reset is driving the RESET pin Low for the POR time.
Any devices driving the RESET line must be open-drain to
avoid damage from a possible conflict during RESET con-
28
ditions. RESET depends on oscillator operation to achieve
full reset conditions, except for conditions wherein a WDT
reset is permanently enabled. Pull-up is provided internally.
Note: The RESET pin is not available on devices in the 28-pin
package.
After the POR time, RESET is a Schmitt-triggered input.
During the RESET cycle, DS is held active Low while AS
cycles at a rate of TPC/2. Program execution begins at location 000Ch, after the RESET is released. For Power-On
Reset, the reset output time is TPOR ms.
When program execution begins, AS and DS toggles only
for external memory accesses. The Z8 does not reset
WDTMR, SMR, P2M, PCON, and P3M registers on a StopMode Recovery operation or from a WDT reset out of STOP
mode.
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION
The Z8 MCU incorporates the following special functions
to enhance the standard Z8® architecture to provide the user
with increased design flexibility.
RESET. The device is reset in one of the following condi-
tions:
•
•
•
•
•
Power-On Reset
65535
16383/32767
16382/32766
Location of
First Byte of
Instruction
Executed
After RESET 12
Watch-Dog Timer
Stop-Mode Recovery Source
External/Internal
ROM and RAM
External Reset
On-Chip
ROM
11
IRQ5
10
IRQ5
9
IRQ4
8
IRQ4
7
IRQ3
6
IRQ3
5
IRQ2
4
IRQ2
3
IRQ1
2
IRQ1
1
IRQ0
0
IRQ0
Low Voltage Recovery
Auto Power-On Reset circuitry is built into the Z8, eliminating the requirement for an external reset circuit to reset
upon power-up. The internal pull-up resistor is on the Reset
pin, so a pull-up resistor is not required; however, in a highEMI (noisy) environment, it is recommended that a small
value pull-up resistor be used.
Interrupt
Vector
(Lower Byte)
Note: The RESET pin is not available on devices in the 28-pin
package.
Program Memory. The first 12 bytes of program memory
are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available
interrupts. For ROM mode, address 12 to address 65535
(C36/C46)/32767 (C35/C45)/16383 (C34/C44) consists
of on-chip mask-programmed ROM. The Z86C44/C45 can
access external program and data memory from addresses
16384/32768 to 65535.
The 65535 (C36/C46)/ 32767 (C35/C45)/ 16383
(C34/C44) program memory is mask programmable. A
ROM protect feature prevents dumping of the ROM contents by inhibiting execution of LDC, LDCI, LDE, and LDEI
instructions to Program Memory in external program
mode. ROM look-up tables can be used with this feature.
The ROM Protect option is mask-programmable, to be selected by the customer when the ROM code is submitted.
DS007601-Z8X0499
Interrupt
Vector
(Upper Byte)
Figure 17. Program Memory Map
for Z86C34/35/44/45
Data Memory (DM). The ROMless version can address up
to 64 KB of external data memory. External data memory
may be included with, or separated from, the external program memory space. DM, an optional I/O function that can
be programmed to appear on pin P34, is used to distinguish
between data and program memory space (Figure 18). The
state of the DM signal is controlled by the type of instruction
being executed. An LDC Op Code references PROGRAM
(DM inactive) memory, and an LDE instruction references
data (DM active Low) memory. The user must configure
Port 3 Mode Register (P3M) bits D3 and D4 for this mode.
This feature is not usable for devices in 28-pin package.
When used in ROM mode, the Z86C46 cannot access any
external data memory. The Z86C44/C45 can access exter-
PRELIMINARY
29
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
nal program and data memory from addresses
16384/32768 to 65535.
Expanded Register File (ERF). The Z8 register file is ex-
panded to allow for additional system control registers, and
for mapping of additional peripheral devices along with I/O
ports into the register address area. The Z8 register address
space R0 through R15 is implemented as 16 groups of 16
registers per group (Figure 19). These register groups are
65535
known as the Expanded Register File (ERF). Bits 7–4 of register RP select the working register group. Bits 3–0 of register RP select the expanded register group. Three system
configuration registers reside in the Expanded Register File
at Bank F (PCON, SMR, WDTMR). The rest of the Expanded Register is not physically implemented, and is open for
future expansion.
65535
External
Data
Memory
External
Data
Memory
16384/32768
16383/32767
NotAddressable
0
0
ROM Mode
ROMless Mode
Figure 18. Data Memory Map
30
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Z8® STANDARD CONTROL REGISTERS
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER
% FF
SPL
0
0
0
0
0
0
0
% FE
SPH
0
0
0
0
0
0
0
0
% FD
RP
0
0
0
0
0
0
0
0
% FC
FLAGS
U
U
U
U
U
U
U
U
% FB
IMR
0
U
U
U
U
U
U
U
% FA
IRQ
0
0
0
0
0
0
0
0
% F9
IPR
U
U
U
U
U
U
U
U
†
% F8
P01M
0
1
0
0
1
1
0
1
*
*
% F7
P3M
0
0
0
0
0
0
0
0
% F6
P2M
1
1
1
1
1
1
1
1
REGISTER POINTER
7
6
5
4
3
2
WorkingRegister
Group Pointer
1
0
Expanded Register
Group Pointer
Z8 Reg. File
%FF
%FO
% F5
PRE0
U
U
U
U
U
U
U
0
% F4
T0
U
U
U
U
U
U
U
U
% F3
PRE1
U
U
U
U
U
U
0
0
% F2
T1
U
U
U
U
U
U
U
U
% F1
TMR
0
0
0
0
0
0
0
0
% F0
Reserved
EXPANDED REG. GROUP (F)
REGISTER
*
*
%7F
**
Reserved
%0F
%00
*
% (F) 0F
WDTMR
% (F) 0E
Reserved
% (F) 0D
SMR2
% (F) 0C
Reserved
% (F) 0B
SMR
% (F) 0A
Reserved
% (F) 09
Reserved
% (F) 08
Reserved
% (F) 07
Reserved
% (F) 06
Reserved
% (F) 05
Reserved
% (F) 04
Reserved
% (F) 03
Reserved
% (F) 02
Reserved
% (F) 01
Reserved
% (F) 00
PCON
EXPANDED REG. GROUP(0)
REGISTER
Notes:
U = Unknown
†
For ROMless Reset condition: “10110110”.
*Will not be reset with a STOP-Mode Recovery.
**Will not be reset with a STOP-Mode Recovery, except bit D0.
X
Not available on 28-pin packages.
0
*
*
X
RESET CONDITION
U
U
U
0
1
1
0
1
U
U
U
U
U
U
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
0
RESET CONDITION
% (0) 03
P3
1
1
1
1
U
U
U
U
% (0) 02
P2
U
U
U
U
U
U
U
U
% (0) 01
P1
U
U
U
U
U
U
U
U
% (0) 00
P0
U
U
U
U
U
U
U
U
Figure 19. Expanded Register File Architecture
Register File. The register file consists of four I/O port registers, 236 general-purpose registers and 15 control and status registers (R0–R3, R4–R239 and R240–R255, respectively), plus three system configuration registers in the
expanded register group. The instructions access registers
DS007601-Z8X0499
directly or indirectly through an 8-bit address field. As a result, a short, 4-bit register address can use the Register
Pointer (Figure 20). In the 4-bit mode, the register file is
divided into 16 working register groups, each occupying 16
PRELIMINARY
31
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
continuous locations. The Register Pointer addresses the
starting location of the active working register group.
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Group
Working Register Group
Default setting after RESET = 00000000
Figure 20. Register Pointer
r7 r6 r5 r4
r3 r2 r1 r0
R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
Register Group F
R15 to R0
F0
7F
70
6F
60
5F
50
4F
40
3F
30
2F
Specified Working
Register Group
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register
20
1F
10
0F
Register Group 1
R15 to R0
Register Group 0
R15 to R4
I/O Ports
R3 to R0
00
Figure 21. Register Pointer—Detail
32
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers keep
their most recent value after any RESET, as long as the RESET occurs in the VCC voltage-specified operating range.
These do not keep their most recent state from a Low Voltage Protection (VLV) RESET if the VCC drops below 1.8V.
Note: Register Bank E0–EF is only accessed through working
register and indirect addressing modes.
RAM Protect. The upper portion of the RAM’s address
spaces %80F to %EF (excluding the control registers) are
protected from writing. The RAM Protect bit option is
mask-programmable and is selected by the customer when
the ROM code is submitted. After the mask option is selected, the user activates this feature from the internal ROM
code to turn off/on the RAM Protect by loading either a 0
or 1 into the IMR register, bit D6. A 1 in D6 enables RAM
Protect.
Stack. The Z8 internal register file is used for the stack. The
16-bit Stack Pointer (R254–R255) is used for the external
stack, which can reside anywhere in the data memory for
ROMless mode. An 8-bit Stack Pointer (R255) is used for
the internal stack that resides within the 236 general-purpose registers (R4–R239). Stack Pointer High (SPH) is used
as a general-purpose register when using internal stack
only. The devices in 28-pin packages use the 8-bit stack
pointer (R255) for internal stack only.
DS007601-Z8X0499
Note: R254 and R255 are set to 00h after any RESET or StopMode Recovery.
Counter/Timers. There are two 8-bit programmable
counter/timers (T0–T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal
or external clock sources; however, the T0 prescaler is driv-
en by the internal clock only (Figure 22).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to
256) that is loaded into the counter. When the counter
reaches the end of the count, a timer interrupt request, IRQ4
(T0) or IRQ5 (T1), is generated.
The counters can be programmed to START, STOP, restart
to CONTINUE, or restart from the initial value. The counters
can also be programmed to STOP upon reaching 0 (single
pass mode) or to automatically reload the initial value and
continue counting (modulo–n continuous mode).
The counters, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal microprocessor clock divide-by-four, or an external signal input through Port 3. The Timer Mode register configures the
external timer input (P31) as an external clock, a trigger input that can be retriggerable or nonretriggerable, or as a gate
input for the internal clock. The counter/timers can be cascaded by connecting the T0 output to the input of T1. TIN
Mode is enabled by setting R243 PRE1 bit D1 to 0.
PRELIMINARY
33
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
OSC
Internal Data Bus
D1 (SMR)
Write
Write
Read
2
PRE0
Initial Value
Register
T0
Initial Value
Register
6-Bit
Down
Counter
8-bit
Down
Counter
T0
Current Value
Register
D0 (SMR)
16
÷4
IRQ4
Internal
Clock
÷2
TOUT
P36
External Clock
Clock
Logic
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
÷4
Internal Clock
Gated Clock
Triggered Clock
TIN P31
Write
Write
IRQ5
T1
Current Value
Register
Read
Internal Data Bus
Figure 22. Counter/Timer Block Diagram
Interrupts. The Z8 features six different interrupts from six
different sources. These interrupts are maskable, prioritized
(Figure 23) and the six sources are divided as follows: four
sources are claimed by Port 3 lines P33–P30, and two in
34
counter/timers (Table 11). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests.
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
Select
IRQ (D6, D7)
IRQ
IMR
6
IPR
Global
Interrupt
Enable
Interrupt
Request
PRIORITY
LOGIC
Vector Select
Figure 23. Interrupt Block Diagram
Table 11. Interrupt Types, Sources, and Vectors
Name
Source
Vector
Location
Comments
IRQ0
IRQ1,
IRQ2
DAV0, IRQ0
IRQ1
DAV2, IRQ2, TIN
0, 1
2, 3
4, 5
External (P32), Rise Fall Edge Triggered
External (P33), Fall Edge Triggered
External (P31), Rise Fall Edge Triggered
IRQ3
IRQ4
IRQ5
UART (ASCI)
T0
T1
6, 7
8, 9
10, 11
External (P30), Fall Edge Triggered
Internal
Internal
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. An interrupt machine cycle activates when an interrupt request is granted.
This action disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the
program memory vector location reserved for that interrupt.
DS007601-Z8X0499
All Z8 interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for
that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is polled to determine which of the interrupt requests require service.
PRELIMINARY
35
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
An interrupt resulting from AN1 maps to IRQ2, and an interrupt from AN2 maps to IRQ0. Interrupts IRQ2 and IRQ0
may be rising, falling, or both edge-triggered, and are programmable by the user. The software may poll to identify
the state of the pin. When in analog mode, the IRQ1 generates by the Stop-Mode Recovery source selected by SMR
Reg. bits D4, D3, D2, or SMR2 D1 or D0.
Programming bits for the Interrupt Edge Select are located
in the IRQ register (R250), bits D7 and D6. The configuration is indicated in Table 12.
Table 12. IRQ Register
IRQ
D7
0
0
1
1
Notes:
F = Falling Edge
R = Rising Edge
36
Interrupt Edge
D6
0
1
0
1
P31
F
F
R
R/F
P32
F
R
F
R/F
Clock. The Z8 on-chip oscillator features a high-gain, parallel-resonant amplifier for connection to a crystal, LC, RC,
ceramic resonator, or any suitable external clock source
(XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should
be AT-cut, 16 MHz maximum, with a series resistance (RS)
of less than or equal to 100 Ohms when counting from
1 MHz to 16 MHz.
The crystal should be connected across XTAL1 and XTAL2
using the vendor’s recommended capacitor values from
each pin directly to the device Ground pin to reduce groundnoise injection into the oscillator. The RC oscillator option
is mask-programmable on the Z8 and is selected by the customer at the time when the ROM code is submitted.
Notes: The RC option is available up to 8 MHz. The RC
oscillator configuration must be an external resistor
connected from XTAL1 to XTAL2, with a frequencysetting capacitor from XTAL1 to Ground (Figure 24).
For better noise immunity, the capacitors should be tied
directly to the device Ground pin (VSS).
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
XTAL1
C1
XTAL1
C1
VSS**
VSS**
C2
VSS**
L
XTAL2
VSS**
XTAL1
XTAL1
XTAL2
XTAL2
C1
R
XTAL2
C2
VSS**
Ceramic Resonator or
Crystal
C1, C2 = 47 pF TYP *
f = 8 MHz
LC
C1, C2 = 22 pF
RC
@ 5V VCC (TYP)
L = 130 uH *
f = 3 MHz *
C1 = 33 pF *
R = 1K *
f = 6 MHz *
External Clock
*Preliminary value including pin parasitics
**Device ground pin
Figure 24. Oscillator Configuration
Power-On-Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and the
oscillator circuit to stabilize before instruction execution
begins.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
1. Power fail to Power OK status.
a NOP (Op Code = FFH) immediately before the appropriate
sleep instruction. For example:
FF
6F
NOP
STOP
FF
7F
NOP
HALT
; clear the pipeline
; enter STOP mode
or
; clear the pipeline
; enter HALT Mode
2. Stop-Mode Recovery (if D5 of SMR = 1).
3. WDT time-out.
The POR time is specified as TPOR. Bit 5 of the Stop-Mode
Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC/LC
oscillators).
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The de-
vices are recovered by interrupts and are either externally
or internally generated. An interrupt request must be enabled and executed to exit HALT mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
In order to enter STOP (or HALT) mode, it is necessary to
first flush the instruction pipeline to avoid suspending execution in mid-instruction. Therefore, the user must execute
DS007601-Z8X0499
STOP. This instruction turns off the internal clock and external crystal oscillation. It also reduces the standby current
to 10 µA or less. The STOP mode is terminated by a RESET
only, either by WDT time-out, POR, SMR recovery, or external reset. As a result, the processor restarts the application program at address 000Ch. A WDT time-out in STOP
mode affects all registers the same as if a Stop-Mode Recovery occurred via a selected Stop-Mode Recovery source
except that the POR delay is enabled even if the delay is selected for disable.
Note: If a permanent WDT is selected, the WDT runs in all
modes and cannot be stopped or disabled if the onboard
RC oscillator is selected to drive the WDT.
Port Configuration Register (PCON). The PCON regis-
ter configures the ports individually; comparator output on
Port 3, open-drain on Port 0 and Port 1, low EMI on Ports
PRELIMINARY
37
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
0, 1, 2, and 3, and low-EMI oscillator. The PCON register
is located in the expanded register file at Bank F, location
00h (Figure 25).
Note: For emulator, this bit must be set to 1.
Low-EMI Port 2 (D5). Port 2 can be configured as a lowEMI port by resetting this bit (D5 = 0) or configured as a
Standard Port by setting this bit (D5 = 1). The default value
is 1.
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 1 Open Drain
1 Port 1 Push-pull Active*†
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
0 Port 0 Low EMI
1 Port 0 Standard*†
0 Port 1 Low EMI
1 Port 1 Standard*
Low-EMI Port 3 (D6). Port 3 can be configured as a lowEMI port by resetting this bit (D6 = 0) or configured as a
Standard Port by setting this bit (D6 = 1). The default value
is 1.
Low-EMI OSC (D7). This bit of the PCON Register controls the low-EMI noise oscillator. A 1 in this location configures the oscillator, DS, AS and R/W with standard drive,
while a 0 configures the oscillator, DS, AS and R/W with
low noise drive. The low-EMI mode reduces the drive of
the oscillator (OSC). The default value is 1.
0 Port 2 Low EMI
1 Port 2 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
*Default Setting After Reset
†
Must be set to one for devices
in 28-pin packages
Note: Maximum external clock frequency of 4 MHz when running in the low-EMI oscillator mode.
Low EMI Oscillator
0 Low EMI
1 Standard*
Figure 25. Port Configuration Register (PCON)
(WRITE ONLY)
Comparator Output Port 3 (D0). Bit 0 controls the comparator use in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port to
its standard I/O configuration. The default value is 0.
Port 1 Open-Drain (D1). Port 1 can be configured as an
open-drain by resetting this bit (D1 = 0) or configured as
push-pull active by setting this bit (D1 = 1). The default value is 1. The user must set D1 = 1 for devices in 28-pin pack-
ages.
Port 0 Open-Drain (D2). Port 0 can be configured as an
open-drain by resetting this bit (D2 = 0) or configured as
push-pull active by setting this bit (D2 = 1). The default value is 1.
Low-EMI Port 0 (D3). Port 0 can be configured as a lowEMI port by resetting this bit (D3 = 0) or configured as a
Standard Port by setting this bit (D3 = 1). The default value
is 1.
Low-EMI Port 1 (D4). Port 1 can be configured as a lowEMI port by resetting this bit (D4 = 0) or configured as a
Standard Port by setting this bit (D4 = 1). The default value
is 1. The user must set D4 = 1 for devices in 28-pin packages.
38
Low-EMI Emission. The Z8 can be programmed to operate
in a low-EMI emission mode in the PCON register. The oscillator and all I/O ports can be programmed as low-EMI
emission mode independently. Use of this feature results in:
•
•
The pre-drivers slew rate reduced to 10 ns (typical)
•
•
Low-EMI Oscillator
Low-EMI output drivers exhibit resistance of 200 Ohms
(typical)
Internal SCLK/TCLK = XTAL operation limited to a
maximum of 4 MHz–250 ns cycle time, when LOW
EMI OSCILLATOR is selected and system clock (SCLK
= XTAL, SMR REGISTER BIT D1 = 1)
Stop-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figures 26 and 27). All bits are
WRITE ONLY, except bit 7, which is READ ONLY. Bit 7
is a flag bit that is hardware set on the condition of STOP
recovery and RESET by a power-on cycle. Bit 6 controls
whether a low level or a high level is required from the recovery source. Bit 5 controls the reset delay after recovery.
Bits 2, 3, and 4, or the SMR register, specify the source of
the Stop-Mode Recovery signal. Bits 0 and 1 determine the
time-out period of the WDT. The SMR is located in Bank
F of the Expanded Register Group at address 0BH.
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The pur-
SMR (FH) 0B
pose of this control is to selectively reduce device power
consumption during normal processor execution ( SCLK
control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic). This bit is reset to D0
= 0 after a Stop-Mode Recovery.
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag (Read only)
0 POR*
1 Stop Recovery
External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock frequency divided by 2. The
SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1 = 1). Using this bit together with D7 of
PCON further helps lower EMI (that is, D7 (PCON) = 0, D1
(SMR) = 1). The default setting is 0. Maximum external
clock frequency is 4 MHz when SMR BIT D1 = 1 where
SCLK/TCLK = XTAL.
Stop-Mode Recovery Source (D2, D3, and D4). T h e s e
three bits of the SMR specify the wake-up source of the
STOP recovery (Figure 28 and Table 13). When the Stop-
Note: Not used in conjunction with SMR2 Source
* Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
Figure 26. Stop-Mode Recovery Register
(WRITE ONLY Except Bit D7, Which Is READ ONLY)
Mode Recovery Sources are selected in this register, then
SMR2 register bits D0,D1 must be set to 0.
Note: If the Port 2 pin is configured as an output, this output
level is read by the SMR circuitry.
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 27. Stop-Mode Recovery Register 2
(0F) DH: WRITE ONLY
DS007601-Z8X0499
PRELIMINARY
39
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
SMR2 D1 D0
0 0
VDD
SMR D4 D3 D2
0 0 0
VDD
P30
P31
P32
SMR D4
0
0
0
D3
0
1
1
D2 SMR D4 D3 D2
1
1 0 0
0
1
P33
SMR2 D1 D0
1 1
P20
P20
P23
P27
SMR D4 D3 D2
1 0 1
SMR D4 D3 D2
1 1 0
P20
P20
P23
P27
SMR2 D1 D0
1 1
SMR D4 D3 D2
1 1 1
P27
To POR
RESET
Stop-Mode Recovery Edge
Select (SMR)
To P33 Data
Latch and IRQ1
MUX
P33 From Pads
Digital/Analog Mode
Select (P3M)
Figure 28. Stop-Mode Recovery Source
Table 13. Stop-Mode Recovery Source
SMR:432
D4 D3 D2
Operation
Description of Action
wake up is selected, the Stop-Mode Recovery source must
be kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit
POR and/or external reset recovery
P30 transition
P31 transition (not in Analog Mode)
P32 transition (not in Analog Mode)
P33 transition (not in Analog Mode)
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
position indicates that a high level on any one of the recovery sources wakes the Z8 from STOP mode. A 0 indicates
low-level recovery. The default is 0 on POR (Figure 28).
This bit is used for either SMR or SMR2.
Stop-Mode Recovery Delay Select (D5). T h i s b i t , i f
High, enables the TPOR RESET delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the fast
Note: If the Port 2 pin is configured as an output, this output
level is read by the SMR2 circuitry.
0
0
0
0
1
1
1
1
40
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP mode. A 0 in this bit (cold) indicates
that the device resets by POR/WDT RESET. A 1 in this bit
(warm) indicates that the device awakens by a Stop-Mode
Recovery source.
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Stop-Mode Recovery Register 2 (SMR2). This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this register then SMR Register. Bits D2, D3, and D4 must be 0.
Table 14. Stop-Mode Recovery Source
SMR:10
D1 D0
0
0
1
0
1
0
Operation
Description of Action
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it reach-
es its terminal count. The WDT is initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit is driven
by an onboard RC oscillator or external oscillator from the
XTAL1 pin. The POR clock source is selected with bit 4 of
the WDT register (Figure 29).
WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. The WDTMR must be written to within 64 internal system clocks. After that, the WDTMR is WRITE-pro-
tected.
Note: WDT time-out while in STOP mode does not reset SMR,
PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers,
but the POR delay counter is still enabled even though
the SMR stop delay is disabled.
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC External Clock
00
3.5 ms
128 TpC
7 ms
256 TpC
01*
10
14 ms
512 TpC
11
56 ms
2048 TpC
WDT During HALT
0 OFF
1 ON*
WDT During STOP
0 OFF
1 ON*
XTAL1/INT RC Select for WDT
0 On-Board RC*
1 XTAL
Reserved (must be 0)
* Default setting after RESET
Figure 29. Watch-Dog Timer Mode Register (WRITE ONLY)
Table 15. WDT Time Select
WDT Time Select. (D0,D1). Selects the WDT time period
and is configured as indicated in Table 15.
D1
D0
Timeout of
Internal RC OSC
Timeout of
System Clock
0
0
1
1
0
1
0
1
3.5 ms min
7 ms min
14 ms min
56 ms min
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
Notes:
SCLK = system bus clock cycle.
The default on RESET is 7 ms.
Values provided are for VCC = 5.0V.
DS007601-Z8X0499
PRELIMINARY
41
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
FUNCTIONAL DESCRIPTION (Continued)
WDTMR During HALT (D2). This bit determines whether
or not the WDT is active during HALT mode. A 1 indicates
active during HALT. The default is 1.
WDTMR During STOP (D3). This bit determines whether
or not the WDT is active during STOP mode. Because XTAL
clock is stopped during STOP mode, the on-board RC must
be selected as the clock source to the POR counter. A 1 indicates active during STOP. The default is 1.
Note: If permanent WDT is selected, the WDT runs in all
modes and can not be stopped or disabled if the on board
RC oscillator is selected as the clock source for WDT.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and WDT
counter chain. If the bit is a 1, the internal RC oscillator is
bypassed and the POR and WDT clock source is driven from
the external pin, XTAL1. The default configuration of this
bit is 0 which selects the internal RC oscillator.
42
WDTMR Register Accessibility. The WDTMR register is
accessible only during the first 60 internal system clock cycles from the execution of the first instruction after PowerOn Reset, Watch-Dog Reset, or Stop-Mode Recovery. After this point, the register cannot be modified by any means,
intentional or otherwise. The WDTMR cannot be read and
is located in bank F of the Expanded Register Group at address location 0FH (Figure 30).
Note: The WDT can be permanently enabled (automatically
enabled after RESET) through a mask programming option. The option is selected by the customer at the time
of ROM code submission. In this mode, WDT is always
activated when the device comes out of RESET. Execution of the WDT instruction serves to refresh the WDT
time-out period. WDT operation in the HALT and STOP
Modes is controlled by WDTMR programming. If this
mask option is not selected at the time of ROM code submission, the WDT must be activated by the user through
the WDT instruction and is always disabled by any reset
to the device.
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Reset
4 Clock
Filter
Clear
CLK
18 Clock RESET
Generator
RESET
Internal
RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CLK Source
Select
(WDTMR)
XTAL
Internal
RC OSC.
VDD
+
VLV
–
5ms POR
CK
CLR
M
U
X
5ms 15ms 25ms 100ms
WDT/POR Counter Chain
2V Operating
Voltage Det.
WDT
From Stop
Mode
Recovery
Source
Stop Delay
Select (SMR)
Figure 30. Resets and WDT
Low Voltage Protection. An onboard Voltage Comparator checks that VCC is at the required level to ensure correct
operation of the device. RESET is globally driven if VCC is
below the specified voltage (Low Voltage Protection). The
minimum operating voltage is varying with the temperature
and operating frequency, while the Low Voltage Protection
(VLV) varies with temperature only.
The Low Voltage Protection trip voltage (VLV) is less than
3V and more than 1.4V under the following conditions.
Table 16. Maximum (VLV) Conditions:
Case 1:
TA = –40ºC, +105ºC, Internal Clock
Case 2:
Frequency equal or less than 4 MHz
TA = –40ºC, +85ºC, Internal Clock
Note: The internal clock frequency relationship to the XTAL
clock is dependent on SMR BIT 0 1 setting.
The device functions normally at or above 3.0V under all
conditions. Below 3.0V, the device functions normally until
the Low Voltage Protection trip point (VLV) is reached, for
the temperatures and operating frequencies in Case 1 and
Case 2, above. The device is guaranteed to function normally
at supply voltages above the Low Voltage Protection trip
point. The actual Low Voltage Protection trip point is a function of temperature and process parameters (Figure 36).
Frequency equal or less than 6 MHz
DS007601-Z8X0499
PRELIMINARY
43
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (ASCI)
Key features of the ASCI include:
Programmable data format
ceive Data Register Full Flag also goes active during this
time. If there is no space in the FIFO at the time that the
RSR attempts to transfer the received data into it, an overrun
error occurs.
7 or 8 data bits with optional ninth bit for multiprocessor
communication
Receive Data FIFO. When a complete incoming data byte
is assembled in the RSR, it is automatically transferred to
•
•
•
Full-duplex operation
•
P30 and P37 can be used as general-purpose I/O as long
as the ASCI channels are disabled
•
•
•
•
•
•
One or two STOP bits
Odd, even or no parity
Programmable interrupt conditions
Four level data/status FIFOs for the receiver
Receive parity, framing and overrun error detection
Break detection and generation
Transmit Data Register. Data written to the ASCI Transmit Data Register (TDR) is transferred to the Transmit Shift
Register(TSR) as soon as the TSR is empty. Data can be
written while the TSR is shifting out the previous byte of
data, providing double buffering for the transmit data. The
TDR is READ- and WRITE-accessible. Reading from the
TDR does not affect the ASCI data transmit operation currently in progress.
Transmit Shift Register. When the ASCI Transmit Shift
Register (TSR) receives data from the ASCI Transmit Data
Register, the data is shifted out to the TX (P37) pin. When
transmission is completed, the next byte (if available) is automatically loaded from the TDR into the TSR and the next
transmission starts. If no data is available for transmission,
the TSR idles at a continuous High level. This register is
not program-accessible.
Receive Shift Register. When the RE bit is set in the
CNTLA register, the RX (P30) pin is monitored for a Low.
One-half bit-time after a Low is sensed at RX, the ASCI
samples RX again. If RX goes back to High, the ASCI
ignores the previous Low and resumes looking for a new
Low, but if RX is still Low, it considers RX a START bit
and proceeds to clock in the data based upon the selected
baud rate. The number of data bits, parity, multiprocessor
and STOP bits are selected by the MOD2, MOD1, MOD0
and multiprocessor mode ( MP) bits in the CNTLA and
CNTLB registers.
After the data is received, the appropriate MP, parity and
one STOP bit are checked. Data and any errors are clocked
into the receive data and status FIFO during the STOP bit
if there is an empty position available. Interrupts and Re44
the 4-byte FIFO, which serves to reduce the incidence of
overrun errors. The top (oldest) character in the FIFO (if
any) can be read via the Receive Data Register (RDR).
The next incoming data byte can be shifted into the RSR
while the FIFO is full, thus providing an additional level of
buffering. However, an overrun occurs if the receive FIFO
is still full when the receiver completes assembly of that
character and is ready to transfer it to the FIFO. If this situation occurs, the overrun error bit associated with the previous byte in the FIFO is set. The latest data byte is not transferred from the shift register to the FIFO in this case, and
is lost. When an overrun occurs, the receiver does not place
any further data in the FIFO until the most recent good byte
received arrives at the top of the FIFO and sets the Overrun
latch, and software then clears the Overrun latch by a
WRITE of 0 to the EFR bit. Assembly of bytes continues in
the shift register, but this data is ignored until the byte with
the overrun error reaches the top of the FIFO and the status
is cleared.
When a break occurs (defined as a framing error with the
data equal to all zeros), the all-zero byte with its associated
error bits are transferred to the FIFO if it is not full and the
Break Detect bit in the ASEXT register is set. If the FIFO
is full, an overrun is generated, but the break, framing error
and data are not transferred to the FIFO. Any time a break
is detected, the receiver does not receive any more data until
the RX pin returns to a high state.
If the channel is set in multiprocessor mode and the MPE
bit of the CNTLA register is set to 1,then break, errors and
data are ignored unless the MP bit in the received character
is a 1. The two conditions listed above could cause the missing of a break condition if the FIFO is full and the break
occurs or if the MP bit in the transmission is not a one with
the conditions specified above.
ASCI Status FIFO/Registers. This FIFO contains Parity
Error, Framing Error, RX Overrun, and Break status bits as-
sociated with each character in the receive data FIFO. The
status of the oldest character (if any) can be read from the
ASCI status register, which also provides several other,
non-FIFOed status conditions.
The outputs of the error FIFO go to the set inputs of software-accessible error latches in the status register. Writing
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a 0 to the EFR bit in CNTLA is the only way to clear these
latches. In other words, when an error bit reaches the top
of the FIFO, it sets an error latch. If the FIFO contains more
data and the software reads the next byte out of the FIFO,
the error latch remains set until the software writes a 0 to
the EFR bit. The error bits are cumulative, so if additional
errors are in the FIFO they set any unset error latches as they
reach the top.
Baud Rate Generator. The baud rate generator features
two modes. The first provides a dual set of fixed clock divide ratios as defined in CNTLB. In the second mode, the
BRG is configured as a sixteen-bit down counter that divides
the processor clock by the value in a software accessible,
sixteen-bit, time-constant register. As a result, virtually any
frequency can be created by appropriately selecting the
main processor clock frequency. The BRG can also be disabled in favor of the SCLK.
The Receiver and Transmitter subsequently divide the output of the Baud rate Generator (or the signal from the CLK
pin) by 1, 16 or 64 under the control of the DR bit in the
CNTLB register and the X1 bit in the ASCI Extension Control Register (ASEXT).
RESET. During RESET, the ASCI is forced to the following
conditions:
•
•
•
•
FIFO Empty
All Error Bits Cleared (including those in the FIFO)
Receive Enable Cleared (CNTLA BIT 6 = 0)
Transmit Enable Cleared (CNTLA BIT 5 = 0)
Internal Address/Data Bus
ASCI Transmit Data Register
TDR (Bank:Ah,Addr :01h)
**
(P37) TX
IRQ3
Interrupt Request
ASCI Transmit Shift Register
TSR
ASCI Receive Data FIFO
RDR (Bank:Ah,Addr:02h)
**
(P30) RX
ASCI Receive Shift Register
RSR
ASCI
ASCI Control Register A
CNTLA (Bank:Ah,Addr:03h)
Accessible
Control
ASCI Control Register B
CNTLB (Bank:Ah,Addr:04h)
ASCI Status FIFO/Register
STAT (Bank:Ah,Addr:08h)
ASCI Extension Control Reg.
ASEXT (Bank:Ah,Addr:05h)
ASCI Time Constant High
ASTCH (Bank:Ah,Addr:07h)
ASCI Time Constant Low
ASTCL (Bank:Ah,Add:06h)r
SCLK
Baud Rate Generator
Note: **Not Program
Figure 31. ASCI Interface Diagram
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INTERRUPTS
The ASCI channel generates one interrupt (IRQ3) from two
sources of interrupts: a receiver and a transmitter. In addition, there are several conditions that may cause these in-
terrupts to trigger. Figure 32 illustrates the different conditions for each interrupt source enabled under program
control.
FIFO full
Overrun error
Framing Error
Receiver
Interrupt
Sources
Parity Error
ASCI
Interrupt
(IRQ3)
Start Bit
Buffer Empty
Transmitter
Interrupt
Sources
Figure 32. ASCI Interrupt Conditions and Sources
46
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EXPANDED REGISTER GROUP (A)
%(A)0F
RESERVED
%(A)0E
RESERVED
%(A)0D
RESERVED
%(A)0C
RESERVED
%(A)0B
RESERVED
%(A)0A
RESERVED
%(A)09
GEN PURPOSE
B7
B6
B5
B4
B3
B2
B1
B0
u
u
u
u
u
u
u
u
* %(A)08
STAT
0
0
0
0
0
0
1
0
* %(A)07
ASTCH
1
1
1
1
1
1
1
1
* %(A)06
ASTCL
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
* %(A)05
ASEXT
%(A)04
CNTLB
0
0
0
0
0
1
1
1
* %(A)03
CNTLA
0
0
0
1
0
0
0
0
* %(A)02
RDR
u
u
u
u
u
u
u
u
* %(A)01
TDR
u
u
u
u
u
u
u
u
%(A)00
RESERVED
*
* Not reset with a STOP-Mode Recovery.
Figure 33. Expanded Register Group (A) Registers
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CMOS Z8® MCUs with ASCI UART
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ASCI TRANSMIT DATA REGISTER (TDR)
(%(A)01H: READ/WRITE)
Table 17. TDR Register Bit Functions
Bit
7
6
5
4
3
2
1
0
U
U
U
R
Transmit Data
W
Reset
U
U
U
U
U
written to the TDR while the TSR is shifting out the previous
byte. Data can be written into and read out of the TDR. When
the TDR is read, the data transmit operation is not affected.
Data written to the ASCI Transmit Data Register (TDR) is
transferred to the Transmit Shift Register (TSR) as soon as
the TSR is empty. The TSR is not not software-accessible.
The ASCI transmitter is double-buffered so data can be
ASCI RECEIVE DATA REGISTER (RDR)
(%(A)02H: READ/WRITE)
Table 18. RDR Register Bit Functions
Bit
7
6
5
4
3
2
1
0
U
U
U
R
Receive Data
W
Reset
U
U
U
U
When a complete incoming data byte is assembled in the
Receive Shift Register (RSR), it is automatically transferred
to the highest available location in the Receive Data FIFO.
The Receive Data Register (RDR) is the highest location in
the Receive Data FIFO. The RDRF bit in the STAT register
U
is set when one or more bytes is available from the FIFO.
The FIFO status for the character in the RDR is available
in the STAT register via bits 6, 5 and 4. STAT should be
read before reading the RDR. The data in both FIFO locations is popped when the character is read from the RDR.
ASCI CONTROL REGISTER A (CNTLA)
(%(A)03H: READ/WRITE)
Table 19. CNTLA Register Bit Functions
Bit
7
6
5
4
Multiprocessor
Enable
(MPE)
Receiver
Enable
(RE)
Transmitter
Enable
(TE)
Reserved
1
0
0
0
0
1
Mode Select
Error Flag
Receive
(EFR)
W
48
2
Multiprocessor MOD2 MOD1 MOD0
Bit Received
(MPBR)
R
Reset
3
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0
0
0
0
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Bit 7 is the Multiprocessor Enable
Bit 4 is Reserved
The ASCI features a multiprocessor communication mode
that utilizes an extra data bit for selective communication
when a number of processors share a common serial bus.
Multiprocessor data format is selected when the MP bit in
the corresponding register is set to 1. If multiprocessor
mode is not selected (MP bit in CNTLB = 0), multiprocessor
enable (MPE) has no effect. If multiprocessor mode is selected (MP bit in CNTLB = 1), MPE enables or disables the
wake-up feature as follows. If MPE is set to 1, only received
bytes in which the multiprocessor bit (MPB) = 1 are treated
as valid data characters and loaded into the receiver FIFO
with corresponding error flags in the status FIFO. Bytes
with MPB = 0 are ignored by the ASCI. If MPE is reset to
0, all bytes are received by the ASCI, regardless of the state
of the MPB data bit.
Bit 3 is the Multiprocessor Bit Receive
(Read only)
When multiprocessor mode is enabled (MP in CNTLB = 1),
this bit, when read, contains the value of the MPB bit for
the data byte currently available at the Receive Data Register (the top of the receiver FIFO).
Bit 3 is the Error Flag Reset (WRITE ONLY)
When written to 0, the error flags (OVRN, FE; PE in STAT
and BRK in ASEXT) are cleared to 0. This command selfresets, and as a result, writing EFR to a 1 is not required.
Bits 2–0 are the ASCI Data Format Mode 2,1,0
These bits program the ASCI data format.
Bit 6 is the Receiver Enable
Table 20. Format Mode Control Bits
When Receiver Enable(RE) is set to 1,the ASCI receiver is
enabled. When RE is reset to 0, the receiver is disabled and
any receive operation in progress is aborted. However, the
previous contents of the receiver data and status FIFO are
not affected.
Bit
Name Function
Bit = 0
Bit = 1
2
1
MOD2 Number of Data Bits
MOD1 Parity Enabled
Bit 5 is the Transmitter Enable
0
MOD0 Number of Stop Bits
7
No
Parity
1
8
With
Parity
2
When Transmitter Enable(TE) is set to 1,the ASCI transmitter is enabled. When TE is reset to 0, the transmitter is
disabled and any transmit operation in progress is aborted.
However, the previous contents of the transmitter data register and the TDRE flag are not affected.
If MOD1 = 1, parity is checked on received data and a parity
bit is appended to the data bits in the transmitted data. Parity
Even/Odd (PEO) in CNTLB selects even or odd parity.
The ASCI serial data format is illustrated in Figure 34.
7 or 8 bits Data Field
1 or 2
Stop Bit(s)
Start
Bit
it
Parity
Bit
Figure 34. ASCI Serial Data Format
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ASCI CONTROL REGISTER B (CNTLB)
(%(A)04H: READ/WRITE)
Table 21. CNTLB Register Bit Functions
Bit
7
6
R
Multiprocessor
Bit
Transmitter
(MPBT)
Multiprocessor
Mode
(MP)
0
0
W
Reset
5
Prescale
(PR)
0
BIT 7 is the Multiprocessor Bit Transmit
When multiprocessor format is selected (MP BIT = 1), Multiprocessor Bit Transmit (MPBT) is used to specify the MPB
data bit for transmission. If MPBT = 1, then a 1 is transmitted
in the MPB bit position. If MPBT = 0, a 0 is transmitted.
BIT 6 is the Multiprocessor Mode
4
3
2
SS2
Parity
Even/Odd
(PEO)
Divide Ratio
(DR)
0
0
1
SS1
0
SS0
Clock Source
and Speed
1
1
1
position whose value is specified in MPBT immediately after the specified number of data bits and preceding the specified number of STOP bits.
Note: The multiprocessor format does not provide parity. The
serial data format while in MP mode is illustrated in Figure 35.
When Multiprocessor Mode (MP) is set to 1, the serial data
format is configured for multiprocessor mode, adding a bit
7 or 8 bits Data Field
Start Bit
MPB
1 or 2
Stop Bit(s)
Figure 35. MP Mode Serial Data Format
If MP = 0, the data format is based on MOD2–0 in CNTLA
and may include parity.
Bit 5 is the BRG Prescaler
The Prescale bit specifies the baud rate generator prescale
factor when using the SS2–0 bits to define the ASCI baud
rate (BRG MODE = 0). Writing a 0 to this bit sets the BRG
Prescaler to divide by 10. Setting this bit to a 1 sets the BRG
Prescaler to divide by 30. See the Baud Rate Generation
Summary for more information on setting the ASCI baud
rate.
50
Bit 4 is the Parity Even/Odd
Parity Even/Odd (PEO) controls the parity bit transmitted
on the serial output and the parity check on the serial input.
If PEO is cleared to 0, even parity is transmitted and checked
If PEO is set to 1, odd parity is transmitted and checked.
Bit 3 is the Divide Ratio
The Divide Ratio bit specifies the divider used to obtain the
baud rate from the data sampling clock when using the
SS2–0 bits to define the ASCI baud rate (BRG MODE = 0).
If DR is 0, then DIVIDE-BY-16 is used. If DR is set to a 1,
then DIVIDE-BY-64 is used. See the Baud Rate Generation
Summary for more information on setting the ASCI baud
rate.
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DR
Sampling Clock
0
1
Divide by 16
Divide by 64
Table 22. Clock Source and Speed Bits
Bit 2,1 are the Clock Source and Speed Select
When the BRG mode bit in the ASEXT register is set to 0,
these 3 bits, along with DR and PR in this register define
the ASCI baud rate. Bits 2, 1 and 0 specify a power-of-two
divider of the SCLK as defined in Table 22. These bits
should never be set to all 1s or erratic results may occur.
See the Baud Rate Generation Summary for more information on setting the ASCI baud rate.
DS007601-Z8X0499
SS2
SS1
SS0
Divider (DIV)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷1
÷2
÷4
÷8
÷16
÷32
÷64
Reserved
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CMOS Z8® MCUs with ASCI UART
ZiLOG
ASCI EXTENSION CONTROL REGISTER (ASEXT)
(%(A)05H: READ/WRITE)
Table 23. ASEXT Register Bit Functions
Bit
7
R
RX State
(RX)
6
Reserved
W
Reset
P30
5
4
3
2
RX
Reserved BRG Mode Interrupt on
Reserved
(must be 0) (BRGM)
Start Bit
(RIS)
0
0
0
BIT 7 is the RX State (READ ONLY)
0
0
1
Break
Detect
(BD)
0
Send Break
(SB)
0
0
Bit 5 is Reserved
on RX. Such a receive interrupt is always followed by the
setting of RDRF in the middle of the STOP bit. This interrupt
request must be cleared by writing this bit back to a 0. Writing a 1 to this bit has no effect. One function of this feature
is to wake the part from Sleep mode when a character arrives, so that the ASCI receives clocking with which to process the character. Another function is to ensure that the associated interrupt service routine is activated in time to
sense the setting of RDRF in the status register, and to start
a timer for baud rate measurement at that time.
When read, this bit reflects the default value 0. When
WRITE, this bit is ignored.
Bit 1 is the Break Detect (READ ONLY)
Provides the real time state of RX, the channel’s receive data
input pin—P30.
BIT 6 is Reserved
When read, this bit reflects the default value 0. When
WRITE, this bit is ignored.
Bit 4 is the X1 Bit Clock
Reserved—must be set to 0 or erratic results may occur.
Bit 3 is the BRG Mode
When this bit is set to a 1, the ASCI’s baud rate is set by
the 16-bit programmable divider programmed in ASCI
Time Constant High (ASTH) and ASCI Time Constant Low
(ASTL). If this bit is set to a 0, the baud rate is defined by
the PR bit, the DR bit, and the SS2–0 bits in the CNTLB register. In either case, the source for the baud rate generator
is the SCLK. See the Baud Rate Generation Summary for
more information on setting the ASCI baud rate.
Bit 2 is the Rx Interrupt on Start
If software sets this bit to 1,a receive interrupt is requested
(in a combinatorial fashion) when a START bit is detected
52
This status bit is set to a 1 when a Break is detected, defined
as a framing error with the data bits all equal to 0. The allzero byte with its associated error bits are transferred to the
FIFO if it is not full. If the FIFO is full, an overrun is generated, but the break, framing error and data are not transferred to the FIFO. Any time a break is detected, the receiver
do not receive any more data until the RX pin returns to a
High state. When set, this bit remains set until it is cleared
by writing a 0 to the EFR bit in the CNTLA register.
Bit 0 is the Send Break
Setting this bit to a 1 forces the channel’s transmitter data
output pin, TX, to a Low for as long as it remains set. Before
starting the break, any character(s) in the TSR and in the
TDR are completely transmitted. If a character is loaded into
the TDR while a break is being generated, that character is
held until the break is terminated and transmitted.
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ASCI TIME CONSTANT REGISTER (ASTL)
(%(A)06H: READ/WRITE)
Table 24. ASTL Register Bit Functions
Bit
7
6
5
4
3
2
1
0
1
1
1
2
1
0
1
1
1
R
ASCI Time Constant Low
W
Reset
1
1
1
1
1
ASCI TIME CONSTANT REGISTER (ASTH)
(%(A)07H: READ/WRITE)
Table 25. ASTH Register Bit Functions
Bit
7
6
5
4
3
R
ASCI Time Constant High
W
Reset
1
1
1
1
1
The ASTL and ASTH registers are only used when the BRG
mode bit in the ASEXT register is set to a 1. These two 8bit registers form a 16-bit counter with a flip-flop logic circuit (DIVIDE-BY-2) on the output so that the final BRG output is symmetrical. The values written to these registers determine the time constant from which the baud rate is
generated.
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ASCI STATUS REGISTER (STAT)
(%(A)08H: READ/WRITE)
Table 26. ASCI Status Register (STAT)
Bit
R
7
Receive
Data
Register
Full
(RDRF)
6
5
4
3
Overrun
Error
(OE)
Parity Error
(PE)
Framing
Error
(FE)
2
Receiver
Interrupt
Enable
(RIE)
Reserved
0
0
1
Transmit
Data
Register
Empty
TDRE)
0
Transmitter
Interrupt
Enable
(TIE)
W
Reset
0
0
0
0
0
0
BIT 7 is the Receive Data Register Full
Bit 5 is the Parity Error
RDRF is set to 1 when the receiver transfers a character from
the RSR into an empty Rx FIFO.
A parity error is detected when parity generation and checking is enabled by the MOD1 bit in the CNTLA register and
a character has been assembled in which the parity does not
match that specified by the PEO bit in CNTLB.
Note: If a framing or parity error occurs, RDRF is still set and
the receive data (which generated the error) is still loaded into the FIFO.
When there is more than one character in the FIFO, and software reads a character, RDRF either remains set or is cleared
and immediately set again. RDRF is cleared to 0 when the
FIFO becomes empty after reading the RDR and during
Power-On Reset.
Note: PE is FIFOed and the error bit is not actually set until the
associated data becomes available for reading in the
RDR.
When set, the bit remains set until it is cleared by writing
a 0 to the EFT bit in the CNTLA register. The bit is cleared
at Power-On Reset.
Bit 6 is the Overrun Error
Bit 4 is the Framing Error
An overrun occurs if the receive FIFO is still full when the
receiver completes assembly of a character and is ready to
transfer it to the FIFO. If this situation occurs, the overrun
error bit associated with the previous byte in the FIFO is
set. In this case, the latest data byte is not transferred from
the shift register to the FIFO and is lost.
A framing error is detected when the STOP bit of a character
is sampled as a 0 (space). Like PE, FE is FIFOed and the
error bit is not actually set until the associated data becomes
available for reading in the RDR. When set, the bit remains
set until it is cleared by writing a 0 to the EFR bit in the
CNTLA register. The bit is cleared at Power-On Reset.
When an overrun occurs, the receiver does not place any
further data in the FIFO until the most recent good byte
received (the byte with the associated overrun error bit set)
moves to the top of the FIFO and sets the Overrun latch,
and software then clears the Overrun latch. Assembly of
bytes continues in the shift register, but this data is ignored
until the byte with the overrun error reaches the top of the
FIFO and the status is cleared. When set, the bit remains
set until it is cleared by writing a 0 to the EFR bit in the
CNTLA register. The bit is also cleared during Power-On
Reset.
Bit 3 is the Receiver Interrupt Enable
54
RIE should be set to a 1 to enable ASCI receive interrupt
requests. An interrupt (IRQ3) is generated when RDRF (bit
7 of the STAT register) is a 1. A receive interrupt is also
generated if this bit is set to a 1, bit 2 of the ASEXT register
(RX interrupt on the START bit) is set to a 1, and a START
bit is detected by the receiver.
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Bit 2 is Reserved
Baud Rate =
When read, this bit reflects the default value 0. When
WRITE, this bit is ignored.
SCLK
(10 + 20 x PS) x DIV x Divide Ratio
Bit 1 is the Transmit Data Register Empty
Where:
TDRE = 1 indicates that the Transmit Data Register (TDR)
1. SCLK is the system clock.
is empty and that the next data byte to be transmitted can
be written into the TDR. TDRE is cleared to 0 after the byte
is written to TDR, until the ASCI transfers the byte from the
TDR to the Transmit Shift Register (TSR), and then TDRE
is again set to 1. TDRE is set to 1 at Power-On Reset.
Bit 0 is the Transmit Interrupt Enable
TIE should be set to a 1 to enable ASCI transmit interrupt
requests. An interrupt (IRQ3) is generated when TDRE (bit
1 of the STAT register) is a 1. TIE is cleared to 0 at Power-
2. PS = 1 or 0 and is bit 5 of CNTLB.
3. DIV = 1, 2, 4, 8, 16, 32 or 64 as reflected by SS2–0 in
CNTLB.
4. DIVIDE RATIO = 16 or 64, as defined by DR in
CNTLB.
If BRG mode = 1:
Baud Rate =
On Reset.
An anomaly exists that requires setting of the RIE bit to allow the generation of transmit interrupts. If RIE is not set,
transmit interrupts are not generated, even if TIE is set. See
Precautions.
SCLK
(2 x (TC + 2) x Divide Ratio
or
TC =
SCLK
2 x Baud Rate x Divide Ratio
–2
Baud Rate Generation Summary
The application can select between one of two baud rate
generators for the ASCI. If the BRG Mode bit in the ASEXT
register is set to a 0, the SS2,1,0 bits, the DR, bit and the
PR bit in CNTLB are used to select the baud rate. If the BRG
Mode bit is set to a 1, the ASTL and ASTH registers are
used to select the baud rate.
The following formulas are used to calculate the baud rate
from the two baud rate generators:
Where:
1. SCLK is the system clock.
2. TC is the 16-bit value programmed into ASTL and
ASTH.
3. DIVIDE RATIO = 16 or 64, as defined by DR in
CNTLB.
4. Baud Rate is the desired baud rate.
If BRG mode = 0:
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ZiLOG
ASCI STATUS REGISTER (STAT) (Continued)
Table 27. Baud Rate List (BRG Mode = 0)
Prescaler
PS
0
1
56
Divide
Ratio
Sampling
Rate
DR
Rate
0
16
1
64
SCLK
÷ 10
0
16
1
64
SCLK
÷ 30
Baud Rate
Example Baud Rate (bps)
SS2
SS1
SS0
Divide
Ratio
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷1
÷2
÷4
÷8
÷16
÷32
÷64
PRELIMINARY
General
Divide Ratio
SCLK ÷ 160
SCLK ÷ 320
SCLK ÷ 640
SCLK ÷ 1280
SCLK ÷ 2560
SCLK ÷ 5120
SCLK ÷ 10240
SCLK ÷ 640
SCLK ÷ 1280
SCLK ÷ 2560
SCLK ÷ 5120
SCLK ÷ 10240
SCLK ÷ 20480
SCLK ÷ 40960
SCLK ÷ 480
SCLK ÷ 960
SCLK ÷ 1920
SCLK ÷ 3840
SCLK ÷ 7680
SCLK ÷ 15360
SCLK ÷ 30720
SCLK ÷ 1920
SCLK ÷ 3840
SCLK ÷ 7680
SCLK ÷ 15360
SCLK ÷ 30720
SCLK ÷ 61440
SCLK ÷ 122880
SCLK = SCLK = SCLK =
6.144
4.608
3.072
MHz
MHz
MHz
38400
19200
9600
4800
2400
1200
600
9600
4800
2400
1200
600
300
150
19200
9600
4800
2400
1200
600
300
4800
2400
1200
600
300
150
75
4800
2400
1200
600
300
150
75
2400
1200
600
300
150
75
37.5
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
LOW VOLTAGE PROTECTION
VCC
(Volts)
3.80
3.60
3.40
A RUN/HALT Mode
VLV (Typical)
B STOP Mode
3.20
B
3.00
A
2.80
2.60
2.40
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (ºC)
Figure 36. Typical Low Voltage Protection vs. Temperature
DS007601-Z8X0499
PRELIMINARY
57
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
MASK OPTIONS
Below is an example of the ROM mask bit option selection
for this product.
Options
ROM Protect
RAM Protect
System Clock Source
Oscillator Operational Mode
Option Selections
WDT Mode
Disable ROM Protect
Disable RAM Protect
RC Oscillator Enable
Normal High-Frequency Operation
Enabled
WDT Enabled by Software Only
Auto Latch Mode
Port 0 Pull-Ups
Port 1 Pull-Ups
Port 2 Pull-Ups
Disable Auto Latches
Disable Pull-Ups
Disable Pull-Ups
Disable Pull-Ups
ROM Protect. Selecting the DISABLE ROM PROTECT option READs the software program that is in the program
memory using ZiLOG’s internal factory test mode. However, none of the standard methods for reading or verifying
the code in the microcontroller uses an EPROM programmer. With this option disabled, ZiLOG is able to fully test
the ROM memory and provides its standard warranty for
the part. Selecting the ENABLE ROM PROTECT option negates the possibility of reading the code out of the part using
a tester, programmer, or any other standard method. ZiLOG
will be unable to test the ROM memory at any time prior
to customer delivery.
The ROM PROTECT option bit only affects the ability to
read the code and does not affect the operation of the part
in an application. If the ROM PROTECT option is disabled,
ZiLOG tests the part for ROM fallout and parts which fail
are not shipped to the customer. When the ROM PROTECT
option is enabled, ZiLOG cannot perform these tests on the
ROM. When ROM PROTECT is enabled, except for the improper transfer of the code by ZiLOG, all ROM memory
software errors shall be the responsibility of the Buyer and
ZiLOG shall have no obligation to repair or replace product
containing software errors. Selecting the ENABLE ROM
PROTECT option waives all warranties of ZiLOG, expressed or implied, on microcontrollers containing ROM
failures including, but not limited to, the implied warranty
of merchantability and fitness for a particular purpose.
RAM Protect. Selecting the DISABLE RAM PROTECT option does not affect the RAM memory. RAM memory operates as defined in this Product Specification for all address
locations. Selecting the ENABLE RAM PROTECT option,
58
Enable ROM Protect
Enable RAM Protect
Crystal/Other Clock Source
32-kHz Crystal Operation Enabled
(Limits High-Frequency Operation)
WDT Enabled Automatically After
RESET
Enable Auto Latches
Enable Pull-Ups
Enable Pull-Ups
Enable Pull-Ups
allows protection (under software control) of a portion of
the RAM’s address space from being read or written.
System Clock Source. Selecting the RC OSCILLATOR
ENABLE option, configures the oscillator circuit on the mi-
crocontroller to work with an external RC circuit. Selecting
the CRYSTAL/OTHER CLOCK SOURCE option configures
the oscillator circuit to work with an external crystal, ceramic resonator, or LC oscillator.
Oscillator Operational Mode. Selecting the NORMAL
HIGH FREQUENCY OPERATION ENABLED option en-
ables the part to operate using a standard crystal or resonator, but it does not operate using a 32-kHz crystal. Selecting
the 32-KHZ OPERATION ENABLED option enables the microcontroller to work with a 32-kHz crystal and an external
feedback resistor—these must be supplied between the
XTAL1 and XTAL2 pins. (If RC OSCILLATOR ENABLED
is selected in the SYSTEM CLOCK SOURCE option, this
option defaults to the NORMAL HIGH FREQUENCY OPERATION ENABLED bit.)
WDT Mode. Selecting the WDT ENABLED BY SOFTWARE ONLY option operates the Watch Dog Timer (WDT)
when turned on under software control. Selecting the WDT
ENABLED AUTOMATICALLY AFTER RESET option starts
the WDT automatically at RESET.There is no way to dis-
able or stop this mode, making it necessary in the code to
periodically clear the WDT to prevent it from resetting the
microcontroller. If the WDT ENABLED AUTOMATICALLY AFTER RESET option and the WDT DRIVEN BY SYSTEM CLOCK option (if offered) are selected, the WDT nev-
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
er operates in STOP mode, and cannot be enabled, by any
means, to operate in STOP mode.
Port 0 pins. This option bit does not affect any of the other
port pins on the part.
Auto Latch Mode. Selecting the DISABLE AUTOLATCHES option disables the autolatches on the Port pins. These
Port 1 Pull-Ups. Selecting DISABLE PULL-UPS disables
the input pull-up circuitry on all Port 1 pins. Selecting ENABLE PULL-UPS enables the input pull-up circuitry on all
Port 1 pins. This option bit does not affect any of the other
port pins on the part.
pins will float rather than be pulled to a valid CMOS level
when they are inputs and not connected to an external signal. Selecting the ENABLE AUTOLATCHES option enables
the autolatches on the Port pins and pulls the pins to a valid
CMOS level when they are not connected to an external signal.
Port 0 Pull-Ups. Selecting DISABLE PULL-UPS disables
the input pull-up circuitry on all Port 0 pins. Selecting ENABLE PULL-UPS enables the input pull-up circuitry on all
DS007601-Z8X0499
Port 2 Pull-Ups. Selecting DISABLE PULL-UPS disables
the input pull-up circuitry on all Port 2 pins. Selecting ENABLE PULL-UPS enables the input pull-up circuitry on all
Port 2 pins. This option bit does not affect any of the other
port pins on the part.
PRELIMINARY
59
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
EXPANDED REGISTER FILE CONTROL REGISTERS
WDTMR (F) 0F
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
WDT TAP
00
01 *
10
11
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
WDT During HALT
0 OFF
1 ON *
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
INT RC OSC System Clock
3.5 ms
128 SCLK
10 ms
256 SCLK
14 ms
512 SCLK
56 ms
2048 SCLK
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
* Default setting after RESET
Figure 39. Watch-Dog Timer Mode Register
(WRITE ONLY)
Stop Flag (Read only)
0 POR*
1 Stop Recovery
Note: Not used in conjunction with SMR2 Source
* Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
Figure 37. Stop-Mode Recovery Register
(WRITE ONLY, except Bit D7, which is READ ONLY)
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
Figure 38. Stop-Mode Recovery Register2
60
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Z8 CONTROL REGISTERS
R242 T1
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
T1 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T1 Current Value
(When Read)
0 Port 1 Open Drain
1 Port 1 Push-pull Active*†
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
0 Port 0 Low EMI
1 Port 0 Standard*†
Figure 42. Counter/Timer 1 Register
(F2H: READ/WRITE)
0 Port 1 Low EMI
1 Port 1 Standard*
0 Port 2 Low EMI
1 Port 2 Standard*
0 Port 3 Low EMI
1 Port 3 Standard*
*Default Setting After Reset
†
Must be set to one for devices
in 28-pin packages
R243 PRE1
D7 D6 D5 D4 D3 D2 D1 D0
Low EMI Oscillator
0 Low EMI
1 Standard*
Count Mode
0 T1 Single Pass
1 T1 Modulo N
Figure 40. Port Configuration Register (PCON)
(WRITE ONLY)
Clock Source
1 T1Internal
0 T1External Timing Input
(TIN) Mode
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R241 TMR
Figure 43. Prescaler 1 Register
(F3H: WRITE ONLY)
D7 D6 D5 D4 D3 D2 D1 D0
0 No Function
1 Load T0
0 Disable T0 Count
1 Enable T0 Count
0 No Function
1 Load T1
R244 T0
D7 D6 D5 D4 D3 D2 D1 D0
0 Disable T1 Count
1 Enable T1 Count
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
TOUT Modes
00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out
T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When Read)
Figure 44. Counter/Timer 0 Register
(F4H: READ/WRITE)
Figure 41. Timer Mode Register
(F1H: READ/WRITE)
DS007601-Z8X0499
PRELIMINARY
61
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Z8 CONTROL REGISTERS (Continued)
R245 PRE0
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
P00–P03 Mode
00 Output
01 Input
1X A11–A8
Count Mode
0 T0 Single Pass
1 T0 Modulo N
Stack Selection
0 External
1 Internal†
Reserved (Must be 0)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
P10 - P17 Mode
00 Byte Output†
01 Byte Input
10 AD7 - AD0
11 High-Impedance AD7–AD0,
AS, DS, R/W, A11–A8,
A15–A12, If Selected
Figure 45. Prescaler 0 Register
(F5H: WRITE ONLY)
External Memory Timing
0 Normal
1 Extended
R246 P2M
†
For 28 pin device, the user must set:
D2=1
D3=0
D4=0
D7 D6 D5 D4 D3 D2 D1 D0
P20 - P27 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input
P04–P07 Mode
00 Output
01 Input
1X A15–A12
Figure 48. Port 0 and 1 Mode Register
(F8H: WRITE ONLY)
Figure 46. Port 2 Mode Register
(F6H: WRITE ONLY)
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
0 Port 2 Pull-Ups Open Drain
1 Port 2 Push-Pull Active
0 P31, P32 Digital Mode
1 P31, P32 Analog Mode
0 P32 = Input
P35 = Output
1 P32 = DAV0/RDY0
P35 = RDY0/DAV0
00 P33 = Input
P34 = Output
01 P33 = Input
10 P34 = DM
11 P33 = DAV0/RDY0
P34 = RDY1/DAV1
0 P31
P36
1 P31
P36
0 P30
¬
P37
=
=
=
=
=
=
Input (TIN)
OutputOUT
(T )
DAV2/RDY2
RDY2/DAV2
Input
Output
Reserved (must be 0)
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Reserved (Must be 0)
Figure 49. Interrupt Priority Register
(F9H: WRITE ONLY)
Figure 47. Port 3 Mode Register
(F7H: WRITE ONLY)
62
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
R250 IRQ
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P30 Input
IRQ4 = T0
IRQ5 = T1
Expanded Register File
Working Register Pointer
Figure 53. Register Pointer
(FDH: READ/WRITE)
Inter Edge
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
Figure 50. Interrupt Request Register
(FAH: READ/WRITE)
R254 SPH
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Upper
Byte (SP8 - SP15)
R251 IMR
Figure 54. Stack Pointer High
(FEH: READ/WRITE)
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ0-IRQ5
(D0 = IRQ0)
1 Enables RAM Protect *
1 Enables Interrupts
* This option must be selected when ROM code is
submitted for ROM Masking, otherwise this control bit
is disabled permanently.
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
Figure 51. Interrupt Mask Register
(FBH: READ/WRITE)
Stack Pointer Lower
Byte (SP0 - SP7)
Figure 55. Stack Pointer Low
(FFH: READ/WRITE)
R252 FLAGS
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1 *
User Flag F2 *
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
* Not affected by reset
Figure 52. Flag Register
(FCH: READ/WRITE)
DS007601-Z8X0499
PRELIMINARY
63
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PACKAGE INFORMATION
Figure 56. 28-Pin DIP Package Diagram
Figure 57. 28-Pin SOIC Package Diagram
64
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Figure 58. 28-Pin PLCC Package Diagram
Figure 59. 40-Pin DIP Package Diagram
DS007601-Z8X0499
PRELIMINARY
65
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
Figure 60. 44-Pin PLCC Package Diagram
Figure 61. 44-Pin QFP Package Diagram
66
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
ORDERING INFORMATION
Z86C34
Standard Temperature
28-Pin DIP
28-Pin SOIC
Z86C3416PSC
Z86C3416SSC
28-Pin PLCC
Z86C3416VSC
Extended Temperature
28-Pin DIP
28-Pin SOIC
Z86C3416PEC
Z86C3416SEC
28-Pin PLCC
Z86C3416VEC
28-Pin PLCC
Z86C3516VSC
Extended Temperature
28-Pin DIP
28-Pin SOIC
Z86C3516PEC
Z86C3516SEC
28-Pin PLCC
Z86C3516VEC
28-Pin PLCC
Z86C3616VSC
Extended Temperature
28-Pin DIP
28-Pin SOIC
Z86C3616PEC
Z86C3616SEC
28-Pin PLCC
Z86C3616VEC
44-Pin QFP
Z86C4416FSC
Extended Temperature
40-Pin DIP
44-Pin PLCC
Z86C4416PEC
Z86C4416VEC
44-Pin QFP
Z86C4416FEC
44-Pin QFP
Z86C4516FSC
Extended Temperature
40-Pin DIP
44-Pin PLCC
Z86C4516PEC
Z86C4516VEC
44-Pin QFP
Z86C4516FEC
44-Pin QFP
Z86C4616FSC
Extended Temperature
40-Pin DIP
44-Pin PLCC
Z86C4616PEC
Z86C4616VEC
44-Pin QFP
Z86C4616FEC
Z86C35
Standard Temperature
28-Pin DIP
28-Pin SOIC
Z86C3516PSC
Z86C3516SSC
Z86C36
Standard Temperature
28-Pin DIP
28-Pin SOIC
Z86C3616PSC
Z86C3616SSC
Z86C44
Standard Temperature
40-Pin DIP
44-Pin PLCC
Z86C4416PSC
Z86C4416VSC
Z86C45
Standard Temperature
40-Pin DIP
44-Pin PLCC
Z86C4516PSC
Z86C4516VSC
Z86C46
Standard Temperature
40-Pin DIP
44-Pin PLCC
Z86C4616PSC
Z86C4616VSC
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part required.
DS007601-Z8X0499
PRELIMINARY
67
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
PRECAUTIONS (Continued)
PRECAUTIONS
1. Enabling the transmit interrupt (bit 0 in the ASCI
STAT register) does not make the device ready for
transmitter-related interrupts. The receiver interrupt
(bit 3 in the ASCI STAT register) must also be enabled.
Workaround: For transmit interrupts to be generated,
the RIE bit must also be set. When IRQ3 is generated,
the software should check the STAT register for
details on the interrupt source.
2. When using the device in full-duplex mode under interrupts (both transmit and receive interrupts enabled),
a small window exists where a transmit or receive in-
68
terrupt may be lost. This situation occurs when an interrupt is generated by one side (either the transmitter
or receiver) and, before the interrupt is serviced, another interrupt is generated by the other side. The second interrupt may be lost.
Workaround: The only workaround is not to use
transmitter interrupts when using the ASCI in fullduplex mode. Use the transmitter in polled mode and
the receiver in interrupt mode for full duplex
operation. In half-duplex operation, this anomaly does
not create a problem.
PRELIMINARY
DS007601-Z8X0499
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
CODES
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part required.
Preferred Package
Longer Lead Time
Preferred Temperature
Longer Lead Time
Speed
Environmental
P = Plastic DIP
V = Plastic Chip Carrier
F = Plastic Quad Flat Pack
S = Small Outline
Integrated Chip
S = 0°C to +70°C
E = –40°C to +105°C
16 = 16 MHz
C = Plastic Standard
Example:
The Z86C36 is a 16-MHz PLCC, 0ºC to 70ºC, with Plastic
Standard Flow.
Z
86C36
16
P
S
C
ZiLOG Prefix
Product Number
Speed
Package
Temperature
Environmental Flow
Pre-Characterization Product
The product represented by this document is newly introduced
and ZiLOG has not completed the full characterization of the
product. The document states what ZiLOG knows about this
product at this time, but additional features or nonconformance
©1999 by ZiLOG, Inc. All rights reserved. Information in this
publication concerning the devices, applications, or technology
described is intended to suggest possible uses and may be
superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY
FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES
NOT ASSUME LIABILITY FOR INTELLECTUAL
PROPERTY INFRINGEMENT RELATED IN ANY
MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE.
DS007601-Z8X0499
with some aspects of the document may be found, either by
ZiLOG or its customers in the course of further application and
characterization work. In addition, ZiLOG cautions that delivery
may be uncertain at times, due to start-up yield issues.
Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of
life support systems is not authorized. No licenses are conveyed,
implicitly or otherwise, by this document under any intellectual
property rights.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX (408) 558-8300
Internet: http://www.zilog.com
PRELIMINARY
69
Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
70
ZiLOG
PRELIMINARY
DS007601-Z8X0499