CUSTOMER P ROCUREMENT S PECIFICA TION Z86E21 CMOS Z8® OTP MICROCONTROLLER GENERAL DESCRIPTION The Z86E21 microcontroller (MCU) introduces the next level of sophistication to single-chip architecture. The Z86E21 is a member of the Z8 single-chip microcontroller family with 8 Kbytes of EPROM and 236 bytes of general purpose RAM. The Z86E21 is a pin compatible, One-Time-Programmable (OTP) version of the Z86C21. The Z86E21 contains 8 Kbytes of EPROM memory in place of the 8 Kbyte of ROM on the Z86C21. The MCU is housed in a 40-pin DIP, 44-pin Leaded ChipCarrier, or a 44-pin Quad Flat Pack, and is manufactured in CMOS technology. The ROMless pin option is available on the 44-pin versions only. The MCU can address both external memory and preprogrammed ROM which enables this Z8 microcomputer to be used in high volume applications or where code flexibility is required. Zilog’s CMOS microcontroller offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The Z86E21 architecture is based on Zilog’s 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many industrial and advanced scientific applications. The device applications demand powerful I/O capabilities. The Z86E21 fulfills this with 32-pin dedicated to input and output. These lines are grouped into four ports. Each port consists of eight lines, and is configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. There are three basic address spaces available to support this wide range of configuration: Program Memory, Data Memory and 236 General-Purpose registers. To unburden the program from coping with real-time problems such as counting/timing and serial data communication, the Z86E21 offers two on-chip counter/timers with a large number of user selectable modes, and an asynchronous receiver/transmitter (UART) (see Functional Block Description). In ROM Protect Mode, the instructions LDC, LDCI, LDE and LDEI are disabled when reading address locations %0000 to %1FFF. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS PRODUCT RECOMMENDATIONS Zilog recommends the following programming equipment for use with this One-Time-Programmable product: Recommended Revision Level Hardware Software Device Zilog Support Tool Z86E21 Z86E21 Z86E21 Z86C1200ZEM ICEBOX ™ Emulator* (*Does not support 4K/8K option.) Data I/O 3900 Programmer* (*Does not support option bits.) Data I/O Unisite Programmer* (*Does not support option bits.) Some non-Zilog programmers may have different programming waveforms, voltages and timings and not all programmers may meet the programming requirements of Zilog's One-Time-Programmable products. DC-2964-10 B 1.5 1.1 3.7 If difficulty is encountered in programming a Zilog OTP product, please contact your local Zilog sales office. 1 GENERAL DESCRIPTION (Continued) Output Input Vcc GND XTAL /AS /DS R//W /RESET Machine Timing and Instruction Control Port 3 UART ALU Counter/ Timers (2) FLAGS Interrupt Control Register Pointer Register File 256 x 8-Bit Port 0 Port 2 4 I/O (Bit Programmable) Prg. Memory 8192 x 8-Bit Port 1 4 Address or I/O (Nibble Programmable) Functional Block Diagram 2 Program Counter 8 Address/Data or I/O (Byte Programmable) PIN DESCRIPTION Standard Mode VCC 1 40 P36 XTAL2 2 39 P31 XTAL1 3 38 P27 P37 4 37 P26 P30 5 36 P25 /RESET 6 35 P24 R//W 7 34 P23 /DS 8 33 P22 32 P21 31 P20 /AS 9 P35 10 GND 11 30 P33 P32 12 29 P34 P00 13 28 P17 Z86E21 DIP P01 14 27 P16 P02 15 26 P15 P03 16 25 P14 P04 17 24 P13 P05 18 23 P12 P06 19 22 P11 20 21 P10 P07 40-Lead DIP Pin Assignments 40-Lead DIP Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1 2 3 4 5 V CC XTAL2 XTAL1 P37 P30 Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3 pin 7 Port 3 pin 0 Input Output Input Output Input 11 12 13-20 21-28 29 GND P32 P00-P07 P10-P17 P34 Ground, GND Port 3 pin 2 Port 0 pin 0,1,2,3,4,5,6,7 Port 1 pin 0,1,2,3,4,5,6,7 Port 3 pin 4 Input Input In/Output In/Output Output 6 7 8 9 10 /RESET R//W /DS /AS P35 Reset Read/Write Data Strobe Address Strobe Port 3 pin 5 Input Output Output Output Output 30 31-38 39 40 P33 P20-P27 P31 P36 Port 3 pin 3 Port 2 pin 0,1,2,3,4,5,6,7 Port 3 pin 1 Port 3 pin 6 Input In/Output Input Output 3 P25 2 P26 XTAL2 3 P27 XTAL1 4 P31 P37 5 P36 P30 6 VCC N/C PIN DESCRIPTION (Continued) Standard Mode 1 44 43 42 41 40 /RESET 7 39 N/C R//W 8 38 P24 /DS 9 37 P23 /AS 10 36 P22 P35 11 35 P21 GND 12 34 P20 P32 13 33 P33 P00 14 32 P34 P01 15 31 P17 P02 16 30 P16 R//RL 17 29 P15 Z86E21 PLCC N/C P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 18 19 20 21 22 23 24 25 26 27 28 44-Lead PLCC Pin Assignments 44-Lead PLCC Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1 2 3 4 VCC XTAL2 XTAL1 P37 Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3 pin 7 Input Output Input Output 14-16 17 18-22 23-27 P00-P02 R//RL P03-P07 P10-P14 Port 0 pin 0,1,2 ROM/ROMless control Port 0 pin 3,4,5,6,7 Port 1 pin 0,1,2,3,4 In/Output Input In/Output In/Output 5 6 7 8 P30 N/C /RESET R//W Port 3 pin 0 Not Connected Reset Read/Write Input Input Input Output 28 29-31 32 33 N/C P15-P17 P34 P33 Not Connected Port 1 pin 5,6,7 Port 3 pin 4 Port 3 pin 3 Input In/Output Output Input 9 10 11 12 13 /DS /AS P35 GND P32 Data Strobe Address Strobe Port 3 pin 5 Ground, GND Port 3 pin 2 Output Output Output Input Input 34-38 39 40-42 43 44 P20-P24 N/C P25-P27 P31 P36 Port 2 pin 0,1,2,3,4 Not Connected Port 2 pin 5,6,7 Port 3 pin 1 Port 3 pin 6 In/Output Input In/Output Input Output 4 P25 P26 P27 P31 P36 GND VCC XTAL2 XTAL1 P37 P30 33 32 31 30 29 28 27 26 25 24 23 /RESET 34 22 GND R//W 35 21 P24 /DS 36 20 P23 /AS 37 19 P22 P35 38 18 P21 GND 39 17 P20 P32 40 16 P33 P00 41 15 P34 P01 42 14 P17 P02 43 13 P16 R//RL 44 12 P15 8 9 10 11 P14 P06 7 P13 P05 6 P12 P04 5 P11 4 P10 3 P07 2 GND 1 P03 Z86E21 QFP 44-Lead QFP Pin Assignments 44-Lead QFP Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1-5 6 7-14 15 P03-P07 GND P10-P17 P34 Port 0 pin 3,4,5,6,7 Ground, GND Port 1 pin 0,1,2,3,4,5,6,7 Port 3 pin 4 In/Output Input In/Output Output 31 32 33 34 XTAL1 P37 P30 /RESET Crystal, Oscillator Clock Port 3 pin 7 Port 3 pin 0 Reset Input Output Input Input 16 17-21 22 23-25 P33 P20-P24 GND P25-P27 Port 3 pin 3 Port 2 pin 0,1,2,3,4 Ground, GND Port 2 pin 5,6,7 Input In/Output Input In/Output 35 36 37 38 R//W /DS /AS P35 Read/Write Data Strobe Address Strobe Port 3 pin 5 Output Output Output Output 26 27 28 29 30 P31 P36 GND VCC XTAL2 Port 3 pin 1 Port 3 pin 6 Ground, GND Power Supply Crystal, Oscillator Clock Input Output Input Input Output 39 40 41-43 44 GND P32 P00-P02 R//RL Ground, GND Port 3 pin 2 Port 0 pin 0,1,2 ROM/ROMless control Input Input In/Output Input 5 ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units VCC TSTG TA -0.3 -65 +7.0 +150 † Supply Voltage* Storage Temp Oper Ambient Temp V C C Notes: * Voltages on all pins with respect to GND. 13.0 V Maximum on P30-P33. † See Ordering Information Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS +5V The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram). 2.1 kΩ From Output Under Test 150 pF 9.1 kΩ Test Load Diagram 6 DC CHARACTERISTICS Sym. Parameter T A = 0°C to +70 °C Min Max Typical @ 25°C Units Conditions 7 13 VCC 0.8 V V V V IIN 250 µA P30-P33 Only Driven by External Clock Generator Driven by External Clock Generator VCC 0.8 0.4 V V V V IOH = -2.0 mA IOL = +2.0 mA VCC 0.8 10 10 V V µA µA 0V V IN +5.25V 0V V IN +5.25V VCH VCL Max Input Voltage Max Input Voltage Clock Input High Voltage Clock Input Low Voltage VIH VIL VOH VOL Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage 2.0 -0.3 2.4 VRH VRl IIL IOL Reset Input High Voltage Reset Input Low Voltage Input Leakage Output Leakage 3.8 -0.03 -10 -10 IIR ICC Reset Input Current Supply Current -50 50 60 -50 50 60 25 35 µA mA mA VCC= +5.25V, VRL = 0V @ 12 MHz @ 16 MHz ICC1 Standby Current ICC2 Standby Current 15 20 20 20 15 20 20 20 5 10 5 5 mA mA µA µA HALT Mode VIN = OV, VCC @ 12 MHz HALT Mode VIN = OV, VCC @ 16 MHz STOP Mode VIN = OV, VCC @ 12 MHz STOP Mode VIN = OV, VCC @ 16 MHz 3.8 -0.03 7 13 VCC 0.8 T A = -40°C to +105°C Min Max VCC 0.8 3.8 -0.03 2.0 -0.3 2.4 0.4 VCC 0.8 10 10 3.8 -0.03 -10 -10 Notes: I CC2 requires loading TMR (%F1H) with any value prior to STOP execution. Use this sequence: LD TMR,#00 NOP 7 AC CHARACTERISTICS External I/O or Memory Read or Write Timing Diagram R//W 13 12 Port 0, /DM 16 3 19 Port 1 A 7 -A 1 D 0 7 - D IN 0 2 9 /AS 8 18 11 4 5 /DS (Read) 6 17 10 Port 1 A 7 -A D - D OUT 7 0 0 14 15 7 /DS (Write) External I/O or Memory Read/Write Timing 8 AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table TA = 0°C to 70°C T A = -40°C to 105°C 12 MHz 16 MHz 12 MHz 16 MHz Max Min Max Min Max Min Max Min Units Notes No Symbol Parameter 1 2 3 4 TdA(AS) TdAS(A) TdAS(DR) TwAS Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req’d Valid /AS Low Width 35 45 55 35 55 40 5 6 7 8 TdAZ(DS) TwDSR TwDSW TdDSR(DR) Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req’d Valid 0 185 110 0 135 80 0 185 110 0 135 80 9 10 11 12 ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay 0 45 55 30 0 35 30 20 0 65 45 33 13 14 15 16 TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) /DS Rise to R//W Not Valid Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req’d Valid 35 35 35 30 25 30 50 35 55 17 18 19 TdAS(DS) TdDI(DS) TdDM(AS) /AS Rise to /DS Fall Delay Data Input Setup to /DS Rise /DM Valid to /AS Fall Delay 55 75 50 Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. Standard Test Load All timing references use 2.0V for a logic 1 and 0.8V for a logic 0. 20 30 220 35 45 180 130 [2,3] [2,3] [1,2,3] [2,3] ns ns ns ns [1,2,3] [1,2,3] [1,2,3] 0 50 35 25 ns ns ns ns [2,3] [2,3] [2,3] [2,3] 35 25 35 ns ns ns ns [2,3] [2,3] [2,3] [1,2,3] ns ns ns [2,3] [1,2,3] [2,3] 180 130 200 40 60 30 ns ns ns ns 250 75 255 25 35 75 310 65 75 50 230 45 60 30 Clock Dependent Formulas Number Symbol Equation 1 2 3 4 TdA(AS) TdAS(A) TdAS(DR) TwAS 0.40TpC + 0.32 0.59TpC - 3.25 2.38TpC + 6.14 0.66TpC - 1.65 6 7 8 10 TwDSR TwDSW TdDSR(DR) TdDS(A) 2.33TpC - 10.56 1.27TpC + 1.67 1.97TpC - 42.5 0.8TpC 11 12 13 14 TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) 0.59TpC - 3.14 0.4TpC 0.8TpC - 15 0.4TpC 15 16 17 18 19 TdDS(DW) TdA(DR) TdAS(DS) TsDI(DS) TdDM(AS) 0.88TpC - 19 4TpC - 20 0.91TpC - 10.7 0.8TpC - 10 0.9TpC - 26.3 9 AC CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 T 2 3 IN 4 IRQ N 5 Additional Timing AC CHARACTERISTICS Additional Timing Table No Symbol TA = 0°C to 70°C T A = -40°C to 105°C 12 MHz 16 MHz 12 MHz 16 MHz Max Min Max Min Max Min Max Min Units Notes Parameter 1 2 3 4 TpC TrC,TfC TwC TwTinL Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width 83 1000 15 5 6 7 TwTinH TpTin TrTin,TfTin Timer Input High Width Timer Input Period Timer Input Rise & Fall Times 3TpC 8TpC 100 3TpC 8TpC 100 3TpC 8TpC 100 3TpC 8TpC 100 8A 8B 9 TwIL TwIL TwIH Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times 70 3TpC 3TpC 50 3TpC 3TpC 70 3TpC 3TpC 50 3TpC 3TpC 37 75 Notes: [1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request via Port 3. [4] Interrupt request via Port 3 (P31-P33). [5] Interrupt request via Port 30. 10 62.5 1000 10 21 50 83 37 75 1000 15 62.5 1000 10 21 50 ns ns ns ns [1] [1] [1] [2] ns [2] [2] [2] ns [2,4] [2,5] [2,3] AC CHARACTERISTICS Handshake Timing Diagrams Data In Valid Data In 1 Next Data In Valid 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Output Handshake Timing 11 AC CHARACTERISTICS Handshake Timing Table No Symbol Parameter 1 2 3 4 TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) Data In Setup Time Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay 5 6 7 8 TdDAVId(RDY) TdDO(DAV) TcLDAV0(RDY) TcLDAV0(RDY) DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay 9 10 11 TdRDY0(DAV) TwRDY TdRDY0d(DAV) RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay TA = 0°C to 70°C 12 MHz 16 MHz Max Min Max Min TA = -40°C to 105°C 12 MHz 16 MHz Max Min Max Min 0 145 110 0 145 110 115 115 115 0 TpC TpC 115 115 TpC 115 TpC 0 115 110 115 115 0 0 110 115 115 0 0 110 0 145 110 115 115 0 0 © 1995 by Zilog, Inc. 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Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 12 0 145 110 115 110 115 115 Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com