Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z86E73/E74 32K OTP Z86L73/L74 32K ROM INFRARED REMOTE CONTROLLERS FEATURES Part Z86E73 Z86L73 Z86E74 Z86L74 ROM (Kbyte) 32 32 32 32 RAM* One-Time (Kbyte) Programmable 1004 Yes 492 No 1004 Yes 1004 No Speed (MHz) 8 8 8 8 ■ Expanded Register Files (ERF) ■ 31 Input/Output Lines (E73/L73) 51 Input/Output Lines (E74/L74*) *Note: With Auto Latch on Port 4, 5 and 6. * General-Purpose ■ Five Prioritized Interrupts with Programmable Polarity ■ 40-Pin DIP, 44-Pin PLCC/QFP Packages (E73/L73) 64-Pin DIP, 68-Pin PLCC Packages (E74/L74) ■ Two Comparators ■ ■ 2.0V to 3.9V Operating Range (L73/L74) 4.5V to 5.5V Operating Range (E73/E74) 8-Bit Counter/Timer with Two Capture Registers and 16-Bit Counter/Timer with One Capture Register ■ Watch-Dog Timer (WDT)/Power-On Reset (POR) ■ Low-Power Consumption (Typical: 40 mw for L73/L74) (Typical: 60 mw for E73/E74) ■ On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive 0°C to +70°C Temperature Range ■ Low-Voltage Detection and Protection ■ 32-KHz Mask Option to Disable Internal Feedback Resistor (L73/L74) ■ GENERAL DESCRIPTION The Z86E73/L73/E74/L74 are ROM-based members of Zilog's Z8® single-chip microcontroller family of infrared (IR) consumer controller processors featuring fast and flexible code execution. The Z86E73/E74 devices offer a one-time programmable (OTP) option. For applications demanding powerful I/O capabilities, the Z86E73/L73's dedicated input and output lines are grouped into four ports, and into seven ports for the Z86E74/L74. They are configurable under software control to provide timing, status signals, or parallel I/O. Four address spaces, the Program Memory, Register File, Data Memory, and Expanded Register File (ERF) support a wide range of memory configurations. Through the ERF the designer has access to three additional control registers that provide extra peripheral devices, I/O ports, and register addresses. CP95LVO0801 Two on-chip counter/timers, with a large number of selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O datacommunications. Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS 1 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y GENERAL DESCRIPTION (Continued) P00 P01 P02 P03 Register File 512 or 1K x 8-bit 4 P31 P32 P33 Port 0 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 Port 3 Register Bus Internal Address Bus 4 ROM 16K/32K x 8 Z8 Core Internal Data Bus 8 Port 1 Extended Register File P20 P21 P22 P23 P24 P25 P26 P27 Extended Register Bus Counter/Timer 8 8-Bit Port 4 8 Port 5 Machine Timing & Instruction Control Power Port 2 I/O Bit Programmable Z86E74/L74 version only 8 Port 6 4 Functional Block Diagram 2 P34 P35 P36 P37 Counter/Timer 16 16-Bit XTAL /AS /DS R/W /RESET VDD VSS Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y PIN DESCRIPTION R//W 1 40 /DS P25 2 39 P24 P26 3 P27 4 /DS P51 P50 P05 7 58 P24 P06 8 57 P23 P14 9 56 P22 34 P03 33 P13 P15 10 55 P21 32 P12 P07 11 54 P20 31 VSS VDD 11 30 12 29 VDD 12 53 P03 VDD 13 52 P13 P02 P40 14 51 P12 P11 P41 15 50 VSS P42 16 49 VSS P17 13 28 P10 XTAL2 14 27 P01 15 26 16 25 P43 17 48 P52 18 47 P57 P00 P45 19 46 P02 Pref1 P16 20 45 P46 P17 21 44 P47 XTAL2 17 24 P36 P33 18 23 P37 P34 19 22 20 21 Z86E73 (Standard Mode) Z86L73 40-Pin DIP Pin Assignments Z86E74/L74 DIP P44 P32 /AS 61 59 10 P31 4 60 P07 XTAL1 P53 P26 6 P20 P16 P54 62 5 35 Z86E73/L73 DIP 63 3 P27 6 9 2 P25 P04 P05 P15 R/W 37 P21 P14 R//RL P22 36 8 64 P23 5 7 1 38 P04 P06 P56 22 43 P11 XTAL1 23 42 P10 P35 P31 24 41 P01 /RESET P32 25 40 P00 P33 26 39 PREF1 P34 27 38 P36 P60 28 37 P37 P61 29 36 P35 /AS 30 35 /RESET P63 31 34 VSS P55 32 33 P62 Z86E74 (Standard Mode) Z86L74 64-Pin DIP Pin Assignments 3 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y 6 5 4 3 2 P21 P22 P23 P24 /DS R//RL R//W P25 P26 P27 P04 P02 P11 P10 P01 P00 P03 P13 P12 VSS VSS P20 PIN DESCRIPTION 1 44 43 42 41 40 7 39 8 9 10 11 12 13 38 37 36 35 34 33 Z86E73/L73 PLCC 14 15 16 17 32 31 30 29 Pref1 P36 P37 P35 /RESET VSS /AS P34 P33 P32 P31 VDD VDD P16 P17 XTAL2 XTAL1 P05 P06 P14 P15 P07 18 19 20 21 22 23 24 25 26 27 28 P20 P03 P13 P12 VSS VSS P02 P11 P10 P01 P00 Z86E73 (Standard Mode) Z86L73 44-Pin PLCC Pin Assignments 33 32 31 30 29 28 27 26 25 24 23 P21 P22 P23 P24 /DS R//RL R//W P25 P26 P27 P04 34 35 36 37 38 39 40 41 42 43 44 Z86E73/L73 QFP 22 21 20 19 18 17 16 15 14 13 12 VDD VDD P16 P17 XTAL2 XTAL1 P05 P06 P14 P15 P07 1 2 3 4 5 6 7 8 9 10 11 Z86E73 (Standard Mode) Z86L73 44-Pin QFP Pin Assignments 4 Pref1 P36 P37 P35 /RESET VSS /AS P34 P33 P32 P31 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y P00 P01 68 67 66 65 64 63 62 61 P10 1 P47 2 P11 3 P02 P57 4 P46 P52 5 N/C 6 VSS 7 N/C VSS 8 P13 P03 9 P12 P20 PIN DESCRIPTION (Continued) P21 10 60 PREF1 P22 11 59 P36 P23 12 58 P37 P24 13 57 P35 P50 14 56 /RESET P51 15 55 VSS /DS 16 54 P62 P53 17 53 P55 P54 18 52 N/C R//RL 19 51 P63 P56 20 50 /AS R//W 21 49 P61 N/C 22 48 P60 P25 23 47 P34 P26 24 46 P33 P27 25 45 P32 P04 26 44 P31 Z86E74/L74 PLCC XTAL1 P17 XTAL2 P16 P45 P44 P43 P42 P41 P40 VDD VDD P07 P15 P14 P06 P05 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Z86E74 (Standard Mode) Z86L74 68-Pin PLCC Pin Assignments 5 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Symbol Description Min VCC TSTG TA Supply Voltage (*) –0.3 Storage Temp. –65° Oper. Ambient Temp. Max Units +7.0 +150° † V C C Notes: * Voltage on all pins with respect to GND. † See Ordering Information. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load). From Output Under Test I Test Load Diagram CAPACITANCE TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. 6 Parameter Max Input capacitance Output capacitance I/O capacitance 12 pF 12 pF 12 pF 150 pF Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y DC CHARACTERISTICS (Z86E73/E74) Sym VCH VCL Parameter VCC TA = 0°C to +70°C Min Max Max Input Voltage 4.0V 5.5V 4.0V 0.9 VCC 7 7 VCC + 0.3 V V V 5.5V 0.9 VCC VCC + 0.3 V 40V VSS – 0.3 0.2 VCC V 5.5V VSS– 0.3 0.2 VCC V 4.0V 5.5V 4.0V 5.5V 0.7 VCC 0.7 VCC VSS – 0.3 VSS – 0.3 VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC 4.0V 5.5V 4.0V 5.5V VCC – 0.4 VCC – 0.4 0.7 0.7 Clock Input High Voltage Clock Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VOH1 Output High Voltage VOH2 Output High Voltage (P36, P37) VOL1 Output Low Voltage VOL2 Output Low Voltage Typ @ 25°C Units Conditions IIN 250 µA IIN 250 µA Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator 1.3 2.5 0.5 0.9 V V V V 1.7 3.7 V V V V IOH = –0.5 mA IOH = –0.5 mA IOH = –7 mA IOH ,= –7 mA [10] [10] IOL = 1.0 mA IOL = 4.0 mA IOL = 2.0 mA 3 Pin Max IOL = 8.0 mA 3 Pin Max IOL = 10 mA [9] 4.0V 5.5V 4.0V 0.4 0.4 0.8 0.2 0.1 0.3 V V V 5.5V 0.8 0.5 V Output Low Voltage (P20-P22, P36, P00, P01, P07) 4.0V 0.8 0.3 V 5.5V 0.8 0.5 V Reset Input High Voltage Reset Input Low Voltage Comparator Input Offset Voltage 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 0.8 VCC 0.8 VCC VSS – 0.3 VSS – 0.3 VCC VCC 0.2 VCC 0.2 VCC 25 25 1.5 3.0 0.5 0.9 10 10 V V mV mV IIL Input Leakage IOL Output Leakage 4.0V 5.5V 4.0V 5.5V –1 –1 –1 –1 1 1 1 1 <1 <1 <1 <1 µA µA µA µA VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC IIR Reset Input Current ICC Supply Current –45 –55 10 15 100 300 –20 –30 4 10 10 10 µA µA mA mA µA µA @ 8.0 MHz @ 8.0 MHz @ 32 kHz @ 32 kHz VOL2 VRH VRl VOFFSET 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V Notes [3] IOL = 10 mA 2 O/P only [9] [4, 5] [4, 5] [4, 5,11] [4, 5,11] 7 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y DC CHARACTERISTICS (Z86E73/E74) (Continued) Units 3 1 mA 5.5V 5 4 mA 4.0V 2 0.8 mA 5.5V 4 2.5 mA 4.0V 8 2 µA 5.5V 10 3 µA 4.0V 500 310 µA 5.5V 800 600 µA 75 20 3.3 13 7 2.75 ms ms V Parameter VCC ICC1 Standby Current 4.0V ICC2 Standby Current TPOR Power-On Reset VLV VCC Low Voltage Protection Notes: [1] ICC1 4.0V 5.5V Typ TA = 0°C to +70°C Min Max Typ @ 25°C Sym Max 15 5 Unit Crystal/Resonator 3.0 mA 5 mA External Clock Drive 0.3 mA 5 mA [2] GND = 0V. [3] 4.0V to 5.5V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1 = CL2 = 100 pF. [6] Same as note [4] except inputs at VCC. [7] The VLV increases as the temperature decreases. [8] Oscillator stopped. [9] Two outputs at a time, independent to other outputs. [10] One at a time. [11] 32 kHz clock driver input. 8 Frequency 8.0 MHz 8.0 MHz Conditions Notes [3] HALT Mode VIN = OV, VCC @ 8.0 MHz HALT Mode VIN = OV, VCC @ 8.0 MHz [4,5] [4,5] Clock Divide-by-16 @ 8.0 MHz Clock Divide-by-16 @ 8.0 MHz [4,5] STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is Running STOP Mode VIN = OV, VCC WDT is Running [6,8] 8 MHz max Ext. CLK Freq. [7] [4,5] [6,8] [6,8] [6,8] Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y DC CHARACTERISTICS (Z86L73/L74) Sym VCH VCL Parameter VCC Max Input Voltage 2.0V 3.9V 2.0V Clock Input High Voltage Clock Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VOH1 Output High Voltage VOH2 Output High Voltage (P36, P37) VOL1 Output Low Voltage VOL2 Output Low Voltage TA = 0°C to +70°C Min Max Typ @ 25°C Units 0.9 VCC 7 7 VCC + 0.3 V V V 3.9V 0.9 VCC VCC + 0.3 V 2.0V VSS – 0.3 0.2 VCC V 3.9V VSS– 0.3 0.2 VCC V 2.0V 3.9V 2.0V 3.9V 0.7 VCC 0.7 VCC VSS – 0.3 VSS – 0.3 VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC 2.0V 3.9V 2.0V 3.9V VCC – 0.4 VCC – 0.4 0.7 0.7 V V V V IOH = –0.5 mA IOH = –0.5 mA IOH = –7 mA IOH ,= –7 mA [10] [10] IOL = 1.0 mA IOL = 4.0 mA IOL = 2.0 mA 3 Pin Max IOL = 8.0 mA 3 Pin Max IOL = 10 mA [9] V V V 3.9V 0.8 0.5 V Output Low Voltage (P20-P22, P36, P00, P01, P07) 2.0V 0.8 0.3 V 3.9V 0.8 0.5 V Reset Input High Voltage Reset Input Low Voltage Comparator Input Offset Voltage 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 0.8 VCC 0.8 VCC VSS – 0.3 VSS – 0.3 VCC VCC 0.2 VCC 0.2 VCC 25 25 1.5 3.0 0.5 0.9 10 10 V V IOL Input Leakage 3.9V Output Leakage 2.0V –1 2.0V 3.9V –1 1 –1 –1 1 <1 1 1 <1 µA <1 <1 IIR Reset Input Current ICC Supply Current 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V –45 –55 10 15 100 300 –20 –30 4 10 10 10 VOFFSET IIL Driven by External Clock Generator Driven by External Clock Generator 1.7 3.7 0.2 0.1 0.3 VRl IIN 250 µA IIN 250 µA Driven by External Clock Generator Driven by External Clock Generator V V V V 0.4 0.4 0.8 VRH Notes [3] 1.3 2.5 0.5 0.9 2.0V 3.9V 2.0V VOL2 Conditions IOL = 10 mA 2 O/P only [9] mV mV µA VIN = OV, VCC VIN = OV, VCC µA VIN = OV, VCC µA VIN = OV, VCC µA µA mA mA µA µA @ 8.0 MHz @ 8.0 MHz @ 32 kHz @ 32 kHz [4, 5] [4, 5] [4, 5,11] [4, 5,11] 9 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y DC CHARACTERISTICS (Z86L73/L74) (Continued) Units 3 1 mA 3.9V 5 4 mA 2.0V 2 0.8 mA 3.9V 4 2.5 mA 2.0V 8 2 µA 3.9V 10 3 µA 2.0V 500 310 µA 3.9V 800 600 µA 75 20 2.15 13 7 1.7 ms ms V Parameter VCC ICC1 Standby Current 2.0V ICC2 Standby Current TPOR Power-On Reset VLV VCC Low Voltage Protection Notes: [1] ICC1 2.0V 3.9V Typ TA = 0°C to +70°C Min Max Typ @ 25°C Sym Max 15 5 Unit Crystal/Resonator 3.0 mA 5 mA External Clock Drive 0.3 mA 5 mA [2] GND = 0V. [3] 2.0V to 3.9V. [4] All outputs unloaded, I/O pins floating, inputs at rail. [5] CL1 = CL2 = 100 pF. [6] Same as note [4] except inputs at VCC. [7] The VLV increases as the temperature decreases. [8] Oscillator stopped. [9] Two outputs at a time, independent to other outputs. [10] One at a time. [11] 32 kHz clock driver input. 10 Frequency 8.0 MHz 8.0 MHz Conditions Notes [3] HALT Mode VIN = OV, VCC @ 8.0 MHz HALT Mode VIN = OV, VCC @ 8.0 MHz [4,5] [4,5] Clock Divide-by-16 @ 8.0 MHz Clock Divide-by-16 @ 8.0 MHz [4,5] STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is not Running STOP Mode VIN = OV, VCC WDT is Running STOP Mode VIN = OV, VCC WDT is Running [6,8] 8 MHz max Ext. CLK Freq. [7] [4,5] [6,8] [6,8] [6,8] Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram R//W 13 12 19 Port 0, /DM 16 Port 1 20 3 8 A7 - A0 1 D7 - D0 IN 2 9 /AS 8 11 4 5 /DS (Read) 6 17 10 Port 1 A7 - A0 D7 - D0 OUT 14 15 7 /DS (Write) External I/O or Memory Read/Write Timing 11 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y AC CHARACTERISTICS (Z86E73/E74) External I/O or Memory Read and Write Timing Table No. Symbol Parameter VCC Note [3] 1 TdA(AS) 2 TdAS(A) Address Valid to /AS Rising Delay /AS Rising to Address Float Delay 4.0V 5.5V 2.0V 5.5V 3 TdAS(DR) 4 TwAS /AS Rising to Read Data Required Valid /AS Low Width 4.0V 5.5V 4.0V 5.5V 5 Td 6 TwDSR Address Float to /DS Falling /DS (Read) Low Width 7 TwDSW /DS (Write) Low Width 8 TdDSR(DR) 9 ThDR(DS) 10 TdDS(A) 11 TdDS(AS) 12 TdR/W(AS) 13 TdDS(R/W) 14 TdDW(DSW) 15 TdDS(DW) 16 TdA(DR) 17 TdAS(DS) 18 TdDM(AS) 19 TdDS(DM) 20 ThDS(A) Units Notes ns ns ns ns [2] [1, 2] 80 80 ns ns ns ns 4.0V 5.5V 4.0V 5.5V 0 0 300 300 ns ns ns ns 165 165 ns ns ns ns [1, 2] /DS Falling to Read Data Required Valid 4.0V 5.5V 4.0V 5.5V Read Data to /DS Rising Hold Time /DS Rising to Address Active Delay 4.0V 5.5V 4.0V 5.5V 0 0 85 95 ns ns ns ns [2] /DS Rising to /AS Falling Delay R//W Valid to /AS Rising Delay 4.0V 5.5V 4.0V 5.5V 60 70 70 70 ns ns ns ns /DS Rising to R//W Not Valid Write Data Valid to /DS Falling (Write) Delay 4.0V 5.5V 4.0V 5.5V 70 70 80 80 ns ns ns ns [2] /DS Rising to Write Data Not Valid Delay Address Valid to Read Data Required Valid 4.0V 5.5V 4.0V 5.5V 70 80 ns ns ns ns [2] /AS Rising to /DS Falling Delay /DM Valid to /AS Falling Delay 4.0V 5.5V 4.0V 5.5V 100 100 55 55 ns ns ns ns /DS Rise to /DM Valid Delay /DS Rise to Address Valid Hold Time 4.0V 5.5V 4.0V 5.5V 70 70 70 70 ns ns ns ns Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] 4.0V to 5.5V. Standard Test Load. All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 12 TA = 0°C to +70°C 8.0 MHz Min Max 55 55 70 70 400 400 260 260 475 475 [2] [2] [1, 2] [1, 2] [2] [2] [2] [2] [1, 2] [2] [2] Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y AC CHARACTERISTICS (Z86L73/L74) External I/O or Memory Read and Write Timing Table No. Symbol Parameter VCC Note [3] 1 TdA(AS) 2 TdAS(A) Address Valid to /AS Rising Delay /AS Rising to Address Float Delay 2.0V 3.9V 2.0V 3.9V 3 TdAS(DR) 4 TwAS /AS Rising to Read Data Required Valid /AS Low Width 2.0V 3.9V 2.0V 3.9V 5 Td 6 TwDSR Address Float to /DS Falling /DS (Read) Low Width 7 TwDSW /DS (Write) Low Width 8 TdDSR(DR) 9 ThDR(DS) 10 TdDS(A) 11 TdDS(AS) 12 TdR/W(AS) 13 TdDS(R/W) 14 TdDW(DSW) 15 TdDS(DW) 16 TdA(DR) 17 TdAS(DS) 18 TdDM(AS) 19 TdDS(DM) 20 ThDS(A) TA = 0°C to +70°C 8.0 MHz Min Max Units Notes ns ns ns ns [2] [1, 2] 80 80 ns ns ns ns 2.0V 3.9V 2.0V 3.9V 0 0 300 300 ns ns ns ns 165 165 ns ns ns ns [1, 2] /DS Falling to Read Data Required Valid 2.0V 3.9V 2.0V 3.9V Read Data to /DS Rising Hold Time /DS Rising to Address Active Delay 2.0V 3.9V 2.0V 3.9V 0 0 85 95 ns ns ns ns [2] /DS Rising to /AS Falling Delay R//W Valid to /AS Rising Delay 2.0V 3.9V 2.0V 3.9V 60 70 70 70 ns ns ns ns /DS Rising to R//W Not Valid Write Data Valid to /DS Falling (Write) Delay 2.0V 3.9V 2.0V 3.9V 70 70 80 80 ns ns ns ns [2] /DS Rising to Write Data Not Valid Delay Address Valid to Read Data Required Valid 2.0V 3.9V 2.0V 3.9V 70 80 ns ns ns ns [2] /AS Rising to /DS Falling Delay /DM Valid to /AS Falling Delay 2.0V 3.9V 2.0V 3.9V 100 100 55 55 ns ns ns ns /DS Rise to /DM Valid Delay /DS Rise to Address Valid Hold Time 2.0V 3.9V 2.0V 3.9V 70 70 70 70 ns ns ns ns 55 55 70 70 400 400 260 260 475 475 [2] [2] [1, 2] [1, 2] [2] [2] [2] [2] [1, 2] [2] [2] Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] 2.0V to 3.9V. Standard Test Load. All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 13 P R E L I M I N A R Y AC CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 7 T 2 3 7 IN 4 5 6 IRQ N 8 9 Clock Setup 11 Stop Mode Recovery Source 10 Additional Timing 14 Z86E73/E74/L73/L74 CP95LVO0801 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y AC CHARACTERISTICS (Z86E73/E74) Additional Timing Table No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH 6 TpTin 7 TrTin,TfTin 8A TwIL 8B TwIL 9 TwIH 10 VCC Note [3] TA = 0°C to +70°C 8.0 MHz Min Max 4.0V 5.5V 4.0V 5.5V 121 121 4.0V 5.5V 4.0V 5.5V 37 37 100 70 Timer Input High Width Timer Input Period 4.0V 5.5V 4.0V 5.5V 3TpC 3TpC 8TpC 8TpC Timer Input Rise and Fall Timers Interrupt Request Low Time 4.0V 5.5V 4.0V 5.5V 100 70 Int. Request Low Time Interrupt Request Input High Time 4.0V 5.5V 4.0V 5.5V 3TpC 3TpC 3TpC 3TpC Twsm Stop-Mode Recovery Width Spec 4.0V 5.5V 4.0V 5.5V 12 12 5TpC 5TpC 11 Tost 12 Twdt Oscillator Start-up Time Watch-Dog Timer Delay Time 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V 4.0V 5.5V (5 ms) (10 ms) (20 ms) (80 ms) DC DC 25 25 Notes ns ns ns ns [1] [1] [1] [1] ns ns ns ns [1] [1] [1] [1] [1] [1] [1] [1] 100 100 12 5 25 10 50 20 225 80 Units ns ns ns ns [1] [1] [1, 2] [1, 2] [1, 3] [1, 3] [1, 2] [1, 2] ns ns 5TpC 5TpC 75 20 150 40 300 80 1200 320 ms ms ms ms ms ms ms ms [8] [8] [7] [7] [4] [4] D0 = 0 [5] D1 = 0 [5] D0 = 1 [5] D1 = 0 [5] D0 = 0 [5] D1 = 1 [5] D0 = 1 [5] D1 = 1 [5] Notes: [1] Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request through Port 3 (P33-P31). [3] Interrupt request through Port 3 (P30). [4] SMR – D5 = 0. [5] Reg. WDTMR. [6] 4.0V to 5.5V. [7] Reg. SMR – D5 = 0. [8] Reg. SMR – D5 = 1. 15 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y AC CHARACTERISTICS (Z86L73/L74) Additional Timing Table No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH 6 TpTin 7 TrTin,TfTin 8A TwIL 8B TwIL 9 TwIH 10 VCC Note [3] TA = 0°C to +70°C 8.0 MHz Min Max 2.0V 3.9V 2.0V 3.9V 121 121 2.0V 3.9V 2.0V 3.9V 37 37 100 70 Timer Input High Width Timer Input Period 2.0V 3.9V 2.0V 3.9V 3TpC 3TpC 8TpC 8TpC Timer Input Rise and Fall Timers Interrupt Request Low Time 2.0V 3.9V 2.0V 3.9V 100 70 Int. Request Low Time Interrupt Request Input High Time 2.0V 3.9V 2.0V 3.9V 3TpC 3TpC 3TpC 3TpC Twsm Stop-Mode Recovery Width Spec 2.0V 3.9V 2.0V 3.9V 12 12 5TpC 5TpC 11 Tost 12 Twdt Oscillator Start-up Time Watch-Dog Timer Delay Time 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V (5 ms) (10 ms) (20 ms) (80 ms) Notes: [1] Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. [2] Interrupt request through Port 3 (P33-P31). [3] Interrupt request through Port 3 (P30). [4] SMR – D5 = 0. [5] Reg. WDTMR. [6] 2.0V to 3.9V. [7] Reg. SMR – D5 = 0. [8] Reg. SMR – D5 = 1. 16 DC DC 25 25 Notes ns ns ns ns [1] [1] [1] [1] ns ns ns ns [1] [1] [1] [1] [1] [1] [1] [1] 100 100 12 5 25 10 50 20 225 80 Units ns ns ns ns [1] [1] [1, 2] [1, 2] [1, 3] [1, 3] [1, 2] [1, 2] ns ns 5TpC 5TpC 75 20 150 40 300 80 1200 320 ms ms ms ms ms ms ms ms [8] [8] [7] [7] [4] [4] D0 = 0 [5] D1 = 0 [5] D0 = 1 [5] D1 = 0 [5] D0 = 0 [5] D1 = 1 [5] D0 = 1 [5] D1 = 1 [5] Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Valid Data Out Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Output Handshake Timing 17 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y AC CHARACTERISTICS (Z86E73/E74) Handshake Timing Table No Symbol Parameter 1 TsDI(DAV) Data In Setup Time 2 ThDI(DAV) Data In Hold Time 3 TwDAV Data Available Width 4 TdDAVI(RDY) 5 TdDAVId(RDY) 6 TdRDYO(DAV) 7 TdDO(DAV) 8 TdDAV0(RDY) 9 TdRDY0(DAV) 10 TwRDY 11 TdRDY0d(DAV) Note: [3] 4.0V to 5.5V. 18 VCC Note [3] TA = 0°C to +70°C 8.0 MHz Min Max Data Direction 4.0V 5.5V 4.0V 5.5V 0 0 160 115 IN IN IN IN 155 110 DAV Falling to RDY Falling Delay 4.0V 5.5V 4.0V 5.5V IN IN IN IN DAV Rising to RDY Falling Delay RDY Rising to DAV Falling Delay 4.0V 5.5V 4.0V 5.5V 0 0 IN IN IN IN Data Out to DAV Falling Delay DAV Falling to RDY Falling Delay 4.0V 5.5V 4.0V 5.5V 63 63 0 0 OUT OUT OUT OUT RDY Falling to DAV Rising Delay RDY Width 4.0V 5.5V 4.0V 5.5V RDY Rising to DAV Falling Delay 4.0V 5.5V 160 115 120 80 160 115 OUT OUT OUT OUT 110 80 OUT OUT 110 80 Z86E73/E74/L73/L74 CP95LVO0801 P R E L I M I N A R Y AC CHARACTERISTICS (Z86L73/L74) Handshake Timing Table No Symbol Parameter 1 TsDI(DAV) Data In Setup Time 2 ThDI(DAV) Data In Hold Time 3 TwDAV Data Available Width 4 TdDAVI(RDY) 5 TdDAVId(RDY) 6 TdRDYO(DAV) 7 TdDO(DAV) 8 TdDAV0(RDY) 9 TdRDY0(DAV) 10 TwRDY 11 TdRDY0d(DAV) VCC Note [3] TA = 0°C to +70°C 8.0 MHz Min Max Data Direction 2.0V 3.9V 2.0V 3.9V 0 0 160 115 IN IN IN IN 155 110 DAV Falling to RDY Falling Delay 2.0V 3.9V 2.0V 3.9V IN IN IN IN DAV Rising to RDY Falling Delay RDY Rising to DAV Falling Delay 2.0V 3.9V 2.0V 3.9V 0 0 IN IN IN IN Data Out to DAV Falling Delay DAV Falling to RDY Falling Delay 2.0V 3.9V 2.0V 3.9V 63 63 0 0 OUT OUT OUT OUT RDY Falling to DAV Rising Delay RDY Width 2.0V 3.9V 2.0V 3.9V RDY Rising to DAV Falling Delay 2.0V 3.9V 160 115 120 80 160 115 OUT OUT OUT OUT 110 80 OUT OUT 110 80 Note: [3] 2.0V to 3.9V. 19