ZILOG Z86L78

PRODUCT SPECIFICATION
1
Z86L78
1
IR/LOW-VOLTAGE MICROCONTROLLER
FEATURES
Part
ROM
(KB)
RAM*
(Bytes)
I/O
Voltage
Range
Z86L78
16
493
16
2.0V to 3.9V
Note: *General-Purpose
■
Low Power Consumption: 40 mW (Typical)
■
Three Standby Modes (Typical)
– STOP - 2 µA
– HALT - 0.8 mA
– Low Voltage (<VLv)
■
Programmable Watch-Dog/Power-On Reset Circuits
■
All Digital Inputs are CMOS Levels
■
Five Priority Interrupts
– Three External
– Two Assigned to Counter/Timers
■
Two Independent Comparators with Programmable
Interrupt Polarity
■
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC (Mask Selectable), or External Clock
Drive
■
Mask Selectable Option to Enable 32 kHz Crystal
Operation
■
Special Architecture to Automate Both Generation and
Reception of Complex Pulses or Signals:
– One Programmable 8-Bit Counter/Timer with Two
Capture Registers
– One Programmable 16-Bit Counter/Timer with
One Capture Register
– Programmable Input Glitch Filter for Pulse
Reception
■
Mask-Selectable 200 KOhm Pull-Ups on Ports 0, 2, 3:
– All Eight Port 2 Bits Individually Selected
– Pull-Ups Automatically Disabled Upon Selecting
an Output.
GENERAL DESCRIPTION
Zilog's Z86L78 is a low-voltage microcontroller, a member
of the IR (Infrared) Family, with 16 KB of ROM and 493
bytes of general-purpose RAM. Manufactured in CMOS
technology and offered in 20-pin DIP or SOIC styles packages, this cost-effective, low power consumption ROMbased device offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation
capabilities, automated pulse generation/reception, and
easy hardware/software system expansion.
The Z86L78 architecture is based on Zilog's 8-bit microcontroller core, with an Expanded Register File to allow access to register mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The Z86L78 offers a flexible
DS97LVO0701
I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in
many consumer, automotive, computer peripheral, and
battery operated hand-held applications.
For applications demanding powerful I/O capabilities, the
Z86L78 provides 16 pins dedicated to input and output.
These lines are grouped into three ports, which are configurable under software control to provide timing, status signals and parallel I/O.
There are four basic address spaces available to support a
wide range of configurations: Program Memory, Register
File, Expanded Register File, and Extended Data RAM.
2-1
Z86L78
IR/Low-Voltage Microcontroller
Zilog
GENERAL DESCRIPTION (Continued)
The Register File is composed of 256 bytes of RAM, and it
includes four I/O port registers, 16 control and status registers and the rest are General-Purpose registers. The Extended Data RAM adds 256 bytes of usable general-purpose registers. The Expanded Register File consists of
two additional register groups (F and D).
Notes: Signals with a preceding front slash, "/", are active
Low, for example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
Power connections follow conventional descriptions below:
To unburden the system from coping with real-time tasks,
such as generating complex waveforms or receiving and
demodulating complex waveform/pulses, the Z86L78 offers an innovative intelligent counter/timer architecture
with 8-bit and 16-bit counter/timers (Figure 1). Additionally,
the Z86L78 features a large number of user-selectable
modes, and two on-board comparators to process analog
signals with separate reference voltages (Figure 2).
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
HI16
LO16
8
8
16-Bit
T16
1 2 4
Timer 16
16
8
8
8
SCLK
Clock
Divider
TC16H
TC16L
And/Or
Logic
HI8
LO8
8
8
Input
Glitch
Filter
Timer 8/16
Edge
Detect
Circuit
8-Bit
T8
8
TC8H
Timer 8
8
TC8L
Figure 1. Counter/Timer Block Diagram
2-2
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
Extended Data RAM
256 x 8-Bit
Register File
256 x 8-Bit
P00
Port 0
Port 3
P34
P35
P36
Register Bus
Internal
Address Bus
P07
1
P31
P32
P33
ROM
16K x 8
Z8 Core
Two Analog
Comparators
Internal Data Bus
Interrupt Control
Extended
Register
File
I/O Bit
Programmable
P20
P21
P22
P23
P24
P25
P26
P27
Extended
Register Bus
Machine
Timing
&
Instruction
Control
Power
Port 2
Counter/Timer 8
8-Bit
XTAL2
XTAL1
VDD
VSS
Counter/Timer 16
16-Bit
Figure 2. Functional Block Diagram
DS97LVO0701
2-3
Z86L78
IR/Low-Voltage Microcontroller
Zilog
PIN DESCRIPTION
P24
P25
P26
P27
VDD
XTAL2
XTAL1
P31
P32
P00
1
11
Z86L78
DIP/SOIC
10
20
P23
P22
P21
P20
VSS
P36
P35
P34
P33
P07
Figure 3. 20-Pin DIP/SOIC Pin Assignments
Table 1. 20-Pin DIP and SOIC Pin Identification
2-4
Pin No.
Symbol
Direction
10
P00
Input/Output
11
17
P07
P20
Input/Output
Input/Output
18
19
20
1
2
3
4
8
9
12
13
14
15
7
6
5
P21
P22
P23
P24
P25
P26
P27
P31
P32
P33
P34
P35
P36
XTAL1
XTAL2
VDD
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Input
Output
Output
Output
Input
Output
16
VSS
Description
Port 0 is Nibble
Programmable.
Port 2 pins are individually
configurable as input or
output
IRQ2/Modulator input
IRQ0
IRQ1
T8 output
T16 output
T8/T16 output
Crystal, Oscillator Clock
Crystal, Oscillator Clock
Power Supply
Ground
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
ABSOLUTE MAXIMUM RATINGS
Symbol
Description
Min
Max
Units
VCC
Supply Voltage (*)
–0.3
+7.0
V
TSTG
Storage Temp.
–65°
+150°
C
TA
Oper. Ambient
Temp.
†
C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period
may affect device reliability.
Note:
* Voltage on all pins with respect to Ground.
† See Ordering Information.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Figure 4).
From Output
Under Test
I
150 pF
Figure 4. Test Load Diagram
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to Ground.
Parameter
Input capacitance
Output capacitance
I/O capacitance
DS97LVO0701
Min
Max
0
0
0
12 pF
12 pF
12 pF
2-5
1
Z86L78
IR/Low-Voltage Microcontroller
Zilog
DC ELECTRICAL CHARACTERISTICS
Preliminary
TA = 0°C to +70°C
Sym
VCH
VCL
Parameter
VCC
@ 25°C
Max
Units
Conditions
V
V
IIN 250 µA
IIN 250 µA
0.9 VCC
VCC + 0.3
V
3.9V
0.9 VCC
VCC + 0.3
V
Driven by External
Clock Generator
Driven by External
Clock Generator
2.0V
VSS -0.3
0.2 VCC
V
3.9V
VSS -0.3
0.2 VCC
V
2.0V
3.9V
Clock Input
High Voltage
2.0V
Driven by External
Clock Generator
Driven by External
Clock Generator
VIH
Input High
Voltage
2.0V
3.9V
0.7 VCC
0.7 VCC
VCC + 0.3
VCC + 0.3
1.3
2.5
V
V
VIL
Input Low Voltage
2.0V
3.9V
VSS – 0.3
VSS – 0.3
0.2 VCC
0.2 VCC
0.5
0.9
V
V
VOH1
Output High
Voltage
2.0V
3.9V
VCC – 0.4
VCC – 0.4
1.7
3.7
V
V
IOH = –0.5 mA
VOH2
Output High
Voltage (P36,
P37)
Output Low
Voltage
2.0V
3.9V
0.7
0.7
V
V
IOH = –7 mA
2.0V
3.9V
0.4
0.4
0.2
0.1
V
V
IOL = 1.0 mA
IOL = <4.0 mA
VOL2
Output Low
Voltage
2.0V
3.9V
0.8
0.8
0.3
0.5
V
V
IOL = 2.0 mA
3 Pin Max
VRH
Reset Input
High Voltage
2.0V
3.9V
0.8 VCC
0.8 VCC
VCC
VCC
1.5
3.0
V
V
VRl
Reset Input
Low Voltage
2.0V
3.9V
VSS - 0.3
VSS - 0.3
0.2 VCC
0.2 VCC
0.5
0.9
VOFFSET
2.0V
3.9V
25
25
10
10
mV
mV
IIL
Comparator
Input Offset
Voltage
Input Leakage
2.0V
3.9V
-1
-1
1
1
<1
<1
µA
µA
VIN = OV, VCC
VIN = OV, VCC
IOL
Output Leakage
2.0V
3.9V
-1
-1
1
1
<1
<1
µA
µA
VIN = OV, VCC
VIN = OV, VCC
IIR
Reset Input
Current
Supply Current
(WDT Off)
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
-45
-55
10
15
100
300
-20
-30
4
10
10
10
µA
µA
mA
mA
mA
mA
@ 8.0 MHz
@ 8.0 MHz
@ 32 kHz
@ 32 kHz
VOL1
ICC
2-6
Notes
7
7
Max Input
Voltage
Clock Input
Low Voltage
Min
Typical
4,5
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
TA = 0°C to +70°C
Sym
ICC1
ICC2
VICR
TPOR
Vrf1
Parameter
Standby
Current
(WDT OFF)
Standby
Current
(WDT Off)
Input Common
Mode Voltage
Range
Power-On
Reset
Voltage
Reference
VCC
Min
Typical
Max
@ 25°C
Units
2.0V
3
1
mA
3.9V
5
4
mA
2.0V
2
0.8
mA
3.9V
4
2.5
mA
2.0V
8
2
µA
3.9V
10
3
µA
2.0V
500
310
µA
3.9V
800
600
µA
2.0V
3.9V
0
0
VCC - 1.0V
VCC - 1.0V
2.0V
3.9V
7.5
2.5
1.8
75
20
2.0
Conditions
HALT Mode
VIN=0V, VCC
@ 8.0 MHz
HALT Mode
VIN=0V, VCC
@ 8.0 MHz
Clock Divide-by-16
@ 8.0 MHz
Clock Divide-by-16
@ 8.0 MHz
STOP Mode
VIN = 0V, VCC
WDT is not Running
STOP Mode
VIN = 0V, VCC
WDT is not Running
STOP Mode
VIN = 0V, VCC
WDT is not Running
STOP Mode
VIN = 0V, VCC
WDT is not Running
V
V
13
7
ms
ms
V
Notes
1
1,2
3,5
3,5
3,5
3,5
11
8 MHz max
4
Notes:
1. GND = 0V
2. 2.0V to 3.9V
3. All outputs unloaded, I/O pins floating, inputs at rail.
4. CL1 = CL2 = 100 pF
5. Same as note [4] except inputs at V CC.
6. The Vrf1 increases as the temperature decreases.
7. Oscillator stopped
8. Two outputs at a time, independent to other outputs.
9. One at a time
10. 32 kHz clock driver input
11. For analog comparator, inputs when analog comparators are enabled.
DS97LVO0701
2-7
Z86L78
IR/Low-Voltage Microcontroller
Zilog
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Diagram
R//W
13
12
19
Port 0, /DM
16
18
Port 1
20
3
A7 - A0
1
D7 - D0 IN
2
9
/AS
8
11
4
5
/DS
(Read)
6
17
10
Port 1
A7 - A0
D7 - D0
OUT
14
15
7
/DS
(Write)
Figure 5. External I/O or Memory Read/Write Timing
2-8
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
AC CHARACTERISTICS
Preliminary
External I/O or Memory Read and Write Timing Table
1
TA = 0°C to +70°C
No
Sym
Parameter
1
TdA(AS)
Address Valid to
/AS Rising Delay
/AS Rising to Address
Float Delay
/AS Rising to Read
Data Required Valid
/AS Low Width
2
TdAS(A)
3
TdAS(DR)
4
TwAS
5
Td
6
TwDSR
Address Float to /DS
Falling
/DS (Read) Low Width
7
TwDSW
/DS (Write) Low Width
8
TdDSR(DR)
9
ThDR(DS)
10
TdDS(A)
11
TdDS(AS)
12
TdR/W(AS)
13
TdDS(R/W)
14
TdDW(DSW)
15
TdDS(DW)
16
TdA(DR)
17
TdAS(DS)
18
TdDM(AS)
19
TdDS(DM)
20
ThDS(A)
/DS Falling to Read
Data Required Valid
Read Data to
/DS Rising Hold Time
/DS Rising to Address
Active Delay
/DS Rising to /AS
Falling Delay
R//W Valid to /AS
Rising Delay
/DS Rising to
R//W Not Valid
Write Data Valid to /DS
Falling (Write) Delay
/DS Rising to Write
Data Not Valid Delay
Address Valid to Read
Data Required Valid
/AS Rising to /DS Falling
Delay
/DM Valid to /AS
Falling Delay
/DS Rise to
/DM Valid Delay
/DS Rise to Address
Valid Hold Time
VCC
MIn
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
55
55
70
70
Max
400
400
80
80
0
0
300
300
165
165
260
260
0
0
85
95
60
70
70
70
70
70
80
80
70
80
475
475
100
100
55
55
70
70
70
70
Units
Notes
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
1,2
2
1,2
1,2
1,2
2
2
2
2
2
2
2
1,2
2
2
Notes:
1. When using extended memory timing add 2 TpC.
2. Timing numbers given are for minimum TpC.
Standard Test Load
All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
DS97LVO0701
2-9
Z86L78
IR/Low-Voltage Microcontroller
Zilog
AC CHARACTERISTICS
Additional Timing Diagram
3
1
Clock
2
7
T
2
3
7
IN
4
5
6
IRQ
N
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 6. Additional Timing
2-10
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
AC CHARACTERISTICS
Preliminary
Additional Timing Table
1
TA = 0°C to +70°C
8.0 MHz
No
Symbol
Parameter
1
TpC
Input Clock Period
2
TrC,TfC
3
TwC
Clock Input Rise
and Fall Times
Input Clock Width
4
TwTinL
5
TwTinH
6
TpTin
7
TrTin,TfTin
Timer Input
Low Width
Timer Input
High Width
Timer Input Period
Timer Input Rise
and Fall Timers
Interrupt Request
Low Time
Int. Request
Low Time
Interrupt Request
Input High Time
Stop-Mode Recovery Width
Spec
8A
TwIL
8B
TwIL
9
TwIH
10
Twsm
11
Tost
Oscillator Start-up Time
12
Twdt
Watch-Dog Timer (5 ms)
Delay Time
(10 ms)
(15 ms)
(80 ms)
VCC
Min
Max
Units
Notes
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
121
121
DC
DC
25
25
ns
ns
ns
ns
ns
ns
ns
ns
100
100
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1,2
1,3
1,3
1,2
1,2
5
5
4
4
4
4
37
37
100
70
3TpC
3TpC
8TpC
8TpC
100
70
5TpC
5TpC
5TpC
5TpC
12
12
5TpC
5TpC
10
5
30
10
50
20
200
80
ns
ns
ns
ns
5TpC
5TpC
75
20
150
40
300
80
1200
320
ms
ms
ms
ms
ms
ms
ms
ms
Notes:
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
3. Interrupt request through Port 3 (P30).
4. SMR – D5 = 0
5. SMR – D5 =1
DS97LVO0701
2-11
Z86L78
IR/Low-Voltage Microcontroller
Zilog
AC CHARACTERISTICS
Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
2
1
3
/DAV
(Input)
Delayed DAV
5
4
RDY
(Output)
6
Delayed RDY
Figure 7. Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV
(Output)
Delayed DAV
8
9
11
10
RDY
(Input)
Delayed
RDY
Figure 8. Output Handshake Timing
2-12
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
AC CHARACTERISTICS
Preliminary
Handshake Timing Table
1
TA = 0°C to +70°C
8 MHz
No
Symbol
Parameter
1
TsDI(DAV)
Data In Setup Time
2
ThDI(DAV)
Data In Hold Time
3
TwDAV
Data Available Width
4
TdDAVI(RDY)
5
TdDAVId(RDY)
6
TdRDYO(DAV)
7
TdDO(DAV)
8
TdDAV0(RDY)
9
TdRDY0(DAV)
10
TwRDY
DAV Falling to RDY
Falling Delay
DAV Rising to RDY
Falling Delay
RDY Rising to DAV
Falling Delay
Data Out to DAV
Falling Delay
DAV Falling to RDY
Falling Delay
RDY Falling to DAV
Rising Delay
RDY Width
11
TdRDY0d(DAV)
RDY Rising to DAV
Falling Delay
VCC
Min
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
2.0V
3.9V
0
0
160
115
155
110
Max
160
115
120
80
0
0
63
63
0
0
160
115
110
80
110
80
Data
Direction
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Notes:
Writing or reading the Extended Data RAM is accomplished by using LDE instruction only.
DS97LVO0701
2-13
Z86L78
IR/Low-Voltage Microcontroller
Zilog
PIN FUNCTIONS
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, or RC
network or an external single-phase clock to the on-chip
oscillator input.
XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, LC, or RC
network to the on-chip oscillator output.
Port 0 (P07 and 00). Port 0 is an 2-bit, bidirectional,
CMOS-compatible port. These two I/O lines are configured
under software control, and the output drivers are pushpull.
If one or both bits are needed for I/O operation, they must
be configured by writing to the Port 0 mode register. After
a hardware reset, Port 0 is configured as an input port.
An optional 200 KOhm pull-up is available as a mask option on P07 and P00.
These pull-ups are disabled when configured (bit by
bit) as outputs.
1
Z86L78
MCU
Port 0
1
Mask
Option
OEN
200 kΩ
PAD
Out
In
Figure 9. Port 0 Configuration
2-14
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask
option is available to connect eight 200 KOhm (±50%) pullup resistors on this port. Bits programmed as outputs are
globally programmed as either push-pull or open-drain.
Z86L78
MCU
The Z86L78 wakes up with the eight bits of Port 2 configured as inputs with open-drain outputs.
Port 2 also has an 8-bit input OR and an AND gate which
can be used to wake up the part (Figure 33). P20 can be
programmed to access the edge selection circuitry (Figure
10).
Port 2 (I/O)
VCC
Open-Drain
200 kΩ
OEN
Mask
Option
Pad
Out
In
Figure 10. Port 2 Configuration
DS97LVO0701
2-15
1
Z86L78
IR/Low-Voltage Microcontroller
Zilog
PIN FUNCTIONS (Continued)
Port 3 (P37-P31). Port 3 is a 6-bit, CMOS-compatible
three fixed input and four fixed output port. Port 3 and can
be configured under software control for Input/Output, Interrupt, and output from the counter/timers. P31, P32, and
P33 are standard CMOS inputs. Outputs P34, P35 are
push-pull or open-drain depending on P3M D0. P36 is
push-pull.
Two on-board comparators process analog signals on P31
and P32 with reference to the voltage on P33. The analog
function is enabled by programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge triggered interrupts (IRQ register bits 6
and 7). P33 is the comparator reference voltage inputs.
Access to the edge detection circuit is through P31 or P20.
P33 will be in common to both comparators.
Port 3 provides output for each of the counter/timers and
the AND/OR Logic. Control is performed by programming
bits D5-D4 of CTRI, bit 0 of CTR0 and bit 0 of CTR2.
Table 2. Port 3 Pin Assignments
Pin
Pref1
P31
P32
P33
P34
P35
P36
P00
I/O
IN
IN
IN
IN
OUT
OUT
OUT
I/O
C/T
ISP
T8
T16
T8/16
Comp.
RF1
AN1
AN2
RF2
A01
Int.
P0 HS
P1 HS
IRQ2
P2 HS
Ext
D/R
D/R
IRQ1
D/R
R/D
DM
R/D
R/D
Notes:
HS = Handshake Signals
D = /DAV
R = RDY
Comparator Inputs. In Analog Mode, Port 3, P31 and P32
have a comparator front end. The comparator reference
voltages are on P33. The internal P33 register and its corresponding IRQ1 is connected to the Stop-Mode Recovery
source selected by the SMR. In this mode, any of the StopMode Recovery sources can be used to toggle the P33 bit
or generate IRQ1. In digital mode, P33 can be used as a
Port 3 register input or IRQ1 for P33 (Figure 9).
Notes: Comparators are powered down by entering STOP
Mode. For P33-P31 to be used as a STOP-mode recovery
source, these inputs must be placed into digital mode.
2-16
Comparator Outputs. Comparator output of COMP1 can
be programmed to output on P34 through the PCON register (Figure 8).
/RESET (Input, active Low). Initializes the MCU. Reset is
accomplished either through Power-On, Watch-Dog Timer; Stop-Mode Recovery, and Low Voltage detection. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the internal reset Low for
the POR time.
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
P34
P34 OUT
P31
1
PAD
P34 OUT
+
CTR0
P33
D0
0 Normal Control
1 8-bit Timer output active
**P37
Counter/Timer
T8
**P37
PAD
P34 OUT
P32
+
-
P33
PCON
D0
0 = P34, P37 Standard Output *
1 = P34, P37 Comparator Output
Notes:
* Reset condition.
** Available only on 40-pin versions of the L7X family.
Figure 11. Port 3 Configuration
DS97LVO0701
2-17
Z86L78
IR/Low-Voltage Microcontroller
Zilog
PIN FUNCTIONS (Continued)
Program execution begins at location 000CH, 5-10 TpC
cycles after the RST is asserted. For Power-On Reset, the
typical reset output time is 5 ms.
Note: The Z86L78 does not reset WDTMR, SMR, P2M,
or P3M registers on a Stop-Mode Recovery operation.
Pref1
200 KΩ
P31
P32
Z86LXX
MCU
P33
Mask
Option
Port 3
(I/O or Handshake)
P34
P35
Note:
P31, 32, 33 have a 200 KΩ
mask option called Mask
option 3 similar to Mask
options 1 and 2.
P36
P37
R247 = P3M
D1
1 = Analog
0 = Digital
DIG.
P31 (AN1)
IRQ2, TIN, P31 Data Latch
+
Pref1*
AN.
-
P32 (AN2)
IRQ0, P32 Data Latch
+
P33 (REF2)
-
IRQ1, P33 Data Latch
From Stop-Mode
Recovery Source
Figure 12. Port 3 Configuration
2-18
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
CTR0, D0
Out 34
T8_Out
VDD
1
MUX
Pad
P34
CTR2, D0
VDD
Out 35
MUX
Pad
T16_Out
P35
CTR1, D6
VDD
Out 36
T8/16_Out
MUX
Pad
P36
Figure 13. Port 3 Configuration
DS97LVO0701
2-19
Z86L78
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION
The Z86L78 incorporates special features to enhance the
standard Z8 core architecture to provide the user with increased design flexibility in the areas of consumer and battery operated applications.
Reset. The device is reset in one of the following conditions:
1. Power-On Reset
3. Stop-Mode Recovery Source
4. Low Voltage Detection
Program Memory. The Z86L78 addresses up to 16 KB of
internal program memory (Figure 14). The first 12 bytes of
program memory are reserved for the interrupt vectors.
These locations contain five 16-bit vectors that correspond
to the five available interrupts. Addresses to 16K consist of
on-chip mask-programmed ROM.
2. Watch-Dog Timer
65535
256 bytes internal data RAM
65280
16384
Location of
First Byte of
Instruction
Executed
After RESET
12
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
Not Addressable
On-Chip
ROM
Reset Start Address
11
Reserved
10
Reserved
9
IRQ4
8
IRQ4
7
IRQ3
6
IRQ3
5
IRQ2
4
IRQ2
3
IRQ1
2
IRQ1
1
IRQ0
0
IRQ0
Figure 14. Program Memory Map
2-20
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
RAM. The Z86L78 has 512-bytes of RAM and 256 bytes
make-up the Register file. The remaining 256 bytes make
up the Extended Data RAM.
Extended Data RAM. The Extended Data RAM occupies
the address range. FF00H-FFFFH (256 bytes). Accessing
the Extended Data RAM is accomplished by using LDE instruction only.
Note: The Extended Data RAM cannot be used as Stack
or instructions/code memory.
Expanded Register File (ERF). The standard Z8 register
file has been expanded to allow for additional system control registers, and for mapping of additional peripheral devices along with I/O ports into the register address area.
The Z8 register address space R0 through R15 has been
implemented as 16 groups of 16 registers per group.
These register groups are known as the Expanded Register File (ERF). Bits 7-4 of register RP select the working
register group. Bits 3-0 of register RP select the expanded
register group (Figure 16).
The upper nibble of the register pointer (Figure 18) selects
which group of 16 bytes in the register file, out of the full
256 bytes, will be accessed. The lower nibble selects the
expanded register file bank and, in the case of the Z86L78,
Banks F and D are implemented. A 0H in the lower nibble
will allow the normal register file to be addressed, but any
other value from 1H to FH will exchange the lower 16 registers in favor of an expanded register group of 16 registers.
For example:
Z86L78: (See Figure 17)
R253 RP = 00H
R0 = Port 0
R1 = Port 1
R2 = Port 2
R3 = Port 3
But if:
R253 RP = 0DH R0 = CTRL0
R1 = CTRL1
R2 = CTRL2
R3 = Reserved
R253 RP
D7 D6 D5
D4 D3 D2
The counter/timers are mapped into ERF group D. Access
is easily done using the following example:
D1 D0
Expanded Register
File Pointer
Default Setting After Reset = 0000 0000
Working Register
Pointer
LD RP, #0DH Select ERF D for access and register Bank
0 as the working register group
LD R0,#xx access CTRL0
LD1, #xx access CTRL1
Figure 15. Register Pointer Register
LDRP, #7DH Select expanded register group (ERF) group
D for access and register Bank 7 as the working register bank
LDR1, 2 CTRL2 → register 71H
DS97LVO0701
2-21
1
Z86L78
IR/Low-Voltage Microcontroller
Zilog
Z8® STANDARD CONTROL REGISTERS
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER**
REGISTER POINTER
7
6
5
4
3
2
1
0
Expanded Register
Group Pointer
Working Register
Group Pointer
*
*
FF
SPL
U
U
U
U
U
U
U
U
FE
SPH
U
U
U
U
U
U
U
U
FD
RP
0
0
0
0
0
0
0
0
FC
FLAGS
U
U
U
U
U
U
U
U
FB
IMR
0
U
U
U
U
U
U
U
FA
IRQ
0
0
0
0
0
0
0
0
F9
IPR
U
U
U
U
U
U
U
U
F8
P01M
0
1
0
0
1
1
0
1
F7
P3M
0
0
0
0
0
0
0
0
F6
P2M
1
1
1
1
1
1
1
1
F5
U
Reserved
U
U
U
U
U
U
U
FF
F4
Reserved
U
U
U
U
U
U
U
U
FO
F3
Reserved
U
U
U
U
U
U
U
U
F2
Reserved
U
U
U
U
U
U
U
U
F1
Reserved
0
0
0
0
0
0
0
0
F0
Reserved
0
U
U
0
0
0
0
0
U
U
U
0
1
1
0
1
U
0
U
0
0
0
U
U
0
0
1
0
0
0
U
0
U
U
U
U
U
U
U
0
Z8 Register File**
EXPANDED REG. GROUP (F)
REGISTER**
*
7F
Reserved
†
Reserved
0F
00
EXPANDED REG. GROUP (0)
REGISTER**
*
*
*
(F) 0F
WDTMR
(F) 0E
Reserved
(F) 0D
SMR2
(F) 0C
Reserved
(F) 0B
SMR
(F) 0A
Reserved
(F) 09
Reserved
(F) 08
Reserved
(F) 07
Reserved
(F) 06
Reserved
(F) 05
Reserved
(F) 04
Reserved
(F) 03
Reserved
(F) 02
Reserved
(F) 01
Reserved
(F) 00
PCON
RESET CONDITION
RESET CONDITION
(0) 03
P3
0
0
0
0
U
U
U
U
(0) 02
P2
U
U
U
U
U
U
U
U
EXPANDED REG. GROUP (D)
REGISTER**
RESET CONDITION
(D) 0C
Reserved
(D) 0B
HI8
U
U
U
U
U
U
U
U
(D) 0A
L08
U
U
U
U
U
U
U
U
(D) 09
HI16
U
U
U
U
U
U
U
U
(D) 08
L016
U
U
U
U
U
U
U
U
(D) 07
TC16H
U
U
U
U
U
U
U
U
Notes:
(D) 06
TC16L
U
U
U
U
U
U
U
U
U = Unknown
(D) 05
TC8H
U
U
U
U
U
U
U
U
(D) 04
TC8L
U
U
U
U
U
U
U
U
† Will not be reset with a Stop-Mode Recovery, except Bit 0.
(D) 03
Reserved
0' L78 is undefined.
(D) 02
CTR2
0
U
U
U
U
U
U
0
(D) 01
CTR1
0
0
U
U
U
U
U
U
(D) 00
CTR0
0
U
U
U
U
U
U
0
(0) 01
P1
U
U
U
U
U
U
U
U
(0) 00
P0
U
U
U
U
U
U
U
U
* Will not be reset with a Stop-Mode Recovery.
** All addresses are in Hexadecimal.
Figure 16. Expanded Register File Architecture
2-22
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
Register File. The register file (group 0) consists of four
I/O port registers, 236 general-purpose registers, and 16
control and status registers (R0-R3, R4-R239, and R240R255, respectively), Plus two expanded registers groups
(Banks D and F). Instructions can access registers directly
or indirectly through an 8-bit address field. This allows a
short, 4-bit register address using the Register Pointer
(Figure 15). In the 4-bit mode, the register file is divided
into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group. Note:
r7 r 6 r5 r 4
Registers E0-EF of Bank 0 are only accessed through
working registers and indirect addressing modes.
Stack. The Z86L78 internal register file is used for the
stack. An 8-bit Stack Pointer (R255) is used for the internal
stack that resides within the general-purpose registers
(R4-R239). SPH is used as a general-purpose register
only when using internal stacks. Note: Only the lower 256
bytes of RAM may be used for stack operations.
Note: When SPH is used as a general-purpose register
and Port 0 is in address mode, the contents of SPH will be
loaded into Port 0 whenever the internal stack is accessed.
r3 r 2 r1 r 0
R253
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group
FF
R15 to R0
F0
Specified Working
Register Group
2F
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register
20
1F
Register Group 1
R15 to R0
Register Group 0
R15 to R4
10
0F
00
I/O Ports
R3 to R0
Figure 17. Register Pointer
DS97LVO0701
2-23
1
Z86L78
IR/Low-Voltage Microcontroller
Zilog
Counter/Timer Register Description
Expanded Register Group D
(D)%0C
(D)%0B
(D)%0A
(D)%09
(D)%08
(D)%07
(D)%06
(D)%05
(D)%04
(D)%03
(D)%02
(D)%01
(D)%00
Reserved
HI8
LO8
HI16
LO16
TC16H
TC16L
TC8H
TC8L
Reserved
CTR2
CTR1
CTR0
HI16(D)%09: Holds the captured data from the output of
the 16-bit Counter/Timer16. This register holds the MSByte of the data.
Field
Bit Position
T16_Capture_HI
76543210
Description
R
W
Captured Data
No Effect
L016(D)%08: Holds the captured data from the output of
the 16-bit Counter/Timer16. This register holds the LSByte of the data.
Field
Bit Position
T16_Capture_LO
76543210
Description
R
Captured Data
No Effect
W
TC16H(D)%07: Counter/Timer2 MS-Byte Hold Register.
Register Description
HI8(D)%0B: Holds the captured data from the output of the
8-bit Counter/Timer0. This register is typically used to hold
the number of counts when the input signal is 1.
Field
Bit Position
T16_Data_HI
76543210
Description
R/W
Data
TC16L(D)%06: Counter/Timer2 LS-Byte Hold Register.
Field
Bit Position
T8_Capture_HI
76543210
Description
R
W
Captured Data
No Effect
L08(D)%0A: Holds the captured data from the output of
the 8-bit Counter/Timer0. This register is typically used to
hold the number of counts when the input signal is 0.
Field
Bit Position
T8_Capture_L0
76543210
Bit Position
T16_Data_LO
76543210
Description
R/W
Data
TC8H(D)%05: Counter/Timer8 High Hold Register.
Field
Bit Position
T8_Level_HI
76543210
Description
R/W
Data
Description
R
W
2-24
Field
Captured Data
No Effect
TC8L(D)%04: Counter/Timer8 Low Hold Register.
Field
Bit Position
T8_Level_LO
76543210
Description
R/W
Data
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
CTR0 (D)00: Counter/Timer8 Control Register.
Field
Bit Position
Value
T8_Enable
7-------
R
Single/Modulo-N
-6------
R/W
Time-Out
--5-----
R
T8_Clock
---43---
R/W
Capture_INT_MASK
-----2--
R/W
Counter_INT_Mask
------1-
R/W
P34_Out
-------0
R/W
0*
1
0
1
0
1
0
1
0
1‘
00
01
10
11
0
1
0
1
0*
1
Description
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Modulo-N
Single Pass
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
SCLK
SCLK/2
SCLK/4
SCLK/8
Disable Data Capture Int.
Enable Data Capture Int.
Disable Time-Out Int.
Enable Time-Out Int.
P34 as Port Output*
T8 Output on P34
Note: *Indicates the value upon Power-On Reset
CTR0: Counter/Timer8 Control Register Description
T8 Clock. Defines the frequency of the input signal to T8.
T8 Enable. This field enables T8 when set (written) to 1.
Capture_INT_Mask. Set this bit to allow interrupt when
data is captured into either LO8 or HI8 upon a positive or
negative edge detection in demodulation mode.
Single/Modulo-N. When set to 0 (modulo-n), the counter
reloads the initial value when the terminal count is
reached. When set to 1 (single pass), the counter stops
when the terminal count is reached.
Time-Out. This bit is set when T8 times out (terminal count
reached). To reset this bit, a 1 should be written to this location. This is the only way to reset this status condition,
therefore, care should be taken to reset this bit prior to using/enabling the counter/timers.
Counter_INT_Mask. Set this bit to allow interrupt when T8
has a time out.
P34_Out. This bit defines whether P34 is used as a normal
output pin or the T8 output.
Note: Care must be taken when utilizing the OR or AND
commands to manipulate CTR0, bit 5 and CTR1, bits 0
and 1 (Demodulation Mode). These instructions use a
Read-Modify-Write sequence in which the current status
from the CTR0 and CTR1 registers will be ORed or ANDed
with the designated value and then written back into the
registers. Example: When the status of bit 5 is 1, a reset
condition will occur.
DS97LVO0701
2-25
Z86L78
IR/Low-Voltage Microcontroller
Zilog
CTR1(D)%01: Controls the functions in common with the T8 and T16.
Field
Bit Position
Value
Mode
7-------
R/W
P36_Out/Demodulator_Input
-6------
R/W
0*
1
0*
1
0
1
T8/T16_Logic/Edge Detect
--54----
R/W
00
01
10
11
00
01
10
11
Transmit_Submode/Glitch_Filter
----32--
R/W
00
01
10
11
00
01
10
11
Initial_T8_Out/Rising_Edge
------10
1
0
1
0
1
Initial_T16_Out/Falling_Edge
-------0
R/W
0
1
R
0
1
0
1
W
2-26
Description
Transmit Mode
Demodulation Mode
Transmit Mode
Port Output
T8/T16 Output
Demodulation Mode
P31
P20
Transmit Mode
AND
OR
NOR
NAND
Demodulation Mode
Falling Edge
Rising Edge
Both Edges
Reserved
Transmit Mode
Normal Operation
Ping-Pong Mode
T16_Out = 0
T16_Out = 1
Demodulation Mode
No Filter
4 SCLK Cycle
8 SCLK Cycle
16 SCLK Cycle
Transmit Mode
T8_OUT is 0 Initially
T8_OUT is 0 Initially
Demodulation Mode
No Rising Edge
Rising Edge Detected
No Effect
Reset Flag to 0
Transmit Mode
T16_OUT is 1 Initially
T16_OUT is Initially
Demodulation Mode
No Falling Edge
Falling Edge Detected
No Effect
Reset Flag to 0
DS97LVO0701
Zilog
CTR1 Register Description
Mode. If it is 0, the Counter/Timers are in the transmit
mode, otherwise they are in the demodulation mode.
P36_Out/Demodulator_Input. In Transmit Mode, this bit
defines whether P36 is used as a normal output pin or the
combined output of T8 and T16.
In Demodulation Mode, this bit defines whether the input
signal to the Counter/Timers is from P20 or P31.
T8/T16_Logic/Edge _Detect. In Transmit Mode, this field
defines how the outputs of T8 and T16 are combined
(AND, OR, NOR, NAND).
In Demodulation Mode, this field defines which edge
should be detected by the edge detector.
Transmit_Submode/Glitch Filter. In Transmit Mode, this
field defines whether T8 and T16 are in the "Ping-Pong"
mode or in independent normal operation mode. Setting
this field to "Normal Operation Mode" terminates the "PingPong Mode" operation. When set to 10, T16 is immediately
forced to a 0.
Z86L78
IR/Low-Voltage Microcontroller
In Demodulation Mode, this bit is set to 1 when a rising
edge is detected in the input signal. In order to reset it, a 1
should be written to this location.
Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0,
the output of T16 is set to 0 when it starts to count. If it is
1, the output of T16 is set to 1 when it starts to count. This
bit is effective only in Normal or Ping-Pong Mode (CTR1,
D3, D2). When this bit is set, T16_OUT will be set to the
opposite state of this bit. This insures that when the clock
is enabled a transition occurs to the initial state set by
CTR1, D0.
In Demodulation Mode, this bit is set to 1 when a falling
edge is detected in the input signal. In order to reset it, a 1
should be written to this location.
Note: Modifying CTR1, (D1 or D0) while counters are enabled will cause un-predictable output from T8/16_out.
In Demodulation Mode, this field defines the width of the
glitch that should be filtered out.
Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the
output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. When this bit is
set to 1 or 0, T8_OUT will be set to the opposite state of
this bit. This insures that when the clock is enabled a transition occurs to the initial state set by CTR1, D1.
DS97LVO0701
2-27
1
Z86L78
IR/Low-Voltage Microcontroller
Zilog
CTR2 (D)%02: Counter/Timer16 Control Register.
Field
T16_Enable
Bit Position
7-------
Value
R
W
Single/Modulo-N
-6------
0*
1
0
1
R/W
0
1
T16 _Clock
---43---
R/W
Capture_INT_Mask
-----2--
R/W
Counter_INT_Mask
------1-
R/W
0
1
0
1
0
1
00
01
10
11
0
1
0
P35_Out
-------0
R/W
0
Time_Out
--5-----
R
W
Description
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Transmit Mode
Modulo-N
Single Pass
Demodulation Mode
T16 Recognizes Edge
T16 Does Not Recognize Edge
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
SCLK
SCLK/2
SCLK/4
SCLK/8
Disable Data Capture Int.
Enable Data Capture Int.
Disable Time-Out Int.
Enable Time-Out Int.
P35 as Port Output*
T16 Output on P35
Note: * Indicates the value upon Power-On Reset.
2-28
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
CTR2 Description
T16_Clock. Defines the frequency of the input signal to
Counter/Timer16.
T16_Enable. This field enables T16 when set to 1.
Single/Modulo-N. In Transmit Mode, when set to 0, the
counter reloads the initial value when terminal count is
reached. When set to 1, the counter stops when the terminal count is reached.
In Demodulation Mode, when set to 0 , T16 captures and
reloads on detection of all the edges; when set to 1, T16
captures and detects on the first edge, but ignores the subsequent edges. For details, see the description of T16 Demodulation Mode.
Time_Out. This bit is set when T16 times out (terminal
count reached). In order to reset it, a 1 should be written to
this location.
Capture_INT_Mask. Set this bit to allow interrupt when
data is captured into LO16 and HI16.
Counter_INT_Mask. Set this bit to allow interrupt when
T16 times out.
P35_Out. This bit defines whether P35 is used as a normal
output pin or T16 output.
Port pins configured as outputs are ignored as an SMR2
recover source. For example, if NAND of P23-P20 is selected as the recover source and P20 is configured as output, then P20 is ignored as a recover source. The effective
recover source in this case is NAND of P23-P21.
SMR2(F)%0D: Stop-Mode Recovery Register 2.
Field
Bit Position
Value
Reserved
Recovery Level
7-------6------
W
Reserved
Source
--5-------432--
W
Reserved
------10
00
0
0*
1
0
000*
001
010
011
100
101
110
111
Reserved (Must be 0)
Description
Reserved (Must be 0)
Low
High
Reserved (Must be 0)
A. POR Only
B. NAND of P23-P20
C. NAND of P27-P20
D. NOR of P33-P31
E. NAND of P33-P31
F. NOR of P33-P31, P00,P07
G. NAND of P33-P31,P00,P07
H. NAND of P33-P31,P22-P20
Note: * Indicates the value upon Power-On Reset.
DS97LVO0701
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
Counter/Timer Functional Blocks
CTR1 D5,D4
P31
Glitch
Filter
MUX
P20
Edge
Detector
Pos Edge
Neg Edge
CTR1 D6
CTR1 D3,D2
Figure 18. Glitch Filter Circuitry
Z8 Data Bus
CTR0 D2
Pos Edge
IRQ4
Neg Edge
HI8
LO8
CTR0 D4, D3
SCLK
CTR0 D1
Clock
Select
Clock
TC8H
8-Bit
Counter T8
T8_OUT P34
TC8L
Z8 Data Bus
Figure 19. 8-Bit Counter/Timer Circuit
2-30
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
Input Circuit
The edge detector monitors the input signal on P31 or P20.
Based on CTR1 D5-D4, a pulse is generated at the Pos
Edge or Neg Edge line when an edge is detected. Glitches
in the input signal which have a width less than specified
(CTR1 D3, D2) are filtered out.
T8 Transmit Mode
When T8 is enabled, the output of T8 depends on CTR1,
D1. If it is 0, T8_OUT is 1. If it is 1, T8_OUT is 0.
When T8 is enabled, the output T8_OUT switches to the
initial value (CTR1 D1). If the initial value (CTR1 D1) is 0,
TC8L is loaded, otherwise TC8H is loaded into the
counter. In Single-Pass Mode (CTR0 D6), T8 counts down
to 0 and stops, T8_OUT toggles, the time-out status bit
(CTR0 D5) is set, and a time-out interrupt can be generated if it is enabled (CTR0 D1) (Figure 18). In Modulo-N
Mode, upon reaching terminal count, T8_OUT is toggled,
but no interrupt is generated. Then T8 loads a new count
(if the T8_OUT level now is 0), TC8L is loaded; if it is 1,
TC8H is loaded. T8 counts down to 0, toggles T8_OUT,
sets the time-out status bit (CTR0 D5) and generates an
interrupt if enabled (CTR0 D1) (Figure 19). This completes
one cycle. T8 then loads from TC8H or TC8L according to
the T8_OUT level, and repeats the cycle.
The user can modify the values in TC8H or TC8L at any
time. The new values take effect when they are loaded.
Care must be taken not to write these registers at the time
the values are to be loaded into the counter/timer, to ensure known operation. An initial count of 1 is not allowed (a non-function will occur). An initial count of 0
will cause TC8 to count from 0 to %FF to %FE (Note, % is
used for hexadecimal values). Transition from 0 to %FF is
not a time-out condition.
Note: Using the same instructions for stopping the
counter/timers and setting the status bits is not recommended. Two successive commands, first stopping
the counter/timers, then resetting the status bits is necessary. This is required because it takes one counter/timer
clock interval for the initiated event to actually occur.
TC8H Counts
“Counter Enable” Command,
T8_OUT Switches To Its
Initial Value (CTR1 D1)
T8_OUT Toggles,
Time-Out Interrupt
Figure 20. T8_OUT in SIngle-Pass Mode
T8_OUT Toggles
T8_OUT
TC8L
“Counter Enable” Command,
T8_OUT Switches To Its
Initial Value (CTR1 D1)
TC8H
TC8L
Time-Out Interrupt
TC8H
TC8L
Time-Out Interrupt
Figure 21. T8_OUT in Modulo-N Mode
DS97LVO0701
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
T8 Demodulation Mode
The user should program TC8L and TC8H to %FF. After
T8 is enabled, when the first edge (rising, falling, or both
depending on CTR1 D5, D4) is detected, it starts to count
down. When a subsequent edge (rising, falling, or both depending on CTR1 D5, D4) is detected during counting, the
current value of T8 is one's complemented and put into
one of the capture registers. If it is a positive edge, data is
put into LO8, if negative edge, HI8. One of the edge detect
status bits (CTR1 D1, D0) is set, and an interrupt can be
generated if enabled (CTR0 D2). Meanwhile, T8 is loaded
with %FF and starts counting again. Should T8 reach 0,
the time-out status bit (CTR0 D5) is set, an interrupt can be
generated if enabled (CTR0 D1), and T8 continues counting from %FF (Figure 23).
T8 (8-Bit)
Count Capture
No
T8_Enable
(Set By User)
Yes
Edge Present
No
Yes
What Kind Of Edge
Neg
Pos
T8 → L08
T8 → HI8
%FF → T8
Figure 22. Demodulation Mode Count Capture Flowchart
2-32
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
T8 (8-Bit)
Transmit Mode
No
1
T8_Enable Bit Set
CTR0, D7
Reset T8_Enable Bit
Yes
1
0
CTR1, D1 Value
Load TC8L
Reset T8_OUT
Load TC8H
Set T8_OUT
Set Time-out Status Bit
(CTR0 D5) and Generate
Timeout_Int If Enabled
Start T8
No
T8_OUT
Toggle
T8_Timeout
Start T8
Single Pass
Single Pass?
Modulo-N
1
0
T8_OUT Value
Load TC8L
Reset T8_OUT
Load TC8H
Set T8_OUT
Start T8
Set Time-out Status Bit
(CTR0 D5) and Generate
Timeout_Int If Enabled
No
T8_Timeout
Yes
Stop T8
Figure 23. Transmit Mode Flowchart
DS97LVO0701
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Z8 Data Bus
CTR2 D2
Pos Edge
IRQ3
Neg Edge
HI16
LO16
CTR2 D4, D3
SCLK
CTR2 D1
Clock
Select
Clock
16-Bit
Counter
T16
TC16H
T16_OUT
(P35)
TC16L
Z8 Data Bus
Figure 24. 16-Bit Counter/Timer Circuits
T16 Transmit Mode
In Normal or Ping-Pong Mode, the output of T16 when not
enabled is dependent on CTR1, D0. If it is a 0, T16_OUT
is a 1; if it is a 1, T16_OUT is 0. The user can force the output of T16 to either a 0 or 1 whether it is enabled or not by
programming CTR1 D3, D2 to a 10 or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded,
and T16_OUT is switched to its initial value (CTR1 D0).
When T16 counts down to 0, T16_OUT is toggled (in Normal or Ping-Pong Mode), an interrupt is generated if enabled (CTR2 D1), and a status bit (CTR2 D5) is set. Note
that global interrupts will override this function as described in the interrupts section. If T16 is in Single-Pass
Mode, it is stopped at this point. If it is in Modulo-N Mode,
it is loaded with TC16H * 256 + TC16L and the counting
continues.
2-34
The user can modify the values in TC16H and TC16L at
any time. The new values take effect when they are loaded. Care must be taken not to load these registers at the
time the values are to be loaded into the counter/timer, to
ensure known operation. An initial count of 1 is not allowed. An initial count of 0 will cause T16 to count from 0
to %FFFF to %FFFE. Transition from 0 to %FFFF is not a
time-out condition.
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
TC16H*256+TC16L Counts
1
“Counter Enable” Command,
T16_OUT Switches To Its
Initial Value (CTR1 D0)
T16_OUT Toggles,
Time-Out Interrupt
Figure 25. T16_OUT in Single-Pass Mode
TC16H*256+TC16L
TC16H*256+TC16L
T16_OUT
“Counter Enable” Command,
T16_OUT Switches To Its
Initial Value (CTR1 D0)
TC16H*256+TC16L
T16_OUT Toggles,
Time-Out Interrupt
T16_OUT Toggles,
Time-Out Interrupt
Figure 26. T16_OUT in Modulo-N Mode
T16 Demodulation Mode
The user should program TC16L and TC16H to %FF. After
T16 is enabled, when the first edge (rising, falling, or both
depending on CTR1 D5, D4) is detected, T16 captures
HI16 and LO16, reloads and begins counting.
If D6 of CTR2 is 0: When a subsequent edge (rising, falling, or both depending on CTR1 D5, D4) is detected during
counting, the current count in T16 is one's complemented
and put into HI16 and LO16. When data is captured, one
of the edge detect status bits (CTR1 D1, D0) is set and an
interrupt is generated if enabled (CTR2 D2). T16 is loaded
with %FFFF and starts again.
DS97LVO0701
If D6 of CTR2 is 1: T16 ignores the subsequent edges in
the input signal and continues counting down. A time out
of T8 will cause T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16
does not reload and continues counting. If D6 bit of CTR2
is toggled (by writing a 0 then a 1 to it), T16 will capture and
reload on the next edge (rising, falling, or both depending
on CTR1 D5, D4) but continue to ignore subsequent edges.
Should T16 reach 0, it continues counting from %FFFF;
meanwhile, a status bit (CTR2 D5) is set and an interrupt
time-out can be generated if enabled (CTR2 D1).
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Ping-Pong Mode
This operation mode is only valid in Transmit Mode. T8
and T16 need to be programmed in Single-Pass Mode
(CTR0 D6, CTR2 D6) and Ping-Pong Mode needs to be
programmed in CTR1 D3, D2. The user can begin the operation by enabling either T8 or T16 (CTR0 D7 or CTR2
D7). For example, if T8 is enabled, T8_OUT is set to this
initial value (CTR1 D1). According to T8_OUT's level,
TC8H or TC8L is loaded into T8. After the terminal count
is reached, T8 is disabled and T16 is enabled. T16_OUT
switches to its initial value (CTR1 D0), data from TC16H
and TC16L is loaded, and T16 starts to count. After T16
reaches the terminal count it stops, T8 is enabled again,
and the whole cycle repeats. Interrupts can be allowed
when T8 or T16 reaches terminal control (CTR0 D1, CTR2
D1). To stop the Ping-Pong operation, write 00 to bits D3
and D2 of CTR1.
Note: Enabling Ping-Pong operation while the
counter/timers are running may cause intermittent
counter/timer function. Therefore, disable the
counter/timers, then reset the status flags prior to instituting this operation.
Enable
TC8
Time-Out
Enable
Ping-Pong
CTR1 D3,D2
TC16
Time-Out
Figure 27. Ping-Pong Mode
To Initiate Ping-Pong Mode
First, make sure both counter/timers are not running. Then
set T8 into Single-Pass Mode (CTR0 D6), set T16 into Single-Pass Mode (CTR2 D6), and set Ping-Pong Mode
(CTR1 D2, D3). These instructions do not have to be in
any particular order. Finally, start Ping-Pong Mode by enabling either T8 (CTR0 D7) or T16 (CTR2 D7).
2-36
During Ping-Pong Mode
The enable bits of T8 and T16 (CTR0 D7, CTR2 D7) will
be cleared by hardware. The time-out bits (CTR0 D5,
CTR2 D5) will be set every time the counter/timers reach
the terminal count.
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
TC8H
TC8H
1
T8_OUT Toggles
T8_OUT
Enable T8,
T8_OUT Switches
To Its Initial Value
TC16H*256+TC16L
T8_OUT Toggles
TC16H*256+TC16L
T16_OUT
T16_OUT Toggles
T16_OUT
T16_OUT Switches To Its Initial
Value When TC16 Is Enabled
Figure 28. T8_OUT and T16_OUT in Ping-Pong Mode
P34_INTERNAL
MUX
P34_EXT
CTR0 D0
P36_INTERNAL
T8_OUT
T16_OUT
CTR1, D2
AND/OR/NOR/NAND
Logic
MUX
P36_EXT
MUX
CTR1 D6
CTR1 D5,D4
CTR1 D3
P35_INTERNAL
MUX
P35_EXT
CTR2 D0
Figure 29. Output Circuit
DS97LVO0701
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z86L78 has five different interrupts, which
are maskable and prioritized (Figure 30). The five sources
are divided as follows: two are claimed by Port 3 lines P33,
P31, one by the low voltage detect circuit (IRQ0) and the
IRQ
1 3 4
remaining two by the counter/timers (Table 5). The Interrupt Mask Register globally or individually enables or disables the five interrupt requests.
IRQ0
IRQ2
Interrupt
Edge
Select
IRQ Register (D6, D7)
IRQ
IMR
5
Global
Interrupt
Enable
Interrupt
Request
IPR
Priority
Logic
Vector Select
Figure 30. Interrupt Block Diagram
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
Table 3. Interrupt Types, Sources and Vectors
Name
Source
Vector
Location
IRQ0
IRQ0
0, 1
IRQ1,
IRQ1
2, 3
IRQ2
/DAV2,
IRQ2, TIN
4, 5
IRQ3
IRQ4
T16
T8
6, 7
8, 9
Comments
External (P32),
Rising Falling Edge
Triggered
External (P33),
Falling Edge
Triggered
External (P31),
Rising Falling Edge
Triggered
Internal
Internal
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by
the Interrupt Priority register. An interrupt machine cycle is
activated when an interrupt request is granted. This disables all subsequent interrupts, saves the Program
Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt.
All Z86L78 interrupts are vectored through locations in the
program memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request register is polled to determine which
of the interrupt requests need service.
Programming bits for the Interrupt Edge Select are located
in the IRQ Register (R250), bits D7 and D6. The configuration is shown in Table 4.
Table 4. Interrupt Types, Sources, and Vectors
IRQ
Interrupt Edge
D7
D6
IRQ2(P31)
IRQ0 (P32)
0
0
1
1
0
1
0
1
F
F
R
R/F
F
R
F
R/F
Notes:
F = Falling Edge
R = Rising Edge
Notes: In analog mode, the Stop-Mode Recovery sources
selected by the SMR register are connected to the IRQ1
input. Any of the Stop-Mode Recovery sources for SMR
(except P31,P32 and P33) can be used to generate IRQ1
(falling edge triggered).
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling, or both edge triggered, and are programmable by the user. The software
can poll to identify the state of the pin.
DS97LVO0701
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1
Z86L78
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Clock. The Z86L78 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 1 MHz to 8 MHz maximum, with a series resistance
(RS) less than or equal to 100 Ohms. The Z86L7X on-chip
oscillator may be driven with a cost-effective RC network
or other suitable external clock source. For 32 kHz crystal
operation a mask option is selected which disables the internal XTAL1/2 feedback resistor. The external components for using a 32 kHz crystal include a feedback (Rf)
and serial (Rd) resistor as shown in Figure 33.
The crystal should be connected across XTAL1 and
XTAL2 using the recommended capacitors (capacitance
greater than or equal to 22 pF) from each pin to ground.
The RC oscillator configuration is an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to ground (Figure 32).
XTAL1
C1
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
1. Power Fail to Power OK status.
2. Stop-Mode Recovery (if D5 of SMR = 1).
3. WDT Time-Out.
The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode
Register determines whether the POR timer is bypassed
after Stop-Mode Recovery (typical for external clock, RC,
LC oscillators).
XTAL1
XTAL1
C1
C1
XTAL2
XTAL1
C1
XTAL1
Rf
R
L
C2
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and
the oscillator circuit to stabilize before instruction execution begins.
XTAL2
XTAL2
XTAL2
XTAL2
C2
C2
Ceramic Resonator or Crystal
C1, C2 = 47 pF TYP *
f = 8 MHz
* Preliminary value including pin parasitics
LC
C1, C2 = 22 pF
RC
@ 3V VCC (TYP)
L = 130 µH *
f = 3 MHz *
C1 = 33 pF *
R = 1K *
Rd
32 kHz XTAL
C1 = 20 pF, C = 33
pF
Rd = 56 - 470K
Rf =10 M
External Clock
Figure 31. Oscillator Configuration
2-40
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.
The devices are recovered by interrupts, either externally
or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT.
STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current
to 10 µA (typical) or less. STOP Mode is terminated only
by a reset, such as WDT time-out, POR, SMR, or external
reset. This causes the processor to restart the application
program at address 000CH.
In order to enter STOP (or HALT) Mode, it is necessary to
first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute
a NOP (opcode = FFH) immediately before the appropriate
SLEEP instruction, i.e.,
FF
6F
NOP
STOP
FF
7F
NOP
HALT
DS97LVO0701
; clear the pipeline
; enter STOP Mode
or
; clear the pipeline
; enter HALT Mode
Port Configuration Register (PCON). The PCON register configures the comparator output on Port 3. It is located in the expanded register file at Bank F, location 00 (Figure 32).
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
* Default Setting After Reset
Figure 32. Port Configuration Register (PCON)
(Write Only)
Comparator Output Port 3 (D0). Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port
to its standard I/O configuration.
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 33). All bits are Write Only
except bit 7, which is Read Only. Bit 7 is a flag bit that is
hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or
a high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits D2, D3, and D4, of
the Stop-Mode Recovery signal. Bits D0 determines if
SCLK/TCLK are divided by 16 or not.
SMR (0F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF **
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
0 11 P32
100 P33
101 P27
11 0 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery**
* Default Setting After Reset
** Default Setting After Reset and Stop-Mode Recovery
Figure 33. Stop-Mode Recovery Register
2-42
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR
controls a Divide-by-16 prescaler of SCLK/TCLK (Figure
34). The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT Mode (where TCLK
sources interrupt logic). After Stop-Mode Recovery, this bit
is set to a 0.
OSC
STOP-Mode Recovery Delay Select (D5). This bit, if
Low, disables the 5 ms /RESET delay after Stop-Mode Recovery. The default configuration of this bit is one. If the
"fast" wake up is selected, the Stop-Mode Recovery
source needs to be kept active for at least 5TpC.
STOP-Mode Recovery Edge Select (D6). A 1 in this bit
position indicates that a High level on any one of the recovery sources wakes the Z86L78 from STOP Mode. A 0 indicates Low level recovery. The default is 0 on POR (Figure 35).
÷2
SCLK
÷ 16
SMR, D0
TCLK
Figure 34. SCLK Circuit
STOP-Mode Recovery Source (D2, D3, and D4). These
three bits of the SMR specify the wake up source of the
STOP recovery (Figure 35 and Table 5).
Table 5. STOP-Mode Recovery Source
SMR: 432
D4
D3
D2
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
DS97LVO0701
Note: Any Port 2 bit defined as an output will drive the corresponding input to the default state to allow the remaining
inputs to control the AND/OR function. Refer to SMR2 register for other recover sources.
Operation
Description of Action
POR and/or external reset
recovery
Reserved
P31 transition
P32 transition
P33 transition
P27 transition
Logical NOR of P20 through
P23
Logical NOR of P20 through
P27
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. It is a Read Only Flag bit. A 1
in D7 (warm) indicates that the device will awaken from a
SMR source or a WDT while in STOP Mode. A 0 in this bit
(cold) indicates that the device will be rest by a POR, WDT
while not in STOP, or the device awakened from a low voltage standby mode.
Stop-Mode Recovery Register 2 (SMR2). This register
determines the mode of stop mode recovery for SMR2
(Figure 36).
If SMR2 is used in conjunction with SMR, either of the
specified events will cause a Stop-Mode Recovery.
Note: Port pins configured as outputs are ignored as a
SMR or SMR2 recovery source. For example, if the NAND
of P23-20 is selected as the recovery source and P20 is
configured as an output then the remaining SMR pins
(P23-P21) form the NAND equation.
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Z86L78
IR/Low-Voltage Microcontroller
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FUNCTIONAL DESCRIPTION (Continued)
SMR2 (0F) 0DH
D7 D6
D5
D4
D3
D2
D1
D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR only*
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved
(Must be 0)
Recovery Level
0 Low*
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR,
either of the two specified events will
cause a Stop-Mode Recovery.
*Default Setting After Reset
Figure 35. Stop-Mode Recovery Register 2
((0F) DH: D2-D4, D6 Write Only
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Z86L78
IR/Low-Voltage Microcontroller
Zilog
SMR2 D4 D3 D2
0 0 0
SMR D4 D3 D2
0 0 0
1
VCC
VCC
SMR2 D4 D3 D2
0 0 1
SMR D4 D3 D2
0 1 0
P20
P31
S1
P23
SMR2 D4 D3 D2
0 1 0
SMR D4 D3 D2
0 1 1
P20
P32
S2
P27
SMR2 D4 D3 D2
0 1 1
SMR D4 D3 D2
1 0 0
P33
S3
P31
P32
P33
To IRQ1
SMR2 D4 D3 D2
1 0 0
S4
SMR D4 D3 D2
1 0 1
P31
P32
P33
P27
SMR D4 D3 D2
1 1 0
P20
P23
SMR D4 D3 D2
1 1 1
P20
P27
P31
P32
P33
P00
P07
P31
P32
P33
P00
P07
SMR D6
P31
P32
P33
P20
P21
P22
To RESET and WDT
Circuitry (Active Low)
SMR2 D4 D3 D2
1 0 1
SMR2 D4 D3 D2
1 1 0
SMR2 D4 D3 D2
1 1 1
SMR2 D6
Figure 36. Stop-Mode Recovery Source
DS97LVO0701
2-45
Z86L78
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction and refreshed on
subsequent executions of the WDT instruction. The WDT
circuit is driven by an on-board RC oscillator or external
oscillator from the XTAL1 pin. The WDT instruction affects
the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source is selected with bit 4 of the WDT
register. Bit 0 and 1 control a tap circuit that determines the
time-out period. Bit 2 determines whether the WDT is active during HALT and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 38). This register is accessible only during the first 64 processor cycles
(128 XTAL clocks) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a StopMode Recovery (Figure 35). After this point, the register
cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in Bank
F of the Expanded Register Group at address location
0FH. It is organized as follows:
WDTMR (0F) F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01 *
10
11
INT RC OSC External Clock
5 ms
256 TpC
10 ms
512 TpC
20 ms
1024 TpC
80 ms
4096 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
* Default Setting After Reset
Figure 37. Watch-Dog TImer Mode Register
(Write Only)
2-46
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
WDT Time Select (D0, D1). Selects the WDT time period.
It is configured as shown in Table 6.
WDTMR During HALT (D2). This bit determines whether
or not the WDT is active during HALT Mode. A 1 indicates
active during HALT. The default is 1.
Table 6. WDT TIme Select
D1
D0
Time-Out of
Internal RC
OSC
0
0
1
1
0
1
0
1
5 ms min
10 ms min
20 ms min
80 ms min
Time-Out of
XTAL Clock
256 TpC
512 TpC
1024 TpC
4096 TpC
WDTMR During STOP (D3). This bit determines whether
or not the WDT is active during STOP Mode. Since the
XTAL clock is stopped during STOP Mode, the on-board
RC has to be selected as the clock source to the
WDT/POR counter. A 1 indicates active during STOP. The
default is 1.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configuration of this bit is 0, which selects the RC oscillator.
Notes:
TpC = XTAL clock cycle
The default on reset is 10 ms
/RESET
5 Clock
Filter
* CLR 2
CLK
18 Clock RESET
Generator
RESET
Internal
RESET
Active
High
WDT TAP SELECT
CK Source
Select
(WDTMR)
XTAL
M
U
X
INTERNAL
RC
OSC.
VDD
VBO/VLV
2V REF.
+
-
POR
3
4
WDT1 2
CLK
WDT/POR Counter Chain
*CLR1
Low Operating
Voltage Det.
WDT
From Stop
Mode
Recovery
Source
12 ns Glitch Filter
Stop Delay
Select (SMR)
* /CLR1 and /CLR2 enable the WDT/POR and
18 Clock Reset timers upon a Low to High input translation.
Figure 38. Resets and WDT
DS97LVO0701
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1
Z86L78
IR/Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Reset Functional Operation. Reset is internally driven
by four sources:
Note: The internal clock frequency is one-half the external
clock frequency.
1. POR. (0 volts to operating voltage condition) usually
occurs upon powering up the MCU.
The device functions normally at or above Vrf1 under all
conditions (Figure 39).
2. WDT. The WDT counts down and generates a reset,
usually to "wake" the part from a "sleep" condition.
Mask Selectable Options. There are five Mask Selectable Options to choose from based on ROM code requirements. These are:
3. Low Voltage Detection/Standby. An on-chip Voltage
Comparator checks that the VCC is at the required
level for correct operation of the device. Reset is
globally driven when VCC falls below VLV (Vrf1). A
small further drop in VCC causes the XTAL1 and
XTAL2 circuitry to stop the crystal or resonator clock.
Typical power consumption in this Low Voltage
Standby mode (ILV) is about 45 µA (varying with the
number of Masks selectable options enabled). When
the power level is returned to above VLV, the device
will perform a POR and function normally. If the VCC is
allowed to stay above 1.5V, the RAM content is
preserved. Low Voltage Standby was designed to
allow the device to draw power from board level
decoupling capacitors during battery changes.
4. Stop Mode Recovery (Partial reset).
Low Voltage Protection. An on-board Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. Reset is globally driven if VCC
is below Vrf1.
RC/Other
Clock Source
Port 0 Pull-ups
Port 2 Pull-ups
Port 3 Pull-ups
32 kHz Option
On/Off
On/Off
On/Off
On/Off
Vrf1
T
B
D
Maximum (Vrf1) Conditions:
TA = 0°C, +70°C Internal clock frequency equal to or less
than 4.0 MHz
0
15
25
45
35
Temperature
55
70°C
Figure 39. Z86L78 Low Voltage
vs Temperature at 8 MHz
2-48
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
EXPANDED REGISTER FILE CONTROL REGISTERS (0D)
1
CTR0 (0D) 0H
D7 D6 D5 D4 D3 D2 D1 D0
0 P34 as Port Output*
1 Timer8 Output
0 Disable T8 Time Out Interrupt
1 Enable T8 Time Out Interrupt
0 Disable T8 Data Capture Interrupt
1 Enable T8 Data Capture Interrupt
00
01
10
11
R
R
W
W
SCLK on T8
SCLK/2 on T8
SCLK/4 on T8
SCLK/8 on T8
0 No T8 Counter Time Out
1 T8 Counter Time Out Occured
0 No Effect
1 Reset Flag to 0
0 Modulo-N
1 Single Pass
* Default Setting After Reset
R
R
W
W
0
1
0
1
T8 Disabled *
T8 Enabled
Stop T8
Enable T8
Figure 40. TC8 Control Register
((0D) 0H: Read/Write Accept Where Noted)
DS97LVO0701
2-49
Z86L78
IR/Low-Voltage Microcontroller
Zilog
CTR1 (0D) 1H
D7
D6
D5
D4
D3
D2
D1
D0
Transmit Mode
R/W 0 T16_OUT is 0 Initially
1 T16_OUT is 1 Initially
Demodulation Mode
R
0 No Falling Edge Detection
R
1 Falling Edge Detection
W
W
0 No Effect
1 Reset Flag to 0
Transmit Mode
R/W 0 T8_OUT is 0 Initially
1 T8_OUT is 1 Initially
Demodulation Mode
0 No Rising Edge Detection
R
1 Rising Edge Detection
R
0 No Effect
W
1 Reset Flag to 0
W
Transmit Mode
0 0 Normal Operation
0 1 Ping-Pong Mode
1 0 T16_OUT = 0
1 1 T16_OUT = 1
Demodulation Mode
0 0 No Filter
0 1 4 SCLK Cycle Filter
1 0 8 SCLK Cycle Filter
1 1 16 SCLK Cycle Filter
Transmit Mode/T8/T16 Logic
0 0 AND
0 1 OR
1 0 NOR
1 1 NAND
Demodulation Mode
0 0 Falling Edge Detection
0 1 Rising Edge Detection
1 0 Both Edge Detection
1 1 Reserved
Transmit Mode
0 P36 as Port Output*
1 P36 as T8/T16_OUT
Demodulation Mode
0 P31 as Demodulator Input
1 P20 as Demodulator Input
Transmit/Demodulation Modes
0 Transmit Mode*
1 Demodulation Mode
Note: Care must be taken in differentiating
Transmit Mode from Demodulation Mode.
Depending on which of these two modes is
operating, the CTR1 bit will have different
functions.
*Note: Changing from one mode to
another cannot be
done without disabling the
counter/timers.
Figure 41. T8 and T16 Common Control Functions
((0D) 1H: Read/Write)
2-50
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
CTR2 (0D) 02H
1
D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
P35 is Port Output*
P35 is TC16 Output
Disable T16 Time-Out Interrupt
Enable T16 Time-Out Interrupt
0 Disable T16 Data Capture Interrupt
1 Enable T16 Data Capture Interrupt
00
01
10
11
R
R
W
W
SCLK on T16
SCLK/2 on T16
SCLK/4 on T16
SCLK/8 on T16
0
1
0
1
No T16 Time Out
T16 Time Out Occurs
No Effect
Reset Flag to 0
Transmit Mode
0 Modulo-N for T16
1 Single Pass for T16
Demodulator Mode
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
* Default Setting After Reset
R
R
W
W
0
1
0
1
T16 Disabled *
T16 Enabled
Stop T16
Enable T16
Figure 42. T16 Control Register
((0D) Read/Write Except Where Noted
DS97LVO0701
2-51
Z86L78
IR/Low-Voltage Microcontroller
Zilog
EXPANDED REGISTER FILE CONTROL REGISTERS (0F)
SMR (0F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF **
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
0 11 P32
100 P33
101 P27
11 0 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery**
* Default Setting After Reset
** Default Setting After Reset and Stop-Mode Recovery
Figure 43. Stop-Mode Recovery Register
((F) 0BH: D6-D0 = Write Only, D7=Read Only
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DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
SMR2 (0F) 0DH
1
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR only*
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level
0 Low*
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR,
either of the two specified events will
cause a Stop-Mode Recovery.
*Default Setting After Reset
Figure 44. Stop-Mode Recovery Register 2
((0F) DH: D2-D4, D6 Write Only)
DS97LVO0701
2-53
Z86L78
IR/Low-Voltage Microcontroller
Zilog
EXPANDED REGISTER FILE CONTROL REGISTERS (0F) (Continued)
WDTMR (0F) F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP
00
01 *
10
11
INT RC OSC External Clock
5 ms
256 TpC
10 ms
512 TpC
20 ms
1024 TpC
80 ms
4096 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
* Default Setting After Reset
Figure 45. Watch-Dog Timer Mode Register
((F) 0FH: Write Only)
PCON (FH) 00H
D7 D6 D5
D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
* Default Setting After Reset.
P34 comparator output only.
Figure 46. Port Configuration Register (PCON)
((0F) 0H: Write Only)
2-54
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
Z8 STANDARD CONTROL REGISTER DIAGRAMS
1
R249 IPR
R247 P3M
D7 D6 D5
D7 D6 D5 D4 D3 D2 D1 D0
D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
0 Port 2 Open Drain*
1 Port 2 Push-pull
0 Digital*
1 Analog
Reserved (Must be 0.)
Reserved (Must be 0.)
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
0 P31 = Input (TIN)*
P36 = Output (TOUT)
1 P31 = /DAV2/RDY2
P36 = RDY2//DAV2
** Effects P34 and P35 as well.
* Default setting after Reset.
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
Reserved (Must be 0)
Reserved (Must be 0.)
Reserved (Must be 0)
*Group A only has IRQ3 within it
Figure 47. Port 3 Mode Register
(F7H: Write Only)
R248 P01M
Figure 49. Interrupt Priority Registers
((0) F9H: Write Only)
R250 IRQ
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
D5
D4
D3
D2
D1
D0
P00-P03 Mode
00 Output
01 Input*
1X A11-A8
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16_OUT
IRQ4 = T8_OUT
Reserved (Must be 0.)
Reserved (Must be 0)
Reserved (Must be 0.)
Inter Edge
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
Reserved (Must be 0.)
P07-P04 Mode
00 Output
01 Input*
1X A15-A12
Notes:
Only P00 and P07 are available on Z86L71.
* Default Setting After Reset.
Default Setting After Reset = 0000 0000
Figure 50. Interrupt Request Register
((0) FAH: Read/Write)
Figure 48. Port 0 and 1 Mode Register
(F8H: Write Only)
DS97LVO0701
2-55
Z86L78
IR/Low-Voltage Microcontroller
Zilog
R251 IMR
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ4-IRQ0
(D0 = IRQ0)
P27-P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT*
Reserved (Must be 0)
Reserved (Must be 0)
*Default Setting After Reset
0 Master Interrupt Disable*
1 Master Interrupt Enable
Figure 54. Port 2 Mode Register
(F6H: Write Only)
* Default Setting After Reset
Figure 51. Interrupt Mask Register
((0( FBH: Read/Write)
R254 RP
D7 D6 D5 D4 D3 D2 D1 D0
R252 Flags
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Upper
Byte (SP15-SP8)
User Flag F1
User Flag F2
Figure 55. Stack Pointer High
((0) FEH: Read/Write)
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
R255 SPL
Sign Flag
Zero Flag
D7 D6 D5 D4 D3 D2 D1 D0
Carry Flag
Stack Pointer Lower
Byte (SP7-SP0)
Figure 52. Flag Register
((0) FCH: Read/Write
Figure 56. Stack Pointer Low
((0) FFH: Read/Write)
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register File Pointer
Working Register Pointer
Default Setting After Reset = 00H
Figure 53. Register Pointer
((0) FDH: Read/Write)
2-56
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
PACKAGE INFORMATION
1
Figure 57. 20-Pin DIP Package Diagram
DS97LVO0701
2-57
Z86L78
IR/Low-Voltage Microcontroller
Zilog
Figure 58. 20-Pin SOIC Package Diagram
2-58
DS97LVO0701
Z86L78
IR/Low-Voltage Microcontroller
Zilog
ORDERING INFORMATION
Z86L78
Temperature
8.0 MHz
20-pin DIP
Z86L7808PSC
8 = 8.0 MHz
20-pin SOIC
Z86L7808SSC
1
Environmental
C = Plastic Standard
Codes
Package
P = Plastic DIP
S = SOIC (Small Outline Integrated Circuit)
Example:
Z 86L78 08 P S C
is a Z86L78, 8 MHz, DIP, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
DS97LVO0701
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
2-59