MAXIM Z86L8108PSC

19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage
Infrared Microcontrollers
Product Specification
Maxim Integrated Products Inc.
120 San Gabriel Drive, Sunnyvale CA 94086
Maxim Integrated Products
120 San Gabriel Drive
Sunnyvale, CA 94086
United States
408-737-7600
www.maxim-ic.com
Copyright © 2009 Maxim Integrated Products
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. Maxim retains
the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in
this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to
change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be
assumed by Maxim for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic
devices any license under the patent right of any manufacturer.
Maxim is a registered trademark of Maxim Integrated Products, Inc.
All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their
respective holders.
Z8 is a registered trademark of Zilog, Inc.
Crimzon is a registered trademark of Universal Electronics Inc.
19-4615; REV 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
iii
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Standard Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
23
26
26
27
28
36
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
iv
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
19-4615; Rev 0; 4/09
Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
28-Pin DIP/SOIC/SSOP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . 20
Program Memory Map (64 KB ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register Pointer—Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . . . . . . . 42
Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Ping-Pong Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Port Configuration Register (PCON) (Write Only) . . . . . . . . . . . . . . . . . . . 54
Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Stop-Mode Recovery Register 2 ((0F) DH:D2–D4, D6 Write Only) . . . . . . 59
Watch-Dog Timer Mode Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . 60
Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
v
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
19-4615; Rev 0; 4/09
T8 Control Register ((0D) OH: Read/Write Except Where Noted) . . . . . . . 64
T8 and T16 Common Control Functions ((0D) 1h: Read/Write) . . . . . . . . . 65
T16 Control Register ((0D) 2h: Read/Write Except Where Noted) . . . . . . . 67
Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Stop-Mode Recovery Register ((0F) 0Bh: D6–D0=Write Only, D7=Read Only)
69
Stop-Mode Recovery Register 2 ((0F) 0Dh:D2–D4, D6 Write Only) . . . . . 70
Watch-Dog Timer Register ((0F) 0Fh: Write Only) . . . . . . . . . . . . . . . . . . . 71
Port Configuration Register (PCON) ((0F) 0h: Write Only) . . . . . . . . . . . . . 72
Port 2 Mode Register (F6h: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Port 3 Mode Register (F7h: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Port 0 and 1 Mode Register (F8h: Write Only) . . . . . . . . . . . . . . . . . . . . . . 74
Interrupt Priority Register (F9h: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . 75
Interrupt Request Register (FAh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . 76
Interrupt Mask Register (FBh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 76
Flag Register (FCh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Register Pointer (FDh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Stack Pointer High (FEh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Stack Pointer Low (FFh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
28-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
vi
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
19-4615; Rev 0; 4/09
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
28-Pin DIP, SOIC, and SSOP Pin Identification . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Expanded Register Group D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CTR0 (D)00 Counter/Timer8 Control Register . . . . . . . . . . . . . . . . 30
CTR(D)01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CTR2 (D)02h: Counter/Timer16 Control Register . . . . . . . . . . . . . . 34
SMR2(F)0Dh: Stop-Mode Recovery Register 2 . . . . . . . . . . . . . . . 36
Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 50
IRQ Register* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
WDT Time Select* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Mask Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
1
Features
Table 1 shows the features of the Z86L81/86/98.
Table 1. Features
Device
ROM (KB) RAM* (Bytes) I/O Lines Voltage Range
Z86L81
24
237
23
2.0 V–3.6 V
Z86L86
32
237
23
2.0 V–3.6 V
Z86L98
64
237
23
2.0 V–3.6 V
Note: *General purpose
•
•
Low power consumption–40 mW (typical)
•
Special architecture to automate both generation and reception of complex
pulses or signals:
– One programmable 8-bit counter/timer with two capture registers and two
load registers
– One programmable 16-bit counter/timer with one 16-bit capture register
pair and one 16-bit load register pair
– Programmable input glitch filter for pulse reception
•
Six priority interrupts
– Three external
– Two assigned to counter/timers
– One low-voltage detection interrupt
•
•
•
•
Low-voltage detection with flag
19-4615; Rev 0; 4/09
Three standby modes
– Stop—2 A (typical)
– Halt—0.8 mA (typical)
– Low voltage
Programmable watch-dog/power-on reset circuits
Two independent comparators with programmable interrupt polarity
Mask selectable transistor pull-ups on ports 0, 2, 3
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
2
•
Programmable mask options
– Oscillator selection: RC oscillator or crystal/other clock source
– Oscillator operational mode: normal high-frequency operation enabled or
32-KHz operation enabled
– Port 0: 0–3 pull-ups
– Port 0: 4–7 pull-ups
– Port 2: 0–7 pull-ups
– Port 3: pull-ups
– Port 0: 0–3 mouse mode: normal mode (.5VDD input threshold) versus
mouse mode (.4VDD input threshold)
Note: The mask option pull-up transistor has a typical equivalent
resistance of 200 K±50% at VCC=3 V and 450 K±50% at
VCC=2 V.
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
3
General Description
Based on the Z8 MCU single-chip family of IR microcontrollers, the Z86L81/86/98
features 237 bytes of general-purpose RAM and 24/32/64 KB of ROM. The Maxim
CMOS microcontrollers offer fast executing, efficient use of memory, sophisticated
interrupts, input/output bit manipulation capabilities, automated pulse generation/
reception, and internal key-scan pull-up transistors.
The Z86L81/86/98 architecture is based on the Maxim 8-bit microcontroller core
with an Expanded Register File to allow access to register-mapped peripherals,
input/output (I/O) circuits, and powerful counter/timer circuitry. The Z8 offers a
flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer
peripheral, and battery-operated hand-held applications.
There are three basic address spaces available to support a wide range of configurations: Program Memory, Register File, and Expanded Register File. The register file is composed of 256 bytes of RAM. It includes 3 I/O port registers, 16
control and status registers, and 236 general-purpose registers. Register FEh
(SPH) can be used as a general-purpose register. The Expanded Register File
consists of two additional register groups (F and D).
To unburden the program from coping with such real-time problems as generating
complex waveforms or receiving and demodulating complex waveform/pulses, the
Z86L81/86/98 offers a new intelligent counter/timer architecture with 8-bit and
16-bit counter/timers (see Figure 1, Figure 2, Figure 3, and Table 3). Also included
are a large number of user-selectable modes, and two on-board comparators to
process analog signals with separate reference voltages (Figure 9 on page 20).
Power connections use the conventional descriptions listed in Table 2.
Table 2. Power Connections
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
4
HI16
LO16
8
8
16-Bit
T16
1 2 4 8
Timer 16
16
8
8
SCLK
Clock
Divider
TC16H
TC16L
And/Or
Logic
HI8
LO8
8
8
Input
Edge
Detect
Circuit
Glitch
Filter
8-Bit
T8
8
TC8H
Figure 1. Counter/Timers Diagram
19-4615; Rev 0; 4/09
Timer 8/16
Timer 8
8
TC8L
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
5
P00
P01
P02
P03
P04
P05
P06
P07
Register File
256 x 8-Bit
4
Port 0
4
Internal
Address
Bus
I/O Nibble Programmable
P20
P21
P22
P24
P25
P26
P27
Port 3
Port 2
ROM
24/32/64K x 8
Z8 Core
Internal
Address Bus
Expanded
Register File
Expanded
Register Bus
XTAL
Machine
Timing and
Instruction
Control
Power
I/O Bit Programmable
Counter/Timer 8
8-Bit
Figure 2. Functional Block Diagram
19-4615; Rev 0; 4/09
Pref1
P31
P32
P33
P34
P35
P36
P37
Counter/Timer 16
16-Bit
VDD
VSS
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
6
Pin Description
The pins are shown in Figure 3 and described in Table 3.
P25
P26
P27
P04
P05
P06
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P34
1
28
Z86L81/86/98
DIP/SOIC/
SSOP
14
15
P24
P23
P22
P21
P20
P03
VSS
P02
P01
P00
Pref1
P36
P37
P35
Figure 3. 28-Pin DIP/SOIC/SSOP Pin Assignment
Table 3. 28-Pin DIP, SOIC, and SSOP Pin Identification
28-Pin DIP, SOIC, and SSOP
Standard Mode Direction
Description
19
P00
Input/Output
Port 0 is Nibble Programmable
20
P01
Input/Output
Port 0-3 can be configured as a
21
P02
Input/Output
mouse/trackball input
23
P03
Input/Output
4
P04
Input/Output
5
P05
Input/Output
6
P06
Input/Output
7
P07
Input/Output
24
P20
Input/Output
Port 2 pins are individually
25
P21
Input/Output
configurable as input or output.
26
P22
Input/Output
27
P23
Input/Output
28
P24
Input/Output
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
7
Table 3. 28-Pin DIP, SOIC, and SSOP Pin Identification (Continued)
28-Pin DIP, SOIC, and SSOP
Standard Mode Direction
1
P25
Input/Output
2
P26
Input/Output
3
P27
Input/Output
18
Pref1
Input
Analog Ref Input
11
P31
Input
IRQ2/Modulator input
12
P32
Input
IRQ0
13
P33
Input
IRQ1
14
P34
Output
T8 output
15
P35
Output
T16 output
17
P36
Output
T8/T16 output
16
P37
Output
10
XTAL1
Input
Crystal, Oscillator Clock
9
XTAL2
Output
Crystal, Oscillator Clock
8
VDD
Power Supply
22
VSS
Ground
19-4615; Rev 0; 4/09
Description
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
8
Absolute Maximum Ratings
Stresses greater than those listed in Table 4 might cause permanent damage to
the device. This rating is a stress rating only. Functional operation of the device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an
extended period might affect device reliability.
Table 4. Absolute Maximum Ratings
Symbol
Description
VCC
Supply Voltage (*)
–0.3
+7.0
V
TSTG
Storage Temperature
–65°
+150°
C
TA
Oper. Ambient Temperature.
†
C
Notes:
*Voltage on all pins with respect to GND.
†
See Ordering Information on page 82.
19-4615; Rev 0; 4/09
Min
Max
Units
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
9
Standard Test Conditions
The characteristics listed in this product specification apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into
the referenced pin (see Figure 4).
From Output
Under Test
I
Figure 4. Test Load Diagram
Capacitance
The capacitances are listed in Table 5.
Table 5. Capacitance
Parameter
Max
Input capacitance
12 pF
Output capacitance
12 pF
I/O capacitance
12 pF
Note: TA = 25 °C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured
pins returned to GND
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
10
DC Characteristics
Table 6 lists the DC characteristics.
Table 6. DC Characteristics
TA = 0°C to +70°C
Sym
VCH
VCL
VIH
VIL
VOH1
VOH2
VOL1
VOL2*
VOL2
Parameter
VCC
Max Input Voltage
2.0 V
7
V
IIN <250 A
3.6 V
7
V
IIN <250 A
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
Driven by External
Clock Generator
Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
(P36, P37,P00, P01)
Output Low Voltage
Max
Units Conditions
2.0 V
0.8 VCC
VCC+0.3
V
3.6 V
0.8 VCC
VCC+0.3
V
2.0 V
VSS–0.3
0.2 VCC
V
3.6 V
VSS–0.3
0.2 VCC
V
2.0 V
0.7 VCC
VCC+0.3
V
3.6 V
0.7 VCC
VCC+0.3
V
2.0 V
VSS–0.3
0.2 VCC
V
3.6 V
VSS–0.3
0.2 VCC
V
2.0 V
VCC–0.4
V
IOH = –0.5 mA
3.6 V
VCC–0.4
V
IOH = –0.5 mA
2.0 V
VCC–0.8
V
IOH = –7 mA
3.6 V
VCC–0.8
V
IOH = –7 mA
2.0 V
0.4
V
IOL = 1.0 mA
3.6 V
0.4
V
IOL = 4.0 mA
2.0 V
0.8
V
IOL = 5.0 mA
3.6 V
0.8
V
IOL = 7.0 mA
Output Low Voltage (P00, 2.0 V
P01, P36,P37)
3.6 V
0.8
V
IOL = 10 mA
0.8
V
IOL = 10 mA
25
mV
Output Low Voltage
VOFFSET Comparator Input Offset
Voltage
IIL
Min
Input Leakage
19-4615; Rev 0; 4/09
2.0 V
3.6 V
2.0 V
–1
25
1
mV
A
VIN = 0 V, VCC
3.6 V
–1
1
A
VIN = 0 V, VCC
Notes
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
11
Table 6. DC Characteristics (Continued)
TA = 0°C to +70°C
Sym
Parameter
VCC
Min
Max
IOL
Output Leakage
2.0 V
–1
1
3.6 V
–1
ICC
ICC1
ICC2
TPOR
VBO
VLVD
Supply Current
Standby Current (HALT
Mode)
Standby Current (STOP
Mode)
Power-On Reset
VCC Low Voltage
Protection (Reset)
Vcc Low Voltage
Detection
Units Conditions
Notes
VIN = 0 V, VCC
1
A
A
2.0 V
10
mA
at 8.0 MHz
1, 2
3.6 V
2.0 V
15
250
mA
A
at 8.0 MHz
at 32 kHz
1, 2
1, 2, 3
3.6 V
850
A
at 32 kHz
1, 2, 3
2.0 V
3
mA
3.6 V
2.0 V
5
2
mA
mA
3.6 V
2.0 V
4
8
mA
A
3.6 V
10
2.0 V
500
A
A
VIN = 0 V, VCC at
1, 2
8.0 MHz
Same as above
1, 2
Clock Divide-by-16 1, 2
at 8.0 MHz
Same as above
1, 2
4, 5, 8
VIN = 0 V, VCC
WDT is not
Running
Same as above
4, 5, 8
3.6 V
800
A
2.0 V
12
75
ms
3.6 V
5
20
2.0
ms
V
2.55
V
VIN = 0 V, VCC
VIN = 0 V, VCC
WDT is Running
Same as above
8 MHz max
Ext. CLK Freq.
4, 5, 8
4, 5, 8
7
Notes:
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. 32-kHz clock driver input.
4. Same as note 1, except inputs at VCC.
5. Oscillator stopped.
6. Not applicable
7. The VBO is measured at room temperature and typically is 1.6 V. VBO increases as the temperature decreases.
8. WDT, Comparators, Low Voltage Detection, and ADC (if applicable) are disabled. The IC might draw more current if any of the about peripherals is enabled.
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
12
Additional Timing
Figure 5 and Table 7 describe additional timing characteristics.
1
3
Clock
2
7
2
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
Figure 5. Additional Timing
19-4615; Rev 0; 4/09
10
3
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
13
Table 7. Additional Timing
TA = 0°C to +70°C
8.0 MHz
Stop-Mode
Recovery
Units Notes (D1, D0)
No Sym
Parameter
VCC
Min
Max
1
TpC
Input Clock Period
121
121
2
TrC,TfC
Clock Input Rise and
Fall Times
DC
DC
25
25
3
TwC
Input Clock Width
4
TwTinL
Timer Input
Low Width
ns
ns
ns
ns
ns
ns
ns
ns
5
TwTinH
Timer Input High
Width
6
TpTin
Timer Input Period
7
TrTin,TfTin Timer Input Rise and
Fall Timers
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
100
100
ns
ns
ns
ns
8A TwIL
Interrupt Request
Low Time
8B TwIL
Interrupt Request
Low Time
9
Interrupt Request
Input High Time
TwIH
10 Twsm
11 Tost
Stop-Mode
Recovery Width
Spec
Oscillator
Start-Up Time
19-4615; Rev 0; 4/09
2.0 V
3.6 V
37
37
100
70
3TpC
3TpC
8TpC
8TpC
100
70
5TpC
5TpC
5TpC
5TpC
12
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1,2
1,3
1,3
1,2
1,2
ns
ns
5TpC
5TpC
4
4
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
14
Table 7. Additional Timing (Continued)
TA = 0°C to +70°C
8.0 MHz
No Sym
Parameter
VCC
Min
12 Twdt
Watch-Dog Timer Delay Time
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
2.0 V
3.6 V
12
5
25
10
50
20
200
80
Notes:
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33–P31).
3. Interrupt request through Port 3 (P30).
4. SMR – D5 = 0.
5. For internal RC oscillator.
19-4615; Rev 0; 4/09
Max
Stop-Mode
Recovery
Units Notes (D1, D0)
ms
ms
ms
ms
ms
ms
ms
ms
5
5
5
5
5
5
5
5
0, 0
0, 1
1, 0
1, 1
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
15
Pin Functions
Standard Mode
XTAL1 Crystal 1 (Time-Based Input)
This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network to the on-chip oscillator input. An external single-phase clock to the on-chip
oscillator input is also an option.
XTAL2 Crystal 2 (Time-Based Output)
This pin connects a parallel-resonant crystal, ceramic resonant, LC, or RC network to the on-chip oscillator output.
Port 0 (P07–P00)
Port 0 is an 8-bit, bidirectional, CMOS-compatible port (see Figure 6). These eight
I/O lines are configured under software control as a nibble I/O port. The output
drivers are push-pull or open drain controlled by bit D2 in the PCON register. If
one or both nibbles are required for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an
input port.
A mask option is available to program 0.4 VDD CMOS trip inputs on P00–P03.
This option allows direct interface to mouse/trackball IR sensors.
An optional pull-up transistor is available as a mask option on all Port 0 bits with
nibble select.
Note: Internal pull-ups are disabled on any given pin or group of port
pins when programmed into output mode.
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
16
4
Z89L98
MCU
Port 0 (I/O)
4
Mask VCC
Option
Open-Drain
Resistive
transistor
pull-up
I/O
Pad
Out
In
In
0.4 VDD
Trip Point Buffer
*Mask Selectable
(P00 to P03 only)
Figure 6. Port 0 Configuration
Port 2 (P27–P20)
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 7). These
eight I/O lines can be independently configured under software control as inputs
or outputs. Port 2 is always available for I/O operation. A mask option is available
to connect eight pull-up transistors on this port. Bits programmed as outputs are
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
17
globally programmed as either push-pull or open-drain. The POR resets with the
eight bits of Port 2 configured as inputs.
Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up
the part. P20 can be programmed to access the edge-detection circuitry in
demodulation mode.
Z89L98
MCU
Open-Drain
Port 2 (I/O)
Mask VCC
Option
Resistive
transistor
pull-up
I/O
Pad
Out
In
Figure 7. Port 2 Configuration
Port 3 (P37–P31)
Port 3 is a 7-bit, CMOS-compatible fixed I/O port (see Figure 8). Port 3 consists of
three fixed input (P33–P31) and four fixed output (P37–P34), and each can be
configured under software control for interrupt and output from the counter/timers.
P31, P32, and P33 are standard CMOS inputs; P34, P35, P36 and P37 are pushpull outputs.
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
18
Pref1
P31
P32
Z89L98
MCU
P33
P34
P35
Port 3 (I/O)
P36
P37
R247 = P3M
D1
Dig.
P31 (AN1)
Pref
Comp1
+
-
P32 (AN2)
P33 (REF2)
1 = Analog
0 = Digital
+
Comp2
IRQ2, P31 Data Latch
An.
IRQ0, P32 Data Latch
-
From Stop-Mode Recovery Source of SMR
IRQ1, P33 Data Latch
Figure 8. Port 3 Configuration
Two on-board comparators process analog signals on P31 and P32, with reference to the voltage on Pref1 and P33. The analog function is enabled by programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising,
falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33
are the comparator reference voltage inputs. Access to the Counter Timer edgedetection circuit is through P31 or P20 (see “CTR1 Register Description” on
page 32). Other edge detect and IRQ modes are described in Table 8.
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
19
Table 8. Pin Assignments
Pin
I/O
C/T
Pref1
Comp.
Int.
RF1
P31
IN
P32
IN
AN1
IRQ2
IN
AN2
IRQ0
P33
IN
RF2
IRQ1
P34
OUT
T8
P35
OUT
T16
P36
OUT
T8/16
P37
OUT
P20
I/O
AO1
AO2
IN
Port 3 also provides output for each of the counter/timers and the AND/OR Logic
(see Figure 9). Control is performed by programming bits D5-D4 of CTR1, bit 0 of
CTR0 and bit 0 of CTR2.
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
20
CTR0, D0
P34 data
T8_Out
PCON, D0
MU
VDD
MUX
Pad
P34
P31
Pref1
+
-
Comp1
CTR2, D0
Out 35
T16_Out
VDD
MUX
Pad
P35
CTR1, D6
Out 36
T8/T16_Out
VDD
MUX
Pad
P36
PCON, D0
P37 data
VDD
MUX
Pad
P37
P32
Pref2
+
-
Comp2
Figure 9. Port 3 Counter/Timer Output Configuration
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
21
Comparator Inputs
In analog mode, P31 and P32 have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its
corresponding IRQ1 is diverted to the SMR sources (excluding P31, P32, and
P33) as indicated in Figure 8 on page 18. In digital mode, P33 is used as D3 of
the Port 3 input register, which then generates IRQ1.
Note: Comparators are powered down by entering Stop Mode. For
P31–P33 to be used in a Stop-Mode Recovery source, these
inputs must be placed into digital mode.
Comparator Outputs
These outputs can be programmed to be output on P34 and P37 through the
PCON register.
Functional Description
The Z86L81/86/98 incorporates special functions to enhance the Z8’s functionality
in consumer and battery-operated applications.
Program Memory
The Z86L81/86/98 family addresses 24/32/64 KB of internal program memory.
The first twelve bytes are reserved for interrupt vectors. These locations contain
the five 16-bit vectors, which correspond to the five available interrupts.
RAM
The Z86L81/86/98 device has 237 bytes of RAM, which make up the register file.
See Figure 10.
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
22
65535
Location of
first byte of
instruction
executed
after RESET
On-Chip
ROM
12
Reset Start Address
11
IRQ5
10
IRQ5
9
IRQ4
8
IRQ4
7
IRQ3
6
IRQ3
5
IRQ2
4
Interrupt Vector
(Upper Byte) 3
IRQ2
2
IRQ1
1
IRQ0
0
IRQ0
Interrupt Vector
(Lower Byte)
IRQ1
Figure 10. Program Memory Map (64 KB ROM)
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
23
Expanded Register File
The register file has been expanded to allow for additional system control registers, and for mapping of additional peripheral devices into the register address
area. The Z8 register address space R0 through R15 has been implemented as
16 banks, with 16 registers per bank. These register groups are known as the
ERF (Expanded Register File). Bits 7–4 of register RP select the working register
group. Bits 3–0 of register RP select the expanded register file bank.
Note: An expanded register bank is also referred to as an expanded
register group (see Figure 11).
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
24
Z8® Standard Control Registers
Register* *
Register Pointer
7
6
5
4
3
2
1
Working Register
Group Pointer
0
Expanded Register
Bank Pointer
*
Z8 Register File (Bank 0) * *
FF
F0
Reset Condition
D7 D6 D5 D4 D3 D2 D1 D0
FF
SPL
U
U
U
U
U
U
U
U
FE
SPH
U
U
U
U
U
U
U
U
FD
RP
0
0
0
0
0
0
0
0
FC
FLAGS
U
U
U
U
U
U
U
U
FB
IMR
0
U
U
U
U
U
U
U
FA
IRQ
0
0
0
0
0
0
0
0
F9
IPR
U
U
U
U
U
U
U
U
F8
P01M
0
1
0
0
1
1
0
1
F7
P3M
0
0
0
0
0
0
0
1
F6
P2M
1
1
1
1
1
1
1
1
F5
Reserved
U
U
U
U
U
U
U
U
F4
Reserved
U
U
U
U
U
U
U
U
F3
Reserved
U
U
U
U
U
U
U
U
F2
Reserved
U
U
U
U
U
U
U
U
F1
Reserved
0
0
0
0
0
0
0
0
F0
Reserved
0
U
U
0
0
0
0
0
Expanded Reg. Bank/Group (F)
Register* *
Reset Condition
*
(F) 0F WDTMR
0
0
0
0
1
1
0
1
U
0
U
0
0
0
U
U
0
0
1
0
0
0
U
0
1
1
1
1
1
1
1
0
(F) 0E Reserved
(F) 0D SMR2
(F) 0C Reserved

7F
(F) 0B SMR
(F) 0A Reserved
Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
Reserved
(F) 04 Reserved
0F
00
(F) 03 Reserved
(F) 02 Reserved
(F) 01 Reserved
*
(F) 00 PCON
Expanded Reg. Bank/Group (D)
Register* *
Reset Condition
Expanded Reg. Bank/Group (0)
Register* *
Reset
*
*
(0) 03 P3
0
0
0
0
U
U
U
U
(0) 02 P2
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
(0) 01 P1
(0) 00 P0
U
U
U
U
U
U
U
U
U = Unknown
* Is not reset with a Stop-Mode Recovery
** All addresses are in hexadecimal
 Is not reset with a Stop-Mode Recovery,
except Bit 0
Figure 11. Expanded Register File Architecture
19-4615; Rev 0; 4/09
(D) 0C
LVD
0
0
0
0
0
0
0
0
(D) 0B
HI8
U
U
U
U
U
U
U
U
(D) 0A
LO8
U
U
U
U
U
U
U
U
(D) 09
HI16
U
U
U
U
U
U
U
U
(D) 08
LO16
U
U
U
U
U
U
U
U
(D) 07
TC16H
U
U
U
U
U
U
U
U
(D) 06
TC16L
U
U
U
U
U
U
U
U
(D) 05
TC8H
U
U
U
U
U
U
U
U
(D) 04
TC8L
U
U
U
U
U
U
U
U
(D) 03
Reserved
(D) 02
CTR2
0
U
U
U
U
U
U
0
(D) 01
CTR1
0
0
U
U
U
U
U
U
(D) 00
CTR0
0
U
U
U
U
U
U
0
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
25
The upper nibble of the register pointer (see Figure 12) selects which working register group, of 16 bytes in the register file, is accessed out of the possible 256. The
lower nibble selects the expanded register file bank and, in the case of the
Z86L81/86/98 family, banks 0, F, and D are implemented. A 0h in the lower nibble
allows the normal register file (bank 0) to be addressed, but any other value from
1h to Fh exchanges the lower 16 registers to an expanded register bank.
R253 RP
D7
D6
D5
D4
D3
D2
D1
D0
Expanded Register
File Pointer
Default Setting After Reset = 0000 0000
Working Register
Pointer
Figure 12. Register Pointer
Example: Z86L81/86/98: (See Figure 11 on page 24)
R253 RP = 00h
R0 = Port 0
R1 = Port 1
R2 = Port 2
R3 = Port 3
But if:
R253 RP = 0Dh
R0 = CTRL0
R1 = CTRL1
R2 = CTRL2
R3 = Reserved
The counter/timers are mapped into ERF group D. Access is easily performed
using the following:
LD
RP, #0Dh
(working register
LD
R0,#xx
LD
1, #xx
LD
R1, 2
19-4615; Rev 0; 4/09
; Select ERF D for access to bank D
group 0)
; load CTRL0
; load CTRL1
; CTRL2CTRL1
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
26
LD
RP, #0Dh
; Select ERF D for access to bank D
(working register group 0)
LD
RP, #7Dh
; Select expanded register bank D and working
register group 7 of bank 0 for access.
LD
71h, 2
; CTRL2register 71h
LD
R1, 2
; CTRL2register 71h
Register File
The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose registers, and 16 control and status registers (R0–R3, R4–R239, and R240–R255,
respectively). Additionally, there are two expanded registers groups in Banks D
(see Table 9) and F. Instructions can access registers directly or indirectly through
an 8-bit address field, thereby allowing a short, 4-bit register address to use the
Register Pointer (Figure 13). In the 4-bit mode, the register file is divided into 16
working register groups, each occupying 16 continuous locations. The Register
Pointer addresses the starting location of the active working register group.
Counter/Timer Register Description
Table 9. Expanded Register Group D
(D)0Ch
LVD
(D)0Bh
HI8
(D)0Ah
LO8
(D)09h
HI16
(D)08h
LO16
(D)07h
TC16H
(D)06h
TC16L
(D)05h
TC8H
(D)04h
TC8L
(D)03h
Reserved
(D)02h
CTR2
(D)01h
CTR1
(D)00h
CTR0
19-4615; Rev 0; 4/09
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
27
r7 r6 r5 r4 r3 r2 r1 r0 R253
The upper nibble of the register file address
provided by the register pointer specifies the
active working-register group.
{
{
{
{
{
{
{
{
7F
70
6F
60
5F
50
4F
40
3F
30
2F
20
1F
10
0F
00
Specified Working
Register Group
The lower nibble of the
register file address provided
by the instruction points to
the specified register.
Register Group 1
R15 to R0
Register Group 0
I/O Ports
R15 to R4 *
R3 to R0 *
* RP = 00: Selects Register Group 0, Working Register 0
Figure 13. Register Pointer—Detail
Note: Working register group E0–EF can only be accessed through
working registers and indirect addressing modes.
Stack
The Z86L81/86/98 internal register file is used for the stack. An 8-bit Stack Pointer
(R255) is used for the internal stack that resides in the general-purpose registers
(R4–R239). SPH is used as a general-purpose register only when using internal
stacks.
Note: When SPH is used as a general-purpose register, and Port 0 is
in address mode, the contents of SPH are loaded into Port 0
whenever the internal stack is accessed.
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28
Register Description
LVD (D) 0Ch. Low-Voltage Detection Register
Bit 0 enables/disables the Low-Voltage Detection Circuit. Bit 1 flags if low voltage
is detected. Interrupt 5 is triggered when the flag bit is set, given that IRQ5 is not
masked.
Note: The LVD flag will be valid after enabling the detection for 20 S (design
estimation, not tested in production). LVD does not work at STOP mode. It
must be disabled during STOP mode in order to reduce current.
Field
Bit Position
Description
LVD
765432--
Reserved
No Effect
------1-
R
1
0*
LV flag set
LV flag reset
-------0
R/W
1
0*
Enable LVD
Disable LVD
Note:
*Default after POR
HI8(D)0Bh
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register is used to hold the number of counts when the input signal
is 1.
Field
Bit Position
T8_Capture_HI
76543210
Description
R
W
Captured Data
No Effect
L08(D)0Ah
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register is used to hold the number of counts when the input signal
is 0.
Field
Bit Position
T8_Capture_L0
76543210
19-4615; Rev 0; 4/09
Description
R
W
Captured Data
No Effect
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28-Pin Low-Voltage Infrared Microcontrollers
29
HI16(D)09h
This register holds the captured data from the output of the 16-bit Counter/
Timer16, while also holding the MS-Byte of the data.
Field
Bit Position
T16_Capture_HI 76543210
Description
R
W
Captured Data
No Effect
L016(D)08h
This register holds the captured data from the output of the 16-bit Counter/
Timer16, while also holding the LS-Byte of the data.
Field
Bit Position
T16_Capture_LO 76543210
Description
R
W
Captured Data
No Effect
TC16H(D)07h
Counter/Timer2 MS-Byte Hold Register.
Field
Bit Position
T16_Data_HI
76543210
Description
R/W Data
TC16L(D)06h
Counter/Timer2 LS-Byte Hold Register.
Field
Bit Position
T16_Data_LO
76543210
Description
R/W Data
TC8H(D)05h
Counter/Timer8 High Hold Register.
Field
Bit Position
T8_Level_HI
76543210
19-4615; Rev 0; 4/09
Description
R/W Data
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28-Pin Low-Voltage Infrared Microcontrollers
30
TC8L(D)04h
Counter/Timer8 Low Hold Register.
Field
Bit Position
T8_Level_LO
76543210
Description
R/W Data
CTR0 Counter/Timer8 Control Register
Table 10 lists and briefly describes the fields for this register.
Table 10. CTR0 (D)00 Counter/Timer8 Control Register
Field
Bit Position
T8_Enable
7-------
Value
R
W
Description
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Single/Modulo-N
-6-------
R/W
0
1
Modulo-N
Single Pass
Time_Out
--5------
R
0
1
0
1
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
W
SCLK
SCLK/2
SCLK/4
SCLK/8
T8 _Clock
---43---
R/W
00
01
10
11
Capture_INT_MASK
-----2--
R/W
0
1
Disable Data Capture Int.
Enable Data Capture Int.
Counter_INT_Mask
------1-
R/W
0
1
Disable Time-Out Int.
Enable Time-Out Int.
P34_Out
-------0
R/W
0*
1
P34 as Port Output
T8 Output on P34
Note:
*Indicates the value upon Power-On Reset.
T8 Enable
This field enables T8 when set (written) to 1.
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31
Single/Modulo-N
When set to 0 (modulo-N), the counter reloads the initial value when the terminal
count is reached. When set to 1 (single pass), the counter stops when the terminal
count is reached.
Timeout
This bit is set when T8 times out (terminal count reached). To reset this bit, a 1
should be written to its location.
Caution:
Writing a 1 is the only way to reset the Terminal Count
status condition. Therefore, reset this bit before using/
enabling the counter/timers.
The first clock of T8 might not feature complete clock width
and can occur any time when enabled.
Note: Care must be taken when using the OR or AND commands to
manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation
Mode). These instructions use a Read-Modify-Write sequence
in which the current status from the CTR0 and CTR1 registers
is ORed or ANDed with the designated value and then written
back into the registers.
Example
When the status of bit 5 is 1, a timer reset condition occurs.
T8 Clock
This bit defines the frequency of the input signal to T8.
Capture_INT_Mask
Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon
a positive or negative edge detection in demodulation mode.
Counter_INT_Mask
Set this bit to allow an interrupt when T8 has a timeout.
P34_Out
This bit defines whether P34 is used as a normal output pin or the T8 output.
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32
CTR1(D)01h
This register controls the functions in common with the T8 and T16.
CTR1 Register Description
Table 11 lists and briefly describes the fields for this register.
Table 11. CTR(D)01h Register Descriptions
Field
Mode
Bit Position
7-------
R/W
P36_Out/
Demodulator_Input
-6------
R/W
Value
0*
0*
1
0
1
T8/T16_Logic/
Edge _Detect
--54----
R/W
00
01
10
11
00
01
10
11
Transmit_Submode/
Glitch_Filter
----32--
R/W
00
01
10
11
00
01
10
11
Initial_T8_Out/
Rising Edge
------1R/W
0
1
R
0
1
0
1
W
19-4615; Rev 0; 4/09
Description
Transmit Mode
Demodulation Mode
Transmit Mode
Port Output
T8/T16 Output
Demodulation Mode
P31
P20
Transmit Mode
AND
OR
NOR
NAND
Demodulation Mode
Falling Edge
Rising Edge
Both Edges
Reserved
Transmit Mode
Normal Operation
Ping-Pong Mode
T16_Out = 0
T16_Out = 1
Demodulation Mode
No Filter
4 SCLK Cycle
8 SCLK Cycle
Reserved
Transmit Mode
T8_OUT is 0 Initially
T8_OUT is 1 Initially
Demodulation Mode
No Rising Edge
Rising Edge Detected
No Effect
Reset Flag to 0
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33
Table 11. CTR(D)01h Register Descriptions (Continued)
Field
Initial_T16_Out/
Falling_Edge
Bit Position
-------0
Value
R/W
0
1
R
0
1
0
1
W
Description
Transmit Mode
T16_OUT is 0 Initially
T16_OUT is 1 Initially
Demodulation Mode
No Falling Edge
Falling Edge Detected
No Effect
Reset Flag to 0
Note:
*Default upon Power-On Reset
Mode
If it is 0, the counter/timers are in the transmit mode; otherwise, they are in the
demodulation mode.
P36_Out/Demodulator_Input
In Transmit Mode, this bit defines whether P36 is used as a normal output pin or
the combined output of T8 and T16.
In Demodulation Mode, this bit defines whether the input signal to the Counter/
Timers is from P20 or P31.
T8/T16_Logic/Edge _Detect
In Transmit Mode, this field defines how the outputs of T8 and T16 are combined
(AND, OR, NOR, NAND).
In Demodulation Mode, this field defines which edge should be detected by the
edge detector.
Transmit_Submode/Glitch Filter
In Transmit Mode, this field defines whether T8 and T16 are in the Ping-Pong
mode or in independent normal operation mode. Setting this field to “Normal
Operation Mode” terminates the “Ping-Pong Mode” operation. When set to 10,
T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1.
In Demodulation Mode, this field defines the width of the glitch that must be filtered out.
Initial_T8_Out/Rising_Edge
In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the
output of T8 is set to 1 when it starts to count. When the counter is not enabled
and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This
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34
measure ensures that when the clock is enabled, a transition occurs to the initial
state set by CTR1, D1.
In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the
input signal. In order to reset it, a 1 should be written to this location.
Initial_T16 Out/Falling _Edge
In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it
is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in
Normal or Ping-Pong Mode (CTR1, D3, D2). When the counter is not enabled and
this bit is set, T16_OUT is set to the opposite state of this bit. This measure
ensures that when the clock is enabled, a transition occurs to the initial state set
by CTR1, D0.
In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the
input signal. In order to reset it, a 1 should be written to this location.
Note: Modifying CTR1, (D1 or D0) while the counters are enabled
causes unpredictable output from T8/16_OUT.
CTR2 Counter/Timer 16 Control Register
Table 12 lists and briefly describes the fields for this register.
Table 12. CTR2 (D)02h: Counter/Timer16 Control Register
Field
Bit Position
T16_Enable
7-------
R
W
Single/Modulo-N
-6------
Value
Description
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
R/W
0
1
0
1
Time_Out
--5-----
R
W
19-4615; Rev 0; 4/09
0
1
0
1
Transmit Mode
Modulo-N
Single Pass
Demodulation Mode
T16 Recognizes Edge
T16 Does Not
Recognize Edge
No Counter Timeout
Counter Timeout
Occurred
No Effect
Reset Flag to 0
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35
Table 12. CTR2 (D)02h: Counter/Timer16 Control Register (Continued)
Field
Bit Position
Value
Description
T16 _Clock
---43---
R/W
00
01
10
11
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask
-----2--
R/W
0
1
Disable Data Capture
Int.
Enable Data Capture
Int.
Counter_INT_Mask
------1-
R/W
0
Disable Timeout Int.
Enable Timeout Int.
P35_Out
-------0
R/W
0*
1
P35 as Port Output
T16 Output on P35
Note:
*Indicates the value upon Power-On Reset.
T16_Enable
This field enables T16 when set to 1.
Single/Modulo-N
In Transmit Mode, when set to 0, the counter reloads the initial value when terminal count is reached. When set to 1, the counter stops when the terminal count is
reached.
In Demodulation Mode, when set to 0, T16 captures and reloads on detection of
all the edges. When set to 1, T16 captures and detects on the first edge, but
ignores the subsequent edges. For details, see the description of T16 Demodulation Mode on page 45.
Time_Out
This bit is set when T16 times out (terminal count reached). To reset the bit, write
a 1 to this location.
T16_Clock
This bit defines the frequency of the input signal to Counter/Timer16.
Capture_INT_Mask
This bit is set to allow an interrupt when data is captured into LO16 and HI16.
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36
Counter_INT_Mask
This bit is set to allow an interrupt when T16 times out.
P35_Out
This bit defines whether P35 is used as a normal output pin or T16 output.
SMR2 Stop-Mode Recovery Register 2
Table 13 lists and briefly describes the fields for this register.
Table 13. SMR2(F)0Dh: Stop-Mode Recovery Register 2
Field
Reserved
Recovery Level
Bit Position
7-------6------
W
Reserved
Source
--5-------432--
W
Reserved
------10
Value
0
0*
1
0
000*
001
010
011
100
101
110
111
00
Description
Reserved (Must be 0)
Low
High
Reserved (Must be 0)
A. POR Only
B. NAND of P23–P20
C. NAND of P27–P20
D. NOR of P33–P31
E. NAND of P33–P31
F. NOR of P33-P31, P00, P07
G. NAND of P33-P31, P00, P07
H. NAND of P33-P31, P22–P20
Reserved (Must be 0)
Notes:
* Indicates the value upon Power-On Reset
Counter/Timer Functional Blocks
Input Circuit
The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5–
D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is
detected. Glitches in the input signal that have a width less than specified (CTR1
D3, D2) are filtered out (see Figure 14).
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37
CTR1 D5,D4
Pos Edge
P31
MUX
Glitch Filter
Edge Detector
Neg Edge
P20
CTR1 D6
CTR1 D3,D2
Figure 14. Glitch Filter Circuitry
T8 Transmit Mode
Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is
1; if it is 1, T8_OUT is 0. See Figure 15.
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T8 (8-Bit)
Transmit Mode
No
T8_Enable Bit Set
CTR0, D7
Yes
Reset T8_Enable Bit
0
CTR1, D1
Value
Load TC8H
Set T8_OUT
Load TC8L
Reset T8_OUT
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
1
Enable T8
No
T8_Timeout
Yes
Single Pass
Single
Pass?
Modulo-N
1
T8_OUT Value
Load TC8L
Reset T8_OUT
Load TC8H
Set T8_OUT
Enable T8
No
T8_Timeout
Yes
Figure 15. Transmit Mode Flowchart
19-4615; Rev 0; 4/09
0
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
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28-Pin Low-Voltage Infrared Microcontrollers
39
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1).
If the initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into
the counter. In Single-Pass Mode (CTR0, D6), T8 counts down to 0 and stops,
T8_OUT toggles, the timeout status bit (CTR0, D5) is set, and a timeout interrupt
can be generated if it is enabled (CTR0, D1). In Modulo-N Mode, upon reaching
terminal count, T8_OUT is toggled, but no interrupt is generated. From that point,
T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1,
TC8H is loaded. T8 counts down to 0, toggles T8_OUT, sets the timeout status bit
(CTR0, D5) and generates an interrupt if enabled (CTR0, D1). One cycle is thus
completed. T8 then loads from TC8H or TC8L according to the T8_OUT level, and
repeats the cycle. See Figure 16.
CTR0 D2
Z8 Data Bus
Positive Edge
IRQ4
Negative Edge
HI8
LO8
CTR0 D1
CTR0 D4, D3
SCLK
Clock
Clock
Select
TC8H
8-Bit
Counter T8
T8_OUT
TC8L
Z8 Data Bus
Figure 16. 8-Bit Counter/Timer Circuits
You can modify the values in TC8H or TC8L at any time. The new values take
effect when they are loaded.
Caution:
19-4615; Rev 0; 4/09
Do not write these registers at the time the values are to be
loaded into the counter/timer to ensure known operation. An
Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
40
initial count of “1” is not allowed (a non-function occurs). An
initial count of “0” causes TC8 to count from 0 to FFh to FEh.
Note: The letter h is used for hexadecimal values.
Transition from 0 to FFh is not a timeout condition.
Caution:
Using the same instructions for stopping the counter/timers
and setting the status bits is not recommended.
Two successive commands are necessary. First, the counter/timers must be
stopped. Second, the status bits must be reset. These commands are required
because it takes one counter/timer clock interval for the initiated event to actually
occur. See Figure 17 and Figure 18.
TC8H
Count
Counter Enable
Command; T8_OUT
Switches to Its Initial
Value (CTR1 D1)
T8_OUT Toggles;
Timeout Interrupt
Figure 17. T8_OUT in Single-Pass Mode
T8_OUT
T8_OUT
TC8L
Counter Enable
Command; T8_OUT
Switches to Its
Initial Value (CTR1 D1)
TC8H
TC8L
Timeout
Interrupt
Figure 18. T8_OUT in Modulo-N Mode
19-4615; Rev 0; 4/09
TC8H
TC8L
Timeout
Interrupt
...
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41
T8 Demodulation Mode
Program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising,
falling, or both depending on CTR1, D5; D4) is detected, it starts to count down.
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is
detected during counting, the current value of T8 is complemented and put into
one of the capture registers. If it is a positive edge, data is put into LO8, if negative
edge, HI8. One of the edge detect status bits (CTR1, D1; D0) is set, and an interrupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh
and starts counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set,
an interrupt can be generated if enabled (CTR0, D1), and T8 continues counting
from FFh (see Figure 19 and Figure 20).
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42
T8 (8-Bit)
Count Capture
No
T8 Enable
(Set by User)
Yes
No
Edge Present
Yes
What Kind
of Edge
Positive
Negative
T8 HI8
T8 LO8
FFh T8
Figure 19. Demodulation Mode Count Capture Flowchart
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43
T8 (8-Bit)
Demodulation Mode
No
T8 Enable
CTR0, D7
Yes
FFh TC8
No
First
Edge Present
Yes
Enable TC8
Disable TC8
No
T8_Enable
Bit Set
Yes
No
Edge Present
Yes
Set Edge Present Status
Bit and Trigger Data
Capture Int. If Enabled
No
T8 Timeout
Yes
Set Timeout Status
Bit and Trigger
Timeout Int. If Enabled
Continue Counting
Figure 20. Demodulation Mode Flowchart
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44
T16 Transmit Mode
In Normal or Ping-Pong Mode, the output of T16 when not enabled, is dependent
on CTR1, D0. If the result is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You
can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3, D2 to a 10 or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched
to its initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled
(in Normal or Ping-Pong Mode), an interrupt (CTR2, D1) is generated (if enabled),
and a status bit (CTR2, D5) is set. See Figure 21.
CTR2 D2
Z8 Data Bus
Positive Edge
IRQ3
Negative Edge
HI16
LO16
CTR2 D1
CTR2 D4, D3
SCLK
Clock
Select
Clock
TC16H
16-Bit
Counter T16
T16_OUT
TC16L
Z8 Data Bus
Figure 21. 16-Bit Counter/Timer Circuits
Note: Global interrupts override this function as described in
“Interrupts” on page 48.
If T16 is in Single-Pass Mode, it is stopped at this point (see Figure 22). If it is in
Modulo-N Mode, it is loaded with TC16H * 256 + TC16L, and the counting continues (see Figure 23).
You can modify the values in TC16H and TC16L at any time. The new values take
effect when they are loaded.
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45
Caution:
Do not load these registers at the time the values are to be
loaded into the counter/timer to ensure known operation.
An initial count of 1 is not allowed. An initial count of 0
causes T16 to count from 0 to FFFFh to FFFEh. Transition
from 0 to FFFFh is not a timeout condition.
TC16H*256+TC16L Counts
“Counter Enable” Command
T16_OUT Switches to Its
Initial Value (CTR1 D0)
T16_OUT Toggles,
Timeout Interrupt
Figure 22. T16_OUT in Single-Pass Mode
TC16H*256+TC16L
TC16_OUT
TC16H*256+TC16L
TC16H*256+TC16
“Counter Enable” Command,
T16_OUT Switches to Its
Initial Value (CTR1 D0)
T16_OUT Toggles,
Timeout Interrupt
...
T16_OUT Toggles,
Timeout Interrupt
Figure 23. T16_OUT in Modulo-N Mode
T16 Demodulation Mode
Program TC16L and TC16H to FFh. After T16 is enabled, and the first edge (rising, falling, or both depending on CTR1 D5, D4) is detected, T16 captures HI16
and LO16, reloads, and begins counting.
If D6 of CTR2 Is 0
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is
detected during counting, the current count in T16 is complemented and put into
HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1,
D1; D0) is set and an interrupt is generated if enabled (CTR2, D2). From that
point, T16 is loaded with FFFFh and starts again.
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46
This T16 mode is generally used to measure mark time, defined as the length of
time between carrier signal bursts (marks).
If D6 of CTR2 Is 1
T16 ignores the subsequent edges in the input signal and continues counting
down. A timeout of T8 causes T16 to capture its current value and generate an
interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues
counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge (rising, falling, or both depending on CTR1,
D5; D4), thereby continuing to ignore subsequent edges.
This T16 mode is generally used to measure mark time, defined as the length of
time between carrier signal bursts (marks).
If T16 reach 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2
D5) is set, and an interrupt timeout can be generated if enabled (CTR2 D1).
Ping-Pong Mode
This operation mode is only valid in Transmit Mode. T8 and T16 must be programmed in Single-Pass Mode (CTR0, D6, CTR2, D6) and Ping-Pong Mode must
be programmed in CTR1, D3; D2. The user can begin the operation by enabling
either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT
is set to this initial value (CTR1, D1). According to T8_OUT's level, TC8H or TC8L
is loaded into T8. After the terminal count is reached, T8 is disabled and T16 is
enabled. T16_OUT switches to its initial value (CTR1, D0), data from TC16H and
TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it
stops, T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed
when T8 or T16 reaches terminal control (CTR0, D1; CTR2, D1). To stop the PingPong operation, write 00 to bits D3 and D2 of CTR1. See Figure 24.
Note: Enabling Ping-Pong operation while the counter/timers are
running might cause intermittent counter/timer function. Disable
the counter/timers and then reset the status flags before
instituting this operation.
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47
Enable
TC8
Timeout
Enable
Ping-Pong
CTR1 D3,D2
TC16
Timeout
Figure 24. Ping-Pong Mode
Initiating Ping-Pong Mode
First, make sure both counter/timers are not running. Then, set T8 into SinglePass Mode (CTR0 D6), set T16 into Single-Pass Mode (CTR2 D6), and set the
Ping-Pong Mode (CTR1 D2, D3). These instructions do not have to be in any particular order. Finally, start Ping-Pong Mode by enabling either T8 (CTR0 D7) or
T16 (CTR2 D7). See Figure 25.
P34_INTERNAL
MUX
P34
CTR0 D0
T8_OUT
T16_OUT
P36_INTERNAL
AND/OR/NOR/NAND
Logic
MUX
MUX
P36
CTR1 D6
CTR1, D2
CTR1 D5, D4
P35_INTERNAL
MUX
P35
CTR1 D3
CTR2 D0
Figure 25. Output Circuit
The initial value of T8 or T16 must not be 1. If you stop the timer and start the
timer again, reload the initial value to avoid an unknown previous value.
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48
During Ping-Pong Mode
The enable bits of T8 and T16 (CTR0 D7, CTR2 D7) are set and cleared alternately by hardware. The timeout bits (CTR0 D5, CTR2 D5) are set every time the
counter/timers reach the terminal count.
Interrupts
The Z86L81/86/98 features six different interrupts (Table 14). The interrupts are
maskable and prioritized (Figure 26). The six sources are divided as follows: three
sources are claimed by Port 3 lines P33–P31, two by the counter/timers, and one
by LVD (Table 14). The Interrupt Mask Register globally or individually enables or
disables the six interrupt requests.
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49
P3
IRQ Register
D6, D7
P3
P3
Interrupt
Edge
Select
IRQ2
IRQ0
Timer 16
IRQ1
IRQ3
Timer 8
IRQ4
LowVoltage
Detection
IRQ5
IRQ
IMR
5
IPR
Global
Interrupt
Enable
Interrupt
Request
Priority
Logic
Vector Select
Figure 26. Interrupt Block Diagram
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Table 14. Interrupt Types, Sources, and Vectors
Name
Source
Vector Location
Comments
IRQ0
P32
0,1
External (P32), Rising Falling Edge
Triggered
IRQ1
P33
2,3
External (P33), Falling Edge Triggered
IRQ2
P31, TIN
4,5
External (P31), Rising Falling Edge
Triggered
IRQ3
T16
6,7
Internal
IRQ4
T8
8,9
Internal
IRQ5
LVD
10,11
Internal
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt
machine cycle is activated when an interrupt request is granted. As a result, all
subsequent interrupts are disabled, and the Program Counter and Status Flags
are saved. The cycle then branches to the program memory vector location
reserved for that interrupt. All Z86L81/86/98 interrupts are vectored through locations in the program memory. This memory location, and the next byte, contain the
16-bit address of the interrupt service routine for that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs are masked, and the
Interrupt Request register is polled to determine which of the interrupt requests
require service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling, or both edge
triggered; all are programmable by the user. The software can poll to identify the
state of the pin.
Programming bits for the Interrupt Edge Select are located in the IRQ Register
(R250), bits D7 and D6. The configuration is indicated in Table 15.
Table 15. IRQ Register*
IRQ
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Interrupt Edge
D7
D6
IRQ2(P31)
IRQ0 (P32)
0
0
F
F
0
1
F
R
1
0
R
F
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51
Table 15. IRQ Register* (Continued)
IRQ
1
Interrupt Edge
1
R/F
R/F
Notes:
F = Falling Edge
R = Rising Edge
*In stop mode, the comparators are turned off.
Clock
The Z86L81/86/98 on-chip oscillator has a high-gain, parallel-resonant amplifier,
for connection to a crystal, LC, ceramic resonator, or any suitable external clock
source (XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8
MHz maximum, with a series resistance (RS) less than or equal to 100 Ohms. The
Z86LXX on-chip oscillator can be driven with a low-cost RC network or other suitable external clock source.
For 32-kHz crystal operation, both an external feedback (Rf) and serial resistor
(Rd) are required. See Figure 27.
The crystal must be connected across XTAL1 and XTAL2 using the recommended
capacitors (capacitance greater than or equal to 22 pF) from each pin to ground.
The RC oscillator configuration is an external resistor connected from XTAL1 to
XTAL2, with a frequency-setting capacitor from XTAL1 to ground (Figure 27).
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XTAL1
C1
XTAL1
C1
R
L
XTAL2
C2
Ceramic Resonator or Crystal
C1, C2 = 47 pF TYP *
f = 8 MHz
C1
C2
XTAL2
C2
XTAL1
C1
LC
C1, C2 = 22 pF
L = 130 H *
f = 3 MHz *
XTAL1
XTAL1
XTAL2
XTAL2
XTAL2
RC
@ 3V VCC (TYP)
C1 = 33 pF *
R = 1K *
Rf
Rd
32 kHz XTAL
C1 = 20 pF, C = 33 pF
Rd = 56 - 470K
Rf = 10 M
External Clock
* Preliminary value including pin parasitics
Figure 27. Oscillator Configuration
Power-On Reset (POR)
A timer circuit clocked by a dedicated on-board RC oscillator is used for the
Power-On Reset (POR) timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
•
•
Power Fail to Power OK status, including Waking up from VBO Standby
Stop-Mode Recovery (if D5 of SMR = 1)
WDT Timeout
The POR timer is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines
whether the POR timer is bypassed after Stop-Mode Recovery (typical for external
clock, RC, LC oscillators).
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HALT
HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/
timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.
The devices are recovered by interrupts, either externally or internally generated.
An interrupt request must be executed (enabled) to exit HALT Mode. After the
interrupt service routine, the program continues from the instruction after the
HALT.
STOP
This instruction turns off the internal clock and external crystal oscillation, thereby
reducing the standby current to 10 A or less. STOP Mode is terminated only by a
reset (such as WDT timeout), POR, SMR, or external reset. This termination
causes the processor to restart the application program at address 000Ch. In
order to enter STOP (or HALT) mode, first flush the instruction pipeline to avoid
suspending execution in mid-instruction. Execute a NOP (Op Code = FFh) immediately before the appropriate sleep instruction, as follows:
FF
6F
NOP
STOP
; clear the pipeline
; enter STOP Mode
FF
7F
NOP
HALT
; clear the pipeline
; enter HALT Mode
or
Port Configuration Register (PCON)
The PCON register (Figure 28) configures the comparator output on Port 3. It is
located in the expanded register 2 at Bank F, location 00.
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PCON (FH) 00H
D7
D6
D5
D4
D3
D2
D1
D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Port 0
0: Open-Drain
1: Push-Pull
Reserved (Must be 1)
* Default setting after reset
Figure 28. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration.
Port0 Output Mode (D2)
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of StopMode Recovery (Figure 29). All bits are write only except bit 7, which is read only.
Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or a high level at the XORgate input is required from the recovery source. Bit 5 controls the reset delay after
recovery. Bits D2, D3, and D4, or the SMR register, specify the source of the StopMode Recovery signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not.
The SMR is located in Bank F of the Expanded Register Group at address 0Bh.
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SMR (0F) 0B
D7
D6
D5
D4
D3
D2
D1
D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
* Default setting after reset
* * Default setting after reset and stop-mode recovery
* * * At the XOR gate input
Figure 29. Stop-Mode Recovery Register
SCLK/TCLK Divide-by-16 Select (D0)
D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (Figure 30). The
purpose of this control is to selectively reduce device power consumption during
normal processor execution (SCLK control) and/or HALT Mode (where TCLK
sources interrupt logic). After Stop-Mode Recovery, this bit is set to a 0.
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OSC
2
SCLK
 16
SMR, D0
TCLK
Figure 30. SCLK Circuit
Stop-Mode Recovery Source (D2, D3, and D4)
These three bits of the SMR specify the wake-up source of the STOP recovery
(Figure 31 and Table 16).
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SMR D4 D3 D2
0 0 0
SMR2 D4 D3 D2
0 0 0
VCC
VCC
SMR D4 D3 D2
0 1 0
P31
S1
SMR D4 D3 D2
0 1 1
P32
S2
SMR D4 D3 D2
1 0 0
P33
To IRQ1
S3
P20
P23
P20
P27
P20
SMR D4 D3 D2
1 1 0
P23
P20
SMR D4 D3 D2
1 1 1
P27
SMR D6
To RESET and WDT
Circuitry (Active Low)
Figure 31. Stop-Mode Recovery Source
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SMR2 D4 D3 D2
0 1 0
P27
P31
P32
P33
S4
SMR D4 D3 D2
1 0 1
SMR2 D4 D3 D2
0 0 1
P31
P32
P33
P31
P32
P33
P00
P07
P31
P32
P33
P00
P07
P31
P32
P33
P20
P21
P22
SMR2 D4 D3 D2
0 1 1
SMR2 D4 D3 D2
1 0 0
SMR2 D4 D3 D2
1 0 1
SMR2 D4 D3 D2
1 1 0
SMR2 D4 D3 D2
1 1 1
SMR2 D6
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Table 16. Stop-Mode Recovery Source
SMR:432
Operation
D4
D3
D2
Description of Action
0
0
0
POR and/or external reset
recovery
0
0
1
Reserved
0
1
0
P31 transition
0
1
1
P32 transition
1
0
0
P33 transition
1
0
1
P27 transition
1
1
0
Logical NOR of P20 through P23
1
1
1
Logical NOR of P20 through P27
Note: Any Port 2 bit defined as an output drives the corresponding
input to the default state to allow the remaining inputs to control
the AND/OR function. Refer to SMR2 register on page 58 for
other recover sources.
Stop-Mode Recovery Delay Select (D5)
This bit, if low, disables the 5 ms RESET delay after Stop-Mode Recovery. The
default configuration of this bit is 1. If the “fast” wake up is selected, the StopMode Recovery source must be kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select (D6)
A 1 in this bit position indicates that a High level on any one of the recovery
sources wakes the Z86L81/86/98 from STOP Mode. A 0 indicates Low level
recovery. The default is 0 on POR.
Cold or Warm Start (D7)
This bit is read only, and it is set to 1 when the device is recovered from stop
mode. The bit is set to 0 when the device reset is other than Stop Mode Recovery
(SMR).
Stop-Mode Recovery Register 2 (SMR2)
This register determines the mode of Stop-Mode Recovery for SMR2 (Figure 32).
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SMR2 (0F) DH
D7
D6
D5
D4
D3
D2
D1
D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0 Low
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
* Default setting after reset
* * At the XOR gate input
Figure 32. Stop-Mode Recovery Register 2 ((0F) DH:D2–D4, D6 Write Only)
If SMR2 is used in conjunction with SMR, either of the specified events causes a
Stop-Mode Recovery.
Note: Port pins configured as outputs are ignored as an SMR or
SMR2 recovery source. For example, if the NAND or P23–P20
is selected as the recovery source and P20 is configured as an
output, the remaining SMR pins (P23–P21) form the NAND
equation.
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Watch-Dog Timer Mode Register (WDTMR)
The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction.
On subsequent executions of the WDT instruction, the WDT is refreshed. The
WDT circuit is driven by an on-board RC oscillator or external oscillator from the
XTAL1 pin. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V)
flags.
The POR clock source is selected with bit 4 of the WDT register. Bit 0 and 1 control a tap circuit that determines the minimum time-out period. Bit 2 determines
whether the WDT is active during HALT, and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 8). This register is accessible only
during the first 61 processor cycles (122 XTAL clocks) from the execution of the
first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode
Recovery (Figure 33). After this point, the register cannot be modified by any
means (intentional or otherwise). The WDTMR cannot be read. The register is
located in Bank F of the Expanded Register Group at address location 0Fh. It is
organized as shown in Figure 33.
WDTMR (0F) 0F
D7
D6
D5
D4
D3
D2
D1
D0
WDT TAP INT RC OSC
00
5 ms min
01*
10 ms min
10
20 ms min
11
80 ms min
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
Reserved (Must be 0)
Reserved (Must be 0)
* Default setting after reset
Figure 33. Watch-Dog Timer Mode Register (Write Only)
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WDT Time Select (D0, D1)
Selects the WDT time period. It is configured as indicated in Table 17.
Table 17. WDT Time Select*
D1
D0
Timeout of Internal RC OSC
0
0
5 ms min
0
1
10 ms min
1
0
20 ms min
1
1
80 ms min
Note:
*TpC = XTAL clock cycle. The default on reset is 10 ms.
WDTMR During HALT (D2)
This bit determines whether or not the WDT is active during HALT Mode. A 1 indicates active during HALT. The default is 1. See Figure 34.
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*CLR2
CLK
5 Clock Filter
18 Clock RESET
RESET
Generator
Internal
RESET
Active
High
WDT
CK Source
Select
(WDTMR)
XTAL
INTERNAL
RC
OSC.
VDD
VBO/VLV
2V REF.
+
-
M
U
X
TAP SELECT
POR
5 ms 10 ms 20 ms 80 ms
CLK
WDT/POR Counter Chain
*CLR1
Low Operating
Voltage Det.
WDT
From Stop
Mode
Recovery
Source
VCC
12-ns Glitch Filter
Stop Delay
Select (SMR)
* CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers upon a Low-to-High input translation.
Figure 34. Resets and WDT
WDTMR During STOP (D3)
This bit determines whether or not the WDT is active during STOP Mode.
Because the XTAL clock is stopped during STOP Mode, the on-board RC has to
be selected as the clock source to the WDT/POR counter. A 1 indicates active
during STOP. The default is 1.
Clock Source for WDT (D4)
This bit determines which oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the
POR and WDT clock source is driven from the external pin, XTAL1. The default
configuration of this bit is 0, which selects the RC oscillator.
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Mask Selectable Options
There are seven Mask Selectable Options to choose from based on ROM code
requirements. These are listed in Table 18.
Table 18. Mask Selectable Options
RC/Other
RC/XTAL
32 kHz XTAL
On/Off
Port 04-07 Pull-Ups
On/Off
Port 00-03 Pull-Ups
On/Off
Port 20-27 Pull-Ups
On/Off
Port 3 Pull-Ups
On/Off
Port0: 0-3 Mouse Mode 0.4 VDD Trip
On/Off
Brown-Out Voltage/Standby
An on-chip Voltage Comparator checks that the VCC is at the required level for
correct operation of the device. Reset is globally driven when VCC falls below VBO.
A small further drop in VCC causes the XTAL1 and XTAL2 circuitry to stop the
crystal or resonator clock. Typical Low-Voltage power consumpion in this Low
Voltage Standby mode (ILV) is about 20 A. If the VCC is allowed to stay above
Vram, the RAM content is preserved. When the power level is returned to above
VBO, the device performs a POR and functions normally.
Low-Voltage Detection and Flag
A Low-Voltage Detection circuit can be used optionally when the voltage
decreases to VLVD. Expanded Register Bank 0Dh register 0Ch bit 0 and 1 are used
for this option.
Bit D0 is used to enable/disable this function.
Bit D1 is the status flag bit of the LVD.
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Expanded Register File Control Registers (0D)
The expanded register file control registers (0D) are shown in Figure 35 through
Figure 38.
CTR0 (0D) 0H
D7
D6
D5
D4
D3
D2
D1
D0
0 P34 as Port Output *
1 Timer8 Output
0 Disable T8 Timeout Interrupt
1 Enable T8 Timeout Interrupt
0 Disable T8 Data Capture Interrupt
1 Enable T8 Data Capture Interrupt
00
01
10
11
R
R
W
W
SCLK on T8
SCLK/2 on T8
SCLK/4 on T8
SCLK/8 on T8
0 No T8 Counter Timeout
1 T8 Counter Timeout Occurred
0 No Effect
1 Reset Flag to 0
0 Modulo-N
1 Single Pass
R
R
W
W
0 T8 Disabled *
1 T8 Enabled
0 Stop T8
1 Enable T8
* Default setting after reset
Figure 35. T8 Control Register ((0D) OH: Read/Write Except Where Noted)
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CTR1 (0D) 1H
D7
D6
D5
D4
D3
D2
D1
D0
Transmit Mode
R/W 0 T16_OUT is 0 initially
1 T16_OUT is 1 initially
Demodulation Mode
R 0 No Falling Edge Detection
R 1 Falling Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
Transmit Mode
R/W 0 T8_OUT is 0 initially
1 T8_OUT is 1 initially
Demodulation Mode
R 0 No Rising Edge Detection
R 1 Rising Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
Transmit Mode
0 0 Normal Operation
0 1 Ping-Pong Mode
1 0 T16_OUT = 0
1 1 T16_OUT = 1
Demodulation Mode
0 0 No Filter
0 1 4 SCLK Cycle Filter
1 0 8 SCLK Cycle Filter
1 1 Reserved
Transmit Mode/T8/T16 Logic
0 0 AND
0 1 OR
1 0 NOR
1 1 NAND
Demodulation Mode
0 0 Falling Edge Detection
0 1 Rising Edge Detection
1 0 Both Edge Detection
1 1 Reserved
Transmit Mode
0 P36 as Port Output *
1 P36 as T8/T16_OUT
Demodulation Mode
0 P31 as Demodulator Input
1 P20 as Demodulator Input
* Default setting after reset
Transmit/Demodulation Mode
0 Transmit Mode *
1 Demodulation Mode
Figure 36. T8 and T16 Common Control Functions ((0D) 1h: Read/Write)
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Notes: Care must be taken in differentiating Transmit Mode from
Demodulation Mode. Depending on which of these two modes
is operating, the CTR1 bit has different functions.
Changing from one mode to another cannot be done without
disabling the counter/timers.
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CTR2 (0D) 02H
D7
D6
D5
D4
D3
D2
D1
D0
0 P35 is Port Output *
1 P35 is TC16 Output
0 Disable T16 Timeout Interrupt
1 Enable T16 Timeout Interrupt
0 Disable T16 Data Capture Interrupt
1 Enable T16 Data Capture Interrupt
0
0
1
1
0
1
0
1
SCLK on T16
SCLK/2 on T16
SCLK/4 on T16
SCLK/8 on T16
R
R
W
W
0
1
0
1
No T16 Timeout
T16 Timeout Occurs
No Effect
Reset Flag to 0
Transmit Mode
0 Modulo-N for T16
0 Single Pass for T16
Demodulator Mode
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
* Default setting after reset
R
R
W
W
0
1
0
1
T16 Disabled *
T16 Enabled
Stop T16
Enable T16
Figure 37. T16 Control Register ((0D) 2h: Read/Write Except Where Noted)
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LVD (0D) 0CH
D7
D6
D5
D4
D3
D2
D1
D0
Low-Voltage Detection at VBO + 0.4 V
0: Disable *
1: Enable
LVD Flag (Read only)
0: LVD flag reset *
1: LVD flag set
Reserved (Must be 0)
* Default
Figure 38. Low-Voltage Detection
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Expanded Register File Control Registers (0F)
The expanded register file control registers (0F) are shown in Figure 39 through
Figure 52.
SMR (0F) 0B
D7
D6
D5
D4
D3
D2
D1
D0
SCLK/TCLK Divide-by-16
0 OFF *
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
* Default setting after reset
* * Default setting after reset and stop-mode recovery
* * * At the XOR gate input
Figure 39. Stop-Mode Recovery Register ((0F) 0Bh: D6–D0=Write Only, D7=Read
Only)
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SMR2 (0F) DH
D7
D6
D5
D4
D3
D2
D1
D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0 Low
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
* Default setting after reset
* * At the XOR gate input
Figure 40. Stop-Mode Recovery Register 2 ((0F) 0Dh:D2–D4, D6 Write Only)
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WDTMR (0F) 0F
D7
D6
D5
D4
D3
D2
D1
D0
WDT TAP INT RC OSC
00
5 ms min
01*
10 ms min
10
20 ms min
11
80 ms min
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
Reserved (Must be 0)
Reserved (Must be 0)
* Default setting after reset
Figure 41. Watch-Dog Timer Register ((0F) 0Fh: Write Only)
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PCON (FH) 00H
D7
D6
D5
D4
D3
D2
D1
D0
Comparator Output Port 3
0 P34, P37 Standard Output *
1 P34, P37 Comparator Output
Reserved (Must be 1)
Port 0
0: Open-Drain
1: Push-Pull *
Reserved (Must be 1)
* Default setting after reset
Figure 42. Port Configuration Register (PCON) ((0F) 0h: Write Only)
R246 P2M
D7
D6
D5
D4
D3
D2
D1
D0
P27–P20 I/O Definition
0 Defines bit as OUTPUT
1 Defines bit as INPUT *
* Default setting after reset
Figure 43. Port 2 Mode Register (F6h: Write Only)
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R247 P3M
D7
D6
D5
D4
D3
D2
D1
D0
0: Port 2 Open Drain
1: Port 2 Push-Pull
0= P31, P32 Digital Mode
1= P31, P32 Analog Mode
Reserved (Must be 0)
* Default setting after reset
Figure 44. Port 3 Mode Register (F7h: Write Only)
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R248 P01M
D7
D6
D5
D4
D3
D2
D1
D0
P00–P03 Mode
0: Output
1: Input *
Reserved; must be 0
Reserved; must be 1
Reserved; must be 0
P07–P04 Mode
0: Output
1: Input *
Reserved; must be 0
* Default setting after reset
Figure 45. Port 0 and 1 Mode Register (F8h: Write Only)
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R249 IPR
D7
D6
D5
D4
D3
D2
D1
D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B >C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4, Priority
(Group C)
0: IRQ1 > IRQ4
1: IRQ4 > IRQ1
IRQ0, IRQ2, Priority
(Group B)
0: IRQ2 > IRQ0
1: IRQ0 > IRQ2
IRQ3, IRQ5, Priority
(Group A)
0: IRQ5 > IRQ3
1: IRQ3 > IRQ5
Reserved; must be 0
Figure 46. Interrupt Priority Register (F9h: Write Only)
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R250 IRQ
D7
D6
D5
D4
D3
D2
D1
D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16
IRQ4 = T8
IRQ5 = LVD
Inter Edge
P31
P32 = 00
P31
P32 = 01
P31
P32 = 10
P31 P32 = 11
Figure 47. Interrupt Request Register (FAh: Read/Write)
R251 IMR
D7
D6
D5
D4
D3
D2
D1
D0
1 Enables IRQ5–IRQ0
(D0 = IRQ0)
Reserved (Must be 0)
0 Master Interrupt Disable *
1 Master Interrupt Enable * *
* Default setting after reset
* * Only by using E1, D1 instruction; D1 is required before changing the IMR register
Figure 48. Interrupt Mask Register (FBh: Read/Write)
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R252 Flags
D7
D6
D5
D4
D3
D2
D1
D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Tag
Zero Flag
Carry Flag
Figure 49. Flag Register (FCh: Read/Write)
R253 RP
D7
D6
D5
D4
D3
D2
D1
D0
Expanded Register Bank Pointer
Working Register Pointer
Default setting after reset = 0000 0000
Figure 50. Register Pointer (FDh: Read/Write)
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R254 SPH
D7
D6
D5
D4
D3
D2
D1
D0
General-Purpose Register
Byte (SP15–SP8)
Figure 51. Stack Pointer High (FEh: Read/Write)
R255 SPL
D7
D6
D5
D4
D3
D2
D1
D0
Stack Pointer Lower
Byte (SP7–SP0)
Figure 52. Stack Pointer Low (FFh: Read/Write)
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79
Package Information
Package information is shown in Figure 53, Figure 54, and Figure 55.
Figure 53. 28-Pin DIP Package Diagram
Note: Please check with Maxim on the actual bonding diagram and
coordinate for chip-on-board assembly.
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Controlling dimensions: MM
Leads are coplanar within
.004 inch.
Symbol
Millimeter
Min
Max
Inch
Min
Max
A
2.40
2.64
.094
.104
A1
0.10
0.30
.004
.012
A2
2.24
2.44
.088
.096
B
0.36
0.46
.014
.018
C
0.23
0.30
.009
.012
D
17.78
18.00
.700
.710
E
7.40
7.60
.291
.299
1.27 typ
e
.050 typ
H
10.00
10.65
0.394
.419
h
0.30
0.71
.012
.028
L
0.61
1.00
.024
.039
Q1
0.97
1.07
.038
.042
Figure 54. 28-Pin SOIC Package Diagram
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Figure 55. 28-Pin SSOP Package Diagram
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Ordering Information
Z86L81/86/98—8.0 MHz
28-Pin DIP
Z86L8108PSC
Z86L8608PSC
Z86L9808PSC
28-Pin SOIC
Z86L8108SSC
Z86L8608SSC
Z86L9808SSC
28-Pin SSOP
Z86L8108HSC
Z86L8608HSC
Z86L9808HSC
Die Form
Please contact Maxim.
For fast results, contact your local Maxim sales office for assistance in ordering
the part required.
Codes
Package
P = Plastic DIP
S = SOIC (Small Outline Integrated Circuit)
H = SSOP (Shrink Small Outline Package)
Temperature
S = 0 °C to +70 °C
Speed
8 = 8.0 MHz
Environmental
C = Plastic Standard
G = Lead Free
Example
Z
86L98
08
P
S
C
is a Z86L98, 8 MHz, DIP, 0 °C to 70 °C, Plastic Standard
Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Maxim Prefix
19-4615; Rev 0; 4/09