ZILOG Z89332

PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
1
Z89332
1
DIGITAL TELEVISION CONTROLLER
FEATURES
Device
ROM
(KW)
RAM*
(Words)
PWM
(8-Bit)
Voltage
Range
Z89332
24
640
8
4.5 to 5.5V
Note: *General-Purpose
■
■
42-Pin SDIP and 48-Pin Ceramic Packages with
42- to 48-Pin Adapter Socket
0°C to +70°C Temperature Range
■
Fully Customized Character Set
■
Character-Control and Closed-Caption Modes
■
Keypad User Control
■
TV Tuner Serial Interface
■
Direct Video Signals
■
Speed: 12 MHz
GENERAL DESCRIPTION
The Z89332 Digital Television Controller is designed to
provide complete audio and video control of television receivers, video recorders, and advanced on-screen display
facilities. The television controller features a Z89C00 RISC
processor core that controls the on-board peripheral functions and registers using the standard processor instruction set.
Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode provides access to the full set of attribute controls, allowing the
modification of attributes on a character-by-character basis. The insertion of control characters permits direction of
other character attributes. Closed-caption text can be decoded directly from the composite video signal and displayed on-screen with the assistance of the processor's
digital signal processing (DSP) capabilities.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of display attributes that include underlining, italics, blinking,
eight foreground/background colors, character position offset delay, and background transparency.
CP96TEL0607
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tunning adjustments, may be accessed
through the industry-standard I2C port.
User control can be monitored through the keypad scanning port, or the 16-bit remote control capture register. Receiver functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.
Notes:
All Signals with a preceding front slash, "/", are active Low,
e.g.: B//W (WORD is active Low); /B/W (BYTE is active
Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
PRELIMINARY
1-1
Z89332
Digital Television Controller
GENERAL DESCRIPTION (Continued)
PWM
PWM1
PWM2
PWM3
PWM4
PWM5
PWM9
PWM10
Capture
IRIN
ADC
Port 17
Port 00
ADC0
ADC1
ADC2
ADC3
ADC4
Port1
Port 0
Port 00
Port 01
Port 02
Port 03
Port 04
Port 05
Port 06
Port 07
Port 08
Port 09
Port 0F
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
Control
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/Reset
V1
V2
V3
VBLANK
HALFBLNK
CPU
RAM
640 x 16
OSD
Register Addr/Data
Port0F
Address
ROM Addr
Data
ROM
24K x 16
ROM Data
Figure 1. Functional Block Diagram
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PRELIMINARY
CP96TEL0607
Z89332
Digital Television Controller
PIN DESCRIPTION
PWM10
1
42
Port12/I2MSD
PWM9
2
41
P11/I2MSC
PWM5
3
40
Port02/I2SSD
PWM4
4
39
Port01/I2SSC
PWM3
5
38
Port09
PWM2
6
37
Port08/R<1>
PWM1
7
36
IRIN
Port03
8
35
Port07/CSync
Port04/ADC4
9
34
Vcc
Port05/ADC3
10
33
/Reset
Port00/ADC2
11
32
XTAL2
Port17/ADC1
12
31
XTAL1
GND
13
30
ANGND
Port10/R<0>
14
29
LPF
Port06/Counter
15
28
CVI/ADC0
Port18/G<0>
16
27
VSync
Port13/G<1>
17
26
HSync
Port14/B<0>
18
25
VBlank
Port15/B<1>
19
24
V1
Port16/SCLK
20
23
V2
Port0F/HalfBlnk
21
22
V3
Z89332
Shrink
DIP
1
Figure 2. 42-Pin Shrink DIP and 48-Pin Ceramic Pin Configurations
with 42- to 48-Pin Adapter Footprint
CP96TEL0607
PRELIMINARY
1-3
Z89332
Digital Television Controller
Table 1. 42-Pin SDIP Pin Identification
Name
Function
Z89332
Direction
Reset
VCC
+ 5 Volts
34
PWR
–
PWR
I
–
I
AI
O
I
O
OD/O*
O
B
I
B
I
GND
IRIN
0 Volts
13, 30
Infrared Remote Capture
36
Input
ADC[4:0]
4-Bit A/D Converter Input
9, 10, 11, 12, 28
PWM10, PWM9
14-Bit Pulse Width
1, 2
Modulator Output
PWM[5:1]
8-Bit Pulse Width Modulator
3, 4, 5, 6, 7
Output
Port0[F:0]
Bit Programmable
21, -, -, -, -, -, 38, 37,
Input/Output Ports
35, -, -, 15, 8, 40, 39,
11
Port1[8:0]
Bit Programmable
16, 12, 20, 19, 18, 17,
Input/Output Ports
42, 41, 14
2
SCL
39 or 41
I C Clock I/O
SCD
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/Reset
V[3:1]
I2C Data I/O
Crystal Oscillator Input
Crystal Oscillator Output
Loop Filter
H_SYNC
V_SYNC
Device Reset
OSD Video Output Typically
Drive B, G, and R Outputs
[1]
BOD
[2]
40 or 42
BOD
[3]
31
32
29
26
27
33
22, 23, 24
AI
AO
AB
B
B
I
O
I
O
O
I
I
I
O
O
O
O
O
Blank
OSD Blank Output
25
HalfBlank
OSD Half-Blank Outpu
21
RGB Digital
R[1:0], G[1:0], and B[1:0] 37, 14, 17, 16, 19, 18
Outputs
Outputs of the RGB Matrix
SCLK
Internal Processor SCLK
20
Notes:
1) Port 0 [E:A] is not available on the 42-pin SDIP version.
2) SCL I/O pin is shared with Port 0 or Port 11.
3) SCD I/O pin is shared with Port 02 or Port 12.
4) Half Blank output is a function shared with Port 0F.
5) Digital RGB outputs and the internal SCLK are shared with Port 1 [5:0].
6) Internal processor SCLK is shared with Port 16.
* PWM outputs are push/pull in Revision Z89332EA and later.
1-4
Notes
PRELIMINARY
O
[4]
[5]
[6]
CP96TEL0607
Z89332
Digital Television Controller
V1, V2, V3 ANALOG OUTPUT
Specifications VCC = 5.25V and VCC = 4.75V
1
VCC = 5.25V
Condition
Limit
Output Voltage
Setting Time
Bit = 11
Bit = 10
Bit = 01
Bit = 00
70% of DC Level, 10 pF Load
4.2V ± 0.4V
45% – 0.15V to 55% of actual data = 11 value
0.60 V ± 0.4V
74% to 89% of actual data = 11 value
< 50 nsec
VCC = 4.75V
Condition
Limit
Output Voltage
Bit = 11
Bit = 10
Bit = 01
Bit = 00
70% of DC Level, 10 pF Load
3.6V ± 0.4V
45% – 0.15V to 55% of actual data = 11 value
0.60V ± 0.4V
74% to 89% of actual data = 11 value
< 50 nsec
Setting Time
32.768kHz
10 pF
10 MΩ
Z893XX
XTAL1
XTAL2
68 KΩ
47 pF
Figure 3. 32K Oscillator Recommended Circuit
Z893XX
510 Ω
47 µF
0.1 µF
Figure 4. Recommended Low Pass Filter Circuit
CP96TEL0607
PRELIMINARY
1-5
Z89332
Digital Television Controller
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
Conditions
VCC
Power Supply Voltage
0
7
V
VID
Input Voltage
–0.3
VCC +0.3
V
Digital Inputs
VIA
Input Voltage
–0.3
VCC +0.3
V
Analog Inputs (A/D0...A/D4)
VO
Output Voltage
–0.3
VCC +0.3
V
All Push-Pull Digital Output
VO
Output Voltage
–0.3
VCC +8
VO
Output Voltage
–0.3
VCC +0.3
V
IOH
Output Current High
–10
mA
Open-Drain PWM Outputs
(PWM1...PWM8)
Push/Pull PWM Outputs
(PWM1...PWM8) = Z89332EA
and Later Revisions
One Pin
IOH
Output Current High
–100
mA
All Pins
IOL
Output Current Low
20
mA
One Pin
IOL
Output Current Low
200
mA
All Pins
TA
Operating Temperature
0
70
°C
TA
Storage Temperature
–65
150
°C
DC CHARACTERISTICS
TA = 0°C to + 70°C; VCC = 4.5V to + 5.5V; FOSC = 32.768 KHz
Symbol
Parameter
Min
Max
Typical
Units
VIL
Input Voltage Low
0
0.2 VCC
0.4
V
VIH
Input Voltage High
0.7 VCC
VCC
3.6
V
VPU
Max. Pull-Up Voltage
VCC +0.3
VOL
Output Voltage Low
0.4
VOH
Output Voltage High
VXL
Input Voltage XTAL1 Low
VXH
Input Voltage XTAL1 High
VCC –2.0
VHY
Schmitt Hysteresis
3.0
IIR
Reset Input Current
IIL
Input Leakage
ICC
Conditions
V
All Pins
0.16
V
@ IOL = 1 mA
4.75
V
@ IOL = 0.75 mA
1.0
V
External Clock
3.5
V
Generator Driven
0.75
0.5
V
On XTAL1 Input Pin
150
90
µA
VRL = 0V
3.0
0.01
µA
@ 0V and VCC
Supply Current
100
60
mA
IADC
Input Current
0.5
mA
AE Revision
IADC
Input Current
10
µA
CC,CA,EA & Later Rev.
VCC –0.4
0.3 VCC
–3.0
Notes:
A) The Z89332 should not be operated for extended periods with the crystal oscillator disconnected, except in the defined
power-down modes. In the event that the Z89332 is operated with the oscillator disconnected, the device may draw higher
than typical current.
B) Each line of the on-screen display can consist of any number of characters, up to a maximum of 30 characters.
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PRELIMINARY
CP96TEL0607
Z89332
Digital Television Controller
AC CHARACTERISTICS
TA = 0°C to + 70°C; VCC = 4.5V to 5.5V; FOSC = 32.768 KHz
Symbol
Parameter
Min
Max
Typical
Units
T PC
Input Clock Period
16
100
32
µS
TRC,TFC
Clock Input Rise and Fall
12
µS
TDPOR
Power-On Reset Delay
1.2
Sec
0.8
1
AC CHARACTERISTICS
TA = 0°C to + 70°C; VCC = 4.5V to 5.5V; FOSC = 32.768 KHz
Symbol
Parameter
Min
Max
Typical Units
TWRES
Power-On Reset Min. Width
TDHS
H_Sync Incoming Signal Width
5.5
12.5
11
µS
TDVS
V_Sync Incoming Signal Width
0.15
1.5
1.0
mS
TDES
Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field
–12
+12
0
µS
TDOS
Time Delay Between Leading Edge of H_Sync in Odd Field
20
44
32
µS
TWHVS
H_Sync/V_Sync Edge Width
2.0
0.5
µS
µS
5 TPC
Note:
All timing of the I2C bus interface are defined by related specifications of the I2C bus interface.
CP96TEL0607
PRELIMINARY
1-7
Z89332
Digital Television Controller
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PRELIMINARY
CP96TEL0607