INTERSIL ZL9101MIRZ

Digital DC/DC PMBus 12A Module
ZL9101M
Features
The ZL9101M is a 12A variable output step-down
PMBus-compliant digital power supply. Included in the module
is a high performance digital PWM controller, power MOSFETs,
an inductor, and all the passive components required for a
complete DC/DC power solution. The ZL9101M operates over
a wide input voltage range and supports an output voltage
range of 0.6V to 4V, which can be set by external resistors or
via PMBus. This high efficiency power module is capable of
delivering 12A. Only bulk input and output capacitors are
needed to finish the design. The output voltage can be
precisely regulated to as low as 0.6V with ±1% output voltage
regulation over line, load, and temperature variations.
• Complete Digital Switch Mode Power Supply
The ZL9101M features internal compensation, internal
soft-start, auto-recovery overcurrent protection, an enable
option, and pre-biased output start-up capabilities.
• Server, Telecom, and Datacom
• Fast Transient Response
• External Synchronization
• Output Voltage Tracking
• Current Sharing
• Programmable Soft-start Delay and Ramp
• Overcurrent/Undercurrent Protection
• PMBus Compliant
Applications
• Industrial and Medical Equipment
• General Purpose Point of Load
The ZL9101M is packaged in a thermally enhanced, compact
(15mmx15mm) and low profile (3.5mm) over-molded QFN
package module suitable for automated assembly by standard
surface mount equipment. The ZL9101M is Pb-free and RoHS
compliant.
Related Literature
• See AN2033, “Zilker Labs PMBus Command Set - DDC
Products”
• See AN2034, “Configuring Current Sharing on the ZL2004
and ZL2006”
V DRV
4.7µF
16V
10µF
16V
4.5V TO 6.5V
4.7µF
16V
10µF
16V
V IN
5V TO 12V
VDD
V25
PG
ENABLE
VR
POWER GOOD OUTPUT
VDRV
2 x 22µF
16V
VIN
(EPAD)
EN
Ext Sync
SYNC
DDC Bus
2
I C/SMBus
1
ZL9101M
DDC
SW
(EPAD)
SCL
FB+
PGND
(EPAD)
3 x 47µF
16V
3
RTN
FB-
SGND
SA
VTRK
SDA
VSET
2
V OUT
VOUT
(EPAD)
Notes:
1. The I2C/SMBus requires pull-up resistors. Please refer to the I2C/SMBus specifications for more details.
2. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of
devices connected). The 10k default value, assuming a maximum of 100pF per device, provides the necessary 1µs pull-up rise time.
Please refer to the Digital-DC Bus section for more details.
3. Additional capacitance may be required to meet specific transient response targets
4. The VR, V25, VDRV, and VDD capacitors should be placed no further than 0.5 cm from the pin.
FIGURE 1. 12A APPLICATION CIRCUIT
NOTE: Figure 1 represents a typical implementation of the ZL9101M. For PMBus operation, it is recommended to tie the enable pin (EN) to SGND.
January 26, 2011
FN7669.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ZL9101M
Pin Configuration
SGND
VR
DDC
EN
PG
SYNC
SA
SCL
ZL9101M
(21 LD QFN)
TOP VIEW
9
8
7
6
5
4
3
2
1
SDA
PGND
10
21
VSET
V25
11
20
VTRK
VDD
12
19
FB+
VDRV
13
18
FB-
14
SW
VOUT
17
VIN
15
PGND
16
PIN
LABEL
TYPE
DESCRIPTION
1
SDA
I/O
Serial data.
2
SCL
I/O
Serial clock.
3
SA
I
Serial address select pin. Used to assign unique SMBus address to each module.
4
SYNC
I/O
Clock synchronization. Used for synchronization to external frequency reference.
5
PG
O
Power-good output.
6
EN
I
Enable input (factory setting active high). Pull-up to enable PWM switching and pull-down to disable PWM switching.
7
DDC
I/O
8
VR
PWR
Internal 5V reference used to power internal drivers.
9
SGND
PWR
Signal ground. Connect to low impedance ground plane.
10
PGND
PWR
Power ground. Connect to low impedance ground plane.
11
V25
PWR
Internal 2.5V reference used to power internal circuitry.
12
VDD
PWR
Input supply voltage for controller.
13
VDRV
PWR
Power supply for internal FET drivers. Connect 10μF bypass capacitor to this pin.
14(epad)
SW
PWR
Drive train switch node
15(epad)
VIN
PWR
Power supply input FET voltage.
16(epad)
PGND
PWR
Power ground. Connect to low impedance ground plane.
17(epad)
VOUT
PWR
Power supply output voltage. Output voltage from PWM.
18
FB-
I
Output voltage feedback. Connect to load return of ground regulation point.
19
FB+
I
Output voltage feedback. Connect to output regulation point.
20
VTRK
I
Tracking sense input. Used to track an external voltage source.
21
VSET
I
Output voltage selection pin. Used to set VOUT set point and VOUT max.
Digital-DC bus. (open drain) Interoperability between Zilker Labs modules.
2
FN7669.1
January 26, 2011
ZL9101M
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ZL9101MIRZ
PART
MARKING
ZL9101M
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
21 LD 15x15 QFN
PKG.
DWG. #
L21.15x15
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3) termination
finish. These products do contain Pb but they are RoHS compliant by EU exemption 5 (Pb in glass of cathode ray tubes, electronic components and
fluorescent tubes). These Intersil RoHS compliant products are compatible with both SnPb and Pb-free soldering operations. These Intersil RoHS
compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ZL9101M. For more information on MSL please see techbrief TB363.
3
FN7669.1
January 26, 2011
ZL9101M
Table of Contents
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Derating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Soft-start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Adaptive Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
I2C/SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
I2C/SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Phase Adding/Dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Monitoring via I2C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Non-Volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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January 26, 2011
ZL9101M
Absolute Maximum Ratings (Note 4)
Thermal Information
DC Supply Voltage for VDD Pin . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15.7V
Input Voltage for VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15.7V
MOSFET Drive Reference for VR Pin . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
2.5V Logic Reference for V25 Pin. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V
MOSFET Driver Power for VDRV Pin . . . . . . . . . . . . . . . . . . . . . .-0.3V to 7.5V
Logic I/O Voltage for DDC, EN,
FB+, FB-, PG, SA, SCL, SDA,SYNC, VSET Pins . . . . . . . . . . . . . . . -0.3V to 6V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . 1000V
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 7, 8) . . . . . . . . . . . . . .
11.5
2.2
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Input Supply Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . 5V to 13.2V
Input Supply For Controller, VDD (Note 5) . . . . . . . . . . . . . . . . . 5V to 13.2V
Driver Supply Voltage, VDRV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 6.5V
Output Voltage Range, VOUT (Note 6). . . . . . . . . . . . . . . . . . . . . 0.54V to 4V
Output Current Range, IOUT(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 15A
Operating Junction Temperature Range, TJ . . . . . . . . . . . . . . . . . . . -40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Voltage measured with respect to SGND
5. VIN supplies the power FETs. VDD supplies the controller. VIN can be tied to VDD. For VDD ≤ 5.5V, VDD should be tied to VR.
6. Includes ±10% margin limits.
7. θJA is simulated in free air with device mounted on a four-layer FR-4 test board (76.2 x 114.3 x 1.6mm) with 80%-coverage, 2-ounce Cu on top and
bottom layers, plus two, buried, one-ounce Cu layers with coverage across the entire test board area. Multiple vias were used, with via
diameter = 0.3mm on 1.2mm pitch.
8. For θJC, the “case” temperature is measured at the center of the package underside.
Electrical Specifications VDD = 12 V, TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C. Boldface limits apply
over the operating temperature range, -40°C to +85°C.
PARAMETER
CONDITIONS
MIN
(Note 9)
TYP
(Note 10)
MAX
(Note 9)
UNIT
INPUT AND SUPPLY CHARACTERISTICS
Input Bias Supply Current, IDD
fSW = 615kHz, No load
–
20
40
mA
Input Bias Shutdown Current, IDDS
EN = 0 V
No I2C/SMBus activity
–
9.5
12
mA
Input Supply Current, IVIN
VIN = 13.2V, IOUT = 15A, VOUT = 1.2V
–
1.5
2
A
Driver Supply Current, IVDRV
Not switching
–
190
220
µA
VR Reference Output Voltage (Note 11)
VDD > 6V, IVR < 20mA
4.5
5.2
5.7
V
V25 Reference Output Voltage (Note 11)
VR > 3V, IV25 < 20mA
2.25
2.5
2.75
V
OUTPUT CHARACTERISTICS
Line Regulation Accuracy, ΔVOUT/ΔVIN
(Note 12)
VOUT = 1.2V, IOUT = 0A, VIN = 5V to 13.2V
–
0.5
–
%
Load Regulation Accuracy, ΔVOUT/ΔIOUT
(Note 12)
IOUT = 0A to 12A, VOUT = 1.2V
–
0.5
–
%
Peak-to-peak Output Ripple Voltage, ΔVOUT
(Note 12)
IOUT = 12A, VOUT = 1.2V, COUT = 3000µF
–
6
–
mV
Soft-start Delay Duration Range (Notes 11, 13)
Set using I2C/SMBus
2
–
200
ms
Soft-start Delay Duration Accuracy (Note 11)
Turn-on delay (precise mode) (Notes 13, 14)
–
±0.25
-
ms
Turn-on delay (normal mode) (Note 15)
–
-0.25/+4
-
ms
Turn-off delay (Note 15)
–
-0.25/+4
-
ms
Set using I2C
0
–
200
ms
Soft-start Ramp Duration Range (Note 11)
5
FN7669.1
January 26, 2011
ZL9101M
Electrical Specifications VDD = 12 V, TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C. Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
CONDITIONS
Soft-start Ramp Duration Accuracy (Note 11)
MIN
(Note 9)
TYP
(Note 10)
MAX
(Note 9)
UNIT
–
100
–
µs
DYNAMIC CHARACTERISTICS
Voltage Change for Positive Load Step
ΔIOUT = 6A, slew rate = 2.5A/μs,
VOUT = 1.2V, COUT = 3000µF
–
3
–
%
Voltage Change for Negative Load Step
ΔIOUT = 6A, slew rate = 2.5A/μs,
VOUT = 1.2V, COUT = 3000µF
–
3
–
%
590
615
630
kHz
95
–
–
%
150
–
–
ns
External clock source
-13
–
13
%
EN, PG, SCL, SDA pins
-10
–
10
µA
Logic Input Low, VIL
–
–
0.8
V
Logic Input High, VIH
2.0
–
–
V
OSCILLATOR AND SWITCHING CHARACTERISTICS (Note 11)
Switching Frequency Range
Maximum PWM Duty Cycle
Factory setting
Minimum SYNC Pulse Width
Input clock Frequency Drift Tolerance
LOGIC INPUT/OUTPUT CHARACTERISTICS (Note 11)
Logic Input Bias Current
Logic Output Low, VOL
IOL ≤ 4mA (Note 17)
–
–
0.4
V
Logic Output High, VOH
IOH ≥ -2mA (Note 17)
2.25
–
–
V
Configurable via I2C/SMBus
2.85
–
16
V
-150
–
150
mV
Factory setting
–
3
–
%
Configurable via I2C/SMBus
0
–
100
%
–
–
2.5
µs
FAULT PROTECTION CHARACTERISTICS (Note 11)
UVLO Threshold Range
UVLO Set-point Accuracy
UVLO Hysteresis
UVLO Delay
Power Good VOUT Threshold
Factory setting
–
90
–
% VOUT
Power Good VOUT Hysteresis
Factory setting
–
5
–
%
Power Good Delay (Note 16)
Configurable via I2C/SMBus
0
–
200
ms
VSEN Undervoltage Threshold
Factory setting
–
85
–
% VOUT
Configurable via I2C/SMBus
0
–
110
% VOUT
Factory setting
–
115
–
% VOUT
Configurable via I2C/SMBus
0
–
115
% VOUT
–
5
–
% VOUT
Factory setting
–
16
–
µs
Configurable via I2C/SMBus
5
–
60
µs
VSEN Overvoltage Threshold
VSEN Undervoltage Hysteresis
VSEN Undervoltage/Overvoltage Fault Response
Time
6
FN7669.1
January 26, 2011
ZL9101M
Electrical Specifications VDD = 12 V, TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C. Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
CONDITIONS
Thermal Protection Threshold
(Controller Junction Temperature)
MIN
(Note 9)
TYP
(Note 10)
Factory setting
Configurable via I2C/SMBus
Thermal Protection Hysteresis
MAX
(Note 9)
UNIT
–
125
–
°C
-40
–
125
°C
–
15
–
°C
NOTES:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10. Parameters with TYP limits are not production tested unless otherwise specified.
11. Parameters are 100% tested for internal controller prior to module assembly.
12. VOUT measured at the termination of the FB+ and FB- sense points.
13. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to
approximately 2ms, where in normal mode it may vary up to 4ms.
14. Precise ramp timing mode is only valid when using the EN pin to enable the device rather than PMBus enable.
15. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable
signal.
16. Factory setting for Power Good delay is set to the same value as the soft-start ramp time.
17. Nominal capacitance of logic pins is 5pF.
Typical Performance Curves
100
90
85
VOUT = 1.8V
80
VOUT = 1.2V
75
70
VIN = 6V
65
60
2
4
6
8
10
OUTPUT CURRENT (A)
12
14
85
VOUT = 1.8V
80
VOUT = 1.2V
75
70
60
16
VIN = 9V
fSW = 615kHz
0
2
FIGURE 2. EFFICIENCY, VIN = 6V
35
EFFICIENCY (%)
90
VOLTAGE DEVIATION (mV)
VOUT = 3.3V
VOUT = 2.5V
85
80
VOUT = 1.8V
VOUT = 1.2V
75
70
VIN = 12V
65
60
fSW = 615kHz
0
2
4
6
8
10
OUTPUT CURRENT (A)
12
FIGURE 4. EFFICIENCY, VIN = 12V
7
4
6
8
10
OUTPUT CURRENT (A)
12
14
16
FIGURE 3. EFFICIENCY, VIN = 9V
100
95
VOUT = 2.5V
90
65
fSW = 615kHz
0
VOUT = 3.3V
95
VOUT = 2.5V
EFFICIENCY (%)
EFFICIENCY (%)
100
VOUT = 3.3V
95
14
16
VIN = 12V
VOUT = 1.2V
IOUT STEP = 12A to 6A
30
25
SLEW 2.5A/µs
20
15
10
5
0
-5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
FIGURE 5. DYNAMIC RESPONSE, UNLOADING
FN7669.1
January 26, 2011
ZL9101M
Typical Performance Curves (Continued)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.4
1.0
VIN = 12V
0
1.0
VOUT = 1.2V
-5
0.8
tRISE = 5ms
VOUT (V)
VOLTAGE DEVIATION (mV)
0
1.2
5
-10
-15
VIN = 12V
-20 V
OUT = 1.2V
-25 IOUT STEP = 6A to 12A
SLEW 2.5A/µs
-30
0.6
0.4
0.2
0
-0.2
0
1
2
3
4
5
6
TIME (ms)
7
8
9
10
FIGURE 7. SOFT-START RAMP-UP
FIGURE 6. DYNAMIC RESPONSE, LOADING
1.4
VIN = 12V
VOUT (V)
1.2
1.0
VOUT = 1.2V
0.8
tFALL = 5ms
0.6
0.4
0.2
0
-0.2
0
1
2
3
4
5
6
TIME (ms)
7
8
9
10
FIGURE 8. RAMP-DOWN
Derating Curves
16
MAX. LOAD CURRENT (A)
MAX. LOAD CURRENT (A)
16
14
12
10
3.3VOUT
8
6
1.0VOUT
4
2
0
50
60
70
80
90
100
110
AMBIENT TEMPERATURE (°C)
FIGURE 9A. DERATING CURVE, 5VIN
8
120
130
14
12
10
8
3.3VOUT
2.5VOUT
6
4
1.8VOUT
2
0
1.0VOUT
50
60
70
80
90
100
110
120
130
AMBIENT TEMPERATURE (°C)
FIGURE 9B. DERATING CURVE, 12VIN
FN7669.1
January 26, 2011
ZL9101M
Functional Description
The output voltage may also be set to any value between 0.6V and 4.0V
using a PMBus command over the I2C/SMBus interface. See
Application Note AN2033 for details.
Output Voltage Selection
The output voltage may be set to a voltage between 0.6V and
4.0V provided that the input voltage is higher than the desired
output voltage by an amount sufficient to prevent the device
from exceeding its maximum duty cycle specification.
The VSET pin is used to set the output voltage to levels as shown
in Table 1. The RSET resistor is placed between the VSET pin and
SGND.
TABLE 1. OUTPUT VOLTAGE RESISTOR SETTINGS
Soft-start Delay and Ramp Times
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to precisely set the time
required for VOUT to ramp to its target value after the delay
period has expired. These features may be used as part of an
overall inrush current management strategy or to precisely
control how fast a load IC is turned on. The ZL9101M gives the
system designer several options for precisely and independently
controlling both the delay and ramp time periods.
VOUT
(V)
RSET
(kΩ)
0.60
10
0.65
11
0.70
12.1
0.75
13.3
0.80
14.7
0.85
16.2
0.90
17.8
0.95
19.6
1.00
21.5
1.05
23.7
1.10
26.1
1.15
28.7
1.20
31.6
1.25
34.8
1.30
38.3
1.40
42.2
1.50
46.4
1.60
51.1
1.70
56.2
1.80
61.9
1.90
68.1
2.00
75
2.10
82.5
2.20
90.9
2.30
100
2.50
110
Loop Compensation
2.80
121
3.00
133
3.30
147
The ZL9101M operates as a voltage-mode synchronous buck
controller with a fixed frequency PWM scheme. The module is
internally compensated via the I2C/SMBus interface. Please
refer to Application Note AN2033 for further details.
4.00
162
9
The soft-start delay period begins when the EN pin is asserted
and ends when the delay time expires.
The soft-start delay and ramp times are set to custom values via the
I2C/SMBus interface. When the delay time is set to 0ms, the device will
begin its ramp-up after the internal circuitry has initialized
(approximately 2ms). When the soft-start ramp period is set to 0ms, the
output will ramp up as quickly as the output load capacitance and loop
settings will allow. It is generally recommended to set the soft-start
ramp to a value greater than 500µs to prevent inadvertent fault
conditions due to excessive inrush current.
Power Good
The ZL9101M provides a Power Good (PG) signal that indicates
the output voltage is within a specified tolerance of its target
level and no fault condition exists. By default, the PG pin will
assert if the output is within 10% of the target voltage. These
limits and the polarity of the pin may be changed via the
I2C/SMBus interface. See Application Note AN2033 for details.
A PG delay period is defined as the time from when all conditions
within the ZL9101M for asserting PG are met to when the PG pin
is actually asserted. This feature is commonly used instead of
using an external reset controller to control external digital logic.
By default, the ZL9101M PG delay is set equal to the soft-start
ramp time setting. Therefore, if the soft-start ramp time is set to
10ms, the PG delay will be set to 10ms. The PG delay may be set
independently of the soft-start ramp using the I2C/SMBus as
described in Application Note AN2033.
Switching Frequency and PLL
The ZL9101M incorporates an internal phase-locked loop (PLL) to
clock the internal circuitry. The PLL can be driven by an external
clock source connected to the SYNC pin. When using the internal
oscillator, the SYNC pin can be configured as a clock source.
The internal switching frequency of the ZL9101M is 615kHz.
FN7669.1
January 26, 2011
ZL9101M
Adaptive Diode Emulation
Adaptive diode emulation mode turns off the low-side FET gate
drive at low load currents to prevent the inductor current from
going negative, reducing the energy losses and increasing overall
efficiency. Diode emulation is available to single-phase devices
only.
Note: the overall bandwidth of the device may be reduced when
in diode emulation mode. It is recommended that diode
emulation is disabled prior to applying significant load steps.
Input Undervoltage Lockout
The input undervoltage lockout (UVLO) prevents the ZL9101M
from operating when the input falls below a preset threshold,
indicating the input supply is out of its specified range. The UVLO
threshold (VUVLO) can be set between 2.85V and 16V using the
I2C/SMBus interface.
Once an input undervoltage fault condition occurs, the device
can respond in a number of ways as follows:
1. Continue operating without interruption.
2. Continue operating for a given delay period, followed by
shutdown if the fault still exists. The device will remain in
shutdown until instructed to restart.
Please refer to Application Note AN2033 for details on how to
select specific overvoltage fault response options via I2C/SMBus.
Output Pre-Bias Protection
An output pre-bias condition exists when an externally applied
voltage is present on a power supply’s output before the power
supply’s control IC is enabled. Certain applications require that
the converter not be allowed to sink current during start up if a
pre-bias condition exists at the output. The ZL9101M provides
pre-bias protection by sampling the output voltage prior to
initiating an output ramp.
If a pre-bias voltage lower than the target voltage exists after the
pre-configured delay period has expired, the target voltage is set
to match the existing pre-bias voltage and both drivers are
enabled. The output voltage is then ramped to the final
regulation value at the preconfigured ramp rate.
The actual time the output will take to ramp from the pre-bias
voltage to the target voltage will vary depending on the pre-bias
voltage but the total time elapsed from when the delay period
expires and when the output reaches its target value will match
the pre-configured ramp time. See Figure 10.
3. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
The default response from a UVLO fault is an immediate
shutdown of the module. The controller will continuously check
for the presence of the fault condition. If the fault condition is no
longer present, the ZL9101M will be re-enabled.
Please refer to Application Note AN2033 for details on how to
configure the UVLO threshold or to select specific UVLO fault
response options via the I2C/SMBus interface.
Output Overvoltage Protection
The ZL9101M offers an internal output overvoltage protection circuit
that can be used to protect sensitive load circuitry from being subjected
to a voltage higher than its prescribed limits. A hardware comparator is
used to compare the actual output voltage (seen at the FB+ pin) to a
threshold set to 15% higher than the target output voltage (the default
setting). If the FB+ voltage exceeds this threshold, the PG pin will
de-assert and the controller can then respond in a number of ways as
follows:
1. Initiate an immediate shutdown until the fault has been
cleared. The user can select a specific number of retry
attempts.
2. Turn off the high-side MOSFET and turn on the low-side
MOSFET. The low-side MOSFET remains ON until the device
attempts a restart.
The default response from an overvoltage fault is to immediately
shut down. The controller will continuously check for the
presence of the fault condition, and when the fault condition no
longer exists the device will be re-enabled.
For continuous overvoltage protection when operating from an
external clock, the only allowed response is an immediate
shutdown.
10
FIGURE 10. OUTPUT RESPONSES TO PRE-BIAS VOLTAGES
If a pre-bias voltage higher than the target voltage exists after the
pre-configured delay period has expired, the target voltage is set
to match the existing pre-bias voltage and both drivers are
enabled with a PWM duty cycle that would ideally create the
pre-bias voltage.
Once the pre-configured soft-start ramp period has expired, the
PG pin will be asserted (assuming the pre-bias voltage is not
higher than the overvoltage limit). The PWM will then adjust its
FN7669.1
January 26, 2011
ZL9101M
duty cycle to match the original target voltage and the output will
ramp down to the preconfigured output voltage.
If a pre-bias voltage higher than the overvoltage limit exists, the
device will not initiate a turn-on sequence and will declare an
overvoltage fault condition to exist. In this case, the device will
respond based on the output overvoltage fault response method
that has been selected. See “Output Overvoltage Protection” on
page 10 for response options due to an overvoltage condition.
Note that pre-bias protection is not offered for current sharing
groups that also have tracking enabled.
Output Overcurrent Protection
The ZL9101M can protect the power supply from damage if the
output is shorted to ground or if an overload condition is imposed
on the output. The following overcurrent protection response
options are available:
1. Initiate a shutdown and attempt to restart an infinite number
of times with a preset delay period between attempts.
2. Initiate a shutdown and attempt to restart a preset number of
times with a preset delay period between attempts.
3. Continue operating for a given delay period, followed by
shutdown if the fault still exists.
4. Continue operating through the fault (this could result in
permanent damage to the power supply).
5. Initiate an immediate shutdown.
The default response from an overcurrent fault is an immediate
shutdown of the controller. The controller will continuously check
for the presence of the fault condition, and if the fault condition
no longer exists the device will be re-enabled.
Please refer to Application Note AN2033 for details on how to
select specific overcurrent fault response options via I2C/SMBus.
Thermal Overload Protection
The ZL9101M includes a thermal sensor that continuously
measures the internal temperature of the module and shuts
down the controller when the temperature exceeds the preset
limit. The default temperature limit is set to +125°C in the
factory, but the user may set the limit to a different value if
desired. See Application Note AN2033 for details. Note that
setting a higher thermal limit via the I2C/SMBus interface may
result in permanent damage to the controller. Once the module
has been disabled due to an internal temperature fault, the user
may select one of several fault response options as follows:
1. Initiate a shutdown and attempt to restart an infinite number
of times with a preset delay period between attempts.
2. Initiate a shutdown and attempt to restart a preset number of
times with a preset delay period between attempts.
3. Continue operating for a given delay period, followed by
shutdown if the fault still exists.
4. Continue operating through the fault (this could result in
permanent damage to the power supply).
5. Initiate an immediate shutdown.
If the user has configured the module to restart, the controller
will wait the preset delay period (if configured to do so) and will
then check the module temperature. If the temperature has
11
dropped below a threshold that is approximately +15 °C lower
than the selected temperature fault limit, the controller will
attempt to re-start. If the temperature still exceeds the fault limit
the controller will wait the preset delay period and retry again.
The default response from a temperature fault is an immediate
shutdown of the module. The controller will continuously check
for the fault condition, and once the fault has cleared the
ZL9101M will be re-enabled.
Please refer to Application Note AN2033 for details on how to
select specific temperature fault response options via
I2C/SMBus.
I2C/SMBus Communications
The ZL9101M provides an I2C/SMBus digital interface that
enables the user to configure all aspects of the module operation
as well as monitor the input and output parameters. The
ZL9101M can be used with any I2C host device. In addition, the
module is compatible with SMBus version 2.0. Pull-up resistors
are required on the I2C/SMBus as specified in the SMBus 2.0
specification. The ZL9101M accepts most standard PMBus
commands. When controlling the device with PMBus commands,
it is recommended that the enable pin is tied to SGND.
I2C/SMBus Module Address Selection
Each module must have its own unique serial address to
distinguish between other devices on the bus. The module
address is set by connecting a resistor between the SA pin and
SGND. Table 2 lists the available module addresses.
TABLE 2. SMBus ADDRESS RESISTOR SELECTION
RSA0
SMBus Address
10
0x19
11
0x1A
12.1
0x1B
13.3
0x1C
14.7
0x1D
16.2
0x1E
17.8
0x1F
19.6
0x20
21.5
0x21
23.7
0x22
26.1
0x23
28.7
0x24
31.6
0x25
34.8
0x26
38.3
0x27
42.2
0x28
46.4
0x29
51.1
0x2A
56.2
0x2B
FN7669.1
January 26, 2011
ZL9101M
TABLE 2. SMBus ADDRESS RESISTOR SELECTION (Continued)
RSA0
SMBus Address
61.9
0x2C
68.1
0x2D
75
0x2E
82.5
0x2F
90.9
0x30
100
0x31
Multiple device sequencing is configured by issuing PMBus
commands to assign the preceding device in the sequencing
chain as well as the device that will follow in the sequencing
chain.
The Enable pins of all devices in a sequencing group must be tied
together and driven high to initiate a sequenced turn-on of the
group. Enable must be driven low to initiate a sequenced turnoff
of the group.
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to
communicate between Zilker Labs Digital-DC modules and
devices. This dedicated bus provides the communication channel
between devices for features such as sequencing, fault
spreading, and current sharing. The DDC pin on all Digital-DC
devices in an application should be connected together. A pull-up
resistor is required on the DDC bus in order to guarantee the rise
time as follows:
Rise Time = R PU∗ C LOAD ≈ 1μs
(EQ. 1)
where RPU is the DDC bus pull-up resistance and CLOAD is the
bus loading. The pull-up resistor may be tied to an external 3.3V
or 5V supply as long as this voltage is present prior to or during
device power-up. As rules of thumb, each device connected to the
DDC bus presents approximately 10pF of capacitive loading, and
each inch of FR4 PCB trace introduces approximately 2pF. The
ideal design will use a central pull-up resistor that is wellmatched to the total load capacitance. The minimum pull-up
resistance should be limited to a value that enables any device to
assert the bus to a voltage that will ensure a logic 0 (typically
0.8V at the device monitoring point) given the pull-up voltage and
the pull-down current capability of the ZL9101M (nominally
4mA).
Phase Spreading
When multiple point of load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time can dramatically reduce input
capacitance requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively spread out over
a period of time, the peak current drawn at any given moment is
reduced and the power losses proportional to the IRMS2 are
reduced dramatically.
In order to enable phase spreading, all converters must be
synchronized to the same switching clock.
The phase offset of each device may also be set to any value
between 0° and 360° in 22.5° increments via the I2C/SMBus
interface. Refer to Application Note AN2033 for further details.
Output Sequencing
A group of Digital-DC modules or devices may be configured to power
up in a predetermined sequence. This feature is especially useful when
12
powering advanced processors, FPGAs, and ASICs that require one
supply to reach its operating voltage prior to another supply reaching its
operating voltage in order to avoid latch-up from occurring. Multi-device
sequencing can be achieved by configuring each device through the
I2C/SMBus interface.
Refer to Application Note AN2033 for details on sequencing via
the I2C/SMBus interface.
Fault Spreading
Digital DC modules and devices can be configured to broadcast a fault
event over the DDC bus to the other devices in the group. When a nondestructive fault occurs and the device is configured to shut down on a
fault, the device will shut down and broadcast the fault event over the
DDC bus. The other devices on the DDC bus will shut down together if
configured to do so, and will attempt to re-start in their prescribed order
if configured to do so.
Active Current Sharing
Paralleling multiple ZL9101M modules can be used to increase
the output current capability of a single power rail. By connecting
the DDC pins of each module together and configuring the
modules as a current sharing rail, the units will share the current
equally within a few percent.
Figure 11 illustrates a typical connection for two modules.
VIN
3.3V - 5V
CIN
DDC
ZL
COUT
CIN
DDC
ZL
VOUT
COUT
FIGURE 11. CURRENT SHARING GROUP
The ZL9101M uses a low-bandwidth, first-order digital current
sharing technique to balance the unequal module output loading
by aligning the load lines of member modules to a reference
module.
Droop resistance is used to add artificial resistance in the output
voltage path to control the slope of the load line curve,
FN7669.1
January 26, 2011
ZL9101M
calibrating out the physical parasitic mismatches due to power
train components and PCB layout.
Upon system start-up, the module with the lowest member position as
selected in ISHARE_CONFIG is defined as the reference module. The
remaining modules are members. The reference module broadcasts its
current over the DDC bus. The members use the reference current
information to trim their voltages (VMEMBER) to balance the current
loading of each module in the system.
operational. During periods of light loading, it may be beneficial
to disable one or more phases in order to eliminate the current
drain and switching losses associated with those phases,
resulting in higher efficiency.
The ZL9101M offers the ability to add and drop phases using a
PMBus command in response to an observed load current
change. All phases in a current share rail are considered active
prior to the current sharing rail ramp to power-good.
Any member of the current sharing rail can be dropped. If the
reference module is dropped, the remaining active module with
the lowest member position will become the new reference.
VREFERENCE
Additionally, any change to the number of members of a current
sharing rail will precipitate autonomous phase distribution within
the rail where all active phases realign their phase position
based on their order within the number of active members.
VOUT
-R
VMEMBER
-R
If the members of a current sharing rail are forced to shut down
due to an observed fault, all members of the rail will attempt to
re-start simultaneously after the fault has cleared.
Monitoring via I2C/SMBus
I MEMBER
I OUT
I REFERENCE
A system controller can monitor a wide variety of different
ZL9101M system parameters through the I2C/SMBus interface.
FIGURE 12. ACTIVE CURRENT SHARING
Figure 12 shows that, for load lines with identical slopes, the
member voltage is increased towards the reference voltage
which closes the gap between the inductor currents.
The module can monitor for any number of power conversion
parameters including but not limited to the following:
The relation between reference and member current and voltage
is given by the following equation:
• Output current
VMEMBER = VOUT + R × (I REFERENCE − I MEMBER )
(EQ. 2)
The ISHARE_CONFIG command is used to configure the module
for active current sharing. The default setting is a stand-alone
non-current sharing module. A current sharing rail can be part of
a system sequencing group.
For fault configuration, the current share rail is configured in a
quasi-redundant mode. In this mode, when a member module
fails, the remaining members will continue to operate and
attempt to maintain regulation. Of the remaining modules, the
module with the lowest member position will become the
reference. If fault spreading is enabled, the current share rail
failure is not broadcast until the entire current share rail fails.
The phase offset of (multi-phase) current sharing modules is
automatically set to a value between 0° and 337.5° in 22.5°
increments as follows:
(EQ. 3)
Please refer to Application Note AN2034 for additional details on
current sharing.
Phase Adding/Dropping
The ZL9101M allows multiple power converters to be connected
in parallel to supply higher load currents than can be addressed
using a single-phase design. In doing so, the power converter is
optimized at a load current range that requires all phases to be
13
• Internal temperature
• Switching frequency
where R is the value of the droop resistance.
Phase Offset = SMBus Address [ 4:0 ] – Current
Share Position∗ 22.5 °
• Input voltage/Output voltage
• Duty cycle
Please refer to Application Note AN2033 for details on how to
monitor specific parameters via the I2C/SMBus interface.
Snapshot Parameter Capture
The ZL9101M offers a special feature that enables the user to
capture parametric data during normal operation or following a
fault. The Snapshot functionality is enabled by setting bit 1 of
MISC_CONFIG to 1.
See AN2033 for details on using SnapShot in addition to the
parameters supported. The Snapshot feature enables the user to
read parameters via a block read transfer through the SMBus.
This can be done during normal operation, although it should be
noted that reading the 22 bytes will occupy the SMBus for some
time.
The SNAPSHOT_CONTROL command enables the user to store
the snapshot parameters to Flash memory in response to a
pending fault as well as to read the stored data from Flash
memory after a fault has occurred. Table 3 describes the usage
of this command. Automatic writes to Flash memory following a
fault are triggered when any fault threshold level is exceeded,
provided that the specific fault’s response is to shut down
(writing to Flash memory is not allowed if the device is configured
to re-try following the specific fault condition). It should also be
noted that the module’s VDD voltage must be maintained during
the time when the controller is writing the data to Flash memory;
FN7669.1
January 26, 2011
ZL9101M
a process that requires between 700µs to 1400µs depending on
whether the data is set up for a block write. Undesirable results
may be observed if the device’s VDD supply drops below 3.0V
during this process.
TABLE 3. SNAPSHOT_CONTROL COMMAND
DATA
VALUE
DESCRIPTION
1
Copies current SNAPSHOT values from Flash memory to
RAM for immediate access using SNAPSHOT command.
2
Writes current SNAPSHOT values to Flash memory. Only
available when device is disabled.
In the event that the module experiences a fault and power is
lost, the user can extract the last SNAPSHOT parameters stored
during the fault by writing a 1 to SNAPSHOT_CONTROL (transfers
data from Flash memory to RAM) and then issuing a SNAPSHOT
command (reads data from RAM via SMBus).
Non-Volatile Memory and Device Security
Features
The ZL9101M has internal non-volatile memory where user
configurations are stored. Integrated security measures ensure
that the user can only restore the module to a level that has been
made available to them.
During the initialization process, the ZL9101M checks for stored
values contained in its internal non-volatile memory. The
ZL9101M offers two internal memory storage units that are
accessible by the user as follows:
1. Default Store: The ZL9101M has a default configuration that
is stored in the Default Store in the controller. The module can
be restored to its default settings by issuing a
RESTORE_DEFAULT_ALL command over the SMBus.
2. User Store: The user can modify certain power supply settings
as described in this data sheet. The user would use the User
Store to store their configuration.
Please refer to Application Note AN2033 for details on how to set
specific security measures via the I2C/SMBus interface.
14
FN7669.1
January 26, 2011
ZL9101M
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
1/20/2011
FN7669.1
On page 5 Electrical Spec Table under Input and Supply Characteristic - Parameter “Input Supply Current, IVIN”
conditions column changed from “VIN = 14V, IOUT = 15A, VOUT = 1.2V” to “VIN = 13.2V, IOUT = 15A, VOUT = 1.2V.
Under Output Characteristics - Parameter “Line Regulation Accuracy” conditions column changed from
“VOUT = 1.2V, IOUT = 0A, VIN = 5V to 14V” to “VOUT = 1.2V, IOUT = 0A, VIN = 5V to 13.2V”.
1/11/2011
12/20/2010
On page 1, under Features, changed "Tracking" to "Output Voltage Tracking"
On page 1, Figure 1, added footnote 4. "The VR, V25, VDRV, and VDD capacitors should be placed no further
than 0.5 cm from the pin."
On page 5, under “Absolute Maximum Ratings”, changed value: DC Supply Voltage for VDD Pin from 16V to
15.7V
On page 5, under “Absolute Maximum Ratings”, changed value: Input Voltage for VIN Pin from 16V to 15.7V
On page 5, under Recommended Operating Conditions, changed value: Input Supply Voltage Range, Vin from
14V to 13.2V
On page 5, under Recommended Operating Conditions, changed value: Input Supply For Controller, VDD from
14V to 13.2V
On page 7, Note 11, changed "... for internal IC prior ..." to "... for internal controller prior ..."
On page 8, Figure 7, changed title from “Ramp-up” to "Soft-start Ramp-up"
On page 8, Figure 9A, changed labels to from V to VOUT (e.g. 3.3VOUT, 1.0VOUT)
On page 8, Figure 9B, changed labels to from V to VOUT (e.g. 3.3VOUT, 1.0VOUT)
FN7669.0
Initial release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ZL9101M
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
15
FN7669.1
January 26, 2011
Package Outline Drawing
L21.15x15
21 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN)
Rev 0, 10/10
X4
0.2 S AB
A
17x 0.80
18
17
8.3
3.1
16
2.95
101112
13 14 15
4.2
14
0.8
15
4.65
5.65
13
17x 0.75
9
33x 0.5
B
0.05
12 11 10
S AB
8x 1.8±0.05
15.0±0.2
15.8±0.2
TOP VIEW
2
3
4
5
6
7
8
BOTTOM VIEW
A
A A A
A A A
S 0.2
SIDE VIEW
0.50
S 0.05
18
17
16
14
FN7669.1
January 26, 2011
15
B
19 20 21 1
2
3
4
5
6
7
8
A A A A A A
3.5±0.2
S
B
ND
B
AROU
A A A A A A A A
5 ° A LL
9
13
A A A
12 11 10
B C C
B
A:1.3 ±0.1
B:2.6 ±0.1
C:1.13 ±0.1
ZL9101M
9
16
9x 1.9±0.05
19 20 21 1
6.3
1.3
2.0
12.05
4.40
17
15.0±0.2
2
3
4
5
6
7
8
2.95
18
1.95
1 21 20 19
15.8±0.2
16
7.25
PIN 1
INDEX AREA
6.9
6.3
5.6
5.0
4.3
3.7
3.0
2.4
0.6
0.0
0.0
0.9
1.5
2.2
2.8
3.5
4.1
6.8
8.2
6.9
8.3
0.1
0.6
4.2
7.0
6.2
5.7
4.9
4.4
3.6
3.1
2.3
0.7
0.0
8.3
6.9
5.6
5.0
4.2
1 21
2
1.1
0.3
0.0
6.1
5.5
4.9
4.2
3.6
2.9
2.3
1.6
1.0
0.3
0.0
0.3
1.0
1.6
2.3
2.9
4.9
5.5
6.1
1 21
2
6.2
5.4
4.8
4.1
3.5
2.9
2.3
0.6
0.0
0.7
1.3
2.3
2.8
3.5
4.1
6.1
6.7
8.2
STENCIL PATTERN WITH SQUARE PADS-1
6.5
3.4
4.0
TYPICAL RECOMMENDED LAND PATTERN
0.0
0.9
8.2
6.8
5.5
5.1
4.0
3.6
2.9
2.3
1.6
1.2
0.1
0.0
0.3
1.0
1.6
2.3
2.9
3.6
4.0
5.1
5.5
6.8
8.2
6.4
5.3
3.9
1 21
2
1.4
0.8
0.0
0.05
1.6
2.2
3.8
5.1
6.4
FN7669.1
January 26, 2011
0.0
0.7
2.4
2.5
3.0
4.2
4.5
4.8
5.8
6.3
6.5
0.0
1.2
1.8
3.8
4.4
5.8
STENCIL PATTERN WITH SQUARE PADS-2
NOTES:
1.
Dimensions are in millimeters.
2.
Unless otherwise specified, tolerance : Decimal ± 0.2;
Body Tolerance ±0.2mm
3.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
ZL9101M
8.3
4.1
4.9
5.6
8.3
8.3
6.1
5.5
4.7
4.2
3.4
3.0
2.2
0.7
0.0
0.1
0.6
1.4
2.2
4.8
5.6
6.9
17
6.0
5.6
4.8
4.3
3.5
3.0
2.2
1.7
0.9
0.4
0.0
0.4
0.9
1.7
2.2
3.0
4.8
5.6
6.0