General Description These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active-high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Features n Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode n Flow-through architecture optimizes PCB layout n Guaranteed latch-up protection n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9687001 Ordering Code Military Package Package Description Number 54ABT16500W-QML WA56A 56-Lead Cerpack 54ABT16500 54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE ® Outputs 54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE Outputs July 1998 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 1 www.national.com DS100225 cmserv Proof 1 Connection Diagram Pin Assignment for Cerpack DS100225-1 Function Table (Note 1) Inputs OEAB LEAB CLKAB A Output B Z L X X X H H X L L H H X H H H L ↓ L L H L ↓ H H H L H X B0 (Note 2) H L L X B0 (Note 3) Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2: Output level before the indicated steady-state input conditions were established. Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low. www.national.com 2 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof 2 Logic Diagram DS100225-2 3 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 www.national.com cmserv Proof 3 Absolute Maximum Ratings (Note 4) Over Voltage Latchup (I/O) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 4) Input Current (Note 4) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current −65˚C to +150˚C −55˚C to +125˚C Recommended Operating Conditions −55˚C to +175˚C Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −0.5V to 5.5V −0.5V to VCC 10V −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) −500 mA DC Electrical Characteristics Symbol Parameter ABT16500 Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage Typ Units 2.0 VOL Output LOW Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test IIL Input LOW Current VCC Conditions Max V Recognized HIGH Signal 0.8 V −1.2 V Min Recognized LOW Signal IIN = −18 mA 54ABT 2.5 V Min IOH = −3 mA 54ABT 2.0 V Min IOH = −24 mA 54ABT 0.55 V Min IOL = 48 mA 5 µA Max VIN = 2.7V (Note 6) 7 µA Max VIN = 7.0V −5 µA Max VIN = 0.5V (Note 6) V 0.0 IID = 1.9 µA VIN = VCC 5 VIN = 0.0V −5 VID Input Leakage Test 4.75 IIH + Output Leakage Current 50 µA 0 − 5.5V VOUT = 2.7V; OE, OE = 2.0V Output Leakage Current −50 µA 0 − 5.5V VOUT = 0.5V; OE, OE = 2.0V All Other Pins Grounded IOZH IIL + IOZL IOS Output Short-Circuit Current −275 mA Max VOUT = 0V ICEX Output High Leakage Current 50 µA Max VOUT = VCC VOUT = 5.5V; All Others GND −100 IZZ Bus Drainage Test 100 µA 0.0 ICCH Power Supply Current 1.0 mA Max All Outputs HIGH ICCL Power Supply Current 68 µA Max An or Bn Outputs Low ICCZ Power Supply Current 1.0 mA Max OEn = VCC, All Others at VCC or GND ICCT Additional ICC/Input 2.5 mA Max VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 6) 0.23 Max MHz Outputs Open Transparent Mode One Bit Toggling, 50% Duty Cycle Note 6: Guaranteed, but not tested. www.national.com 4 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof 4 DC Electrical Characteristics Symbol Parameter Min Max Units VCC VOLP Quiet Output Maximum Dynamic VOL 1.1 V 5.0 Conditions CL = 50 pF; RL = 500Ω TA = 25˚C (Note 7) VOLV Quiet Output Minimum Dynamic VOL -1.7 V 5.0 TA = 25˚C (Note 7) Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V Units Fig. No. CL = 50 pF Min Max fmax Maximum Clock Frequency 150 tPLH Propagation Delay 1.0 6.5 tPHL A or B to B or A 1.0 7.0 tPLH Propagation Delay 1.0 7.0 tPHL LEAB or LEBA to B or A 1.0 7.8 tPLH Propagation Delay 1.0 7.5 tPHL CLKAB or CLKBA to B or A 1.0 8.0 tPZH Propagation Delay 1.0 6.3 tPZL OEAB or OEBA to B or A 1.0 6.5 tPHZ Propagation Delay 1.0 7.2 tPLZ OEAB or OEBA to B or A 1.0 6.8 MHz ns Figure 4 ns Figure 4 ns Figure 4 ns Figure 6 ns Figure 6 Units Fig. No. ns Figure 7 ns Figure 7 ns Figure 7 ns Figure 7 ns Figure 7 AC Operating Requirements Symbol Parameter 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V CL = 50 pF Min ts(H) Setup Time, 4.5 ts(L) A to CLKAB 4.5 th(H) Hold Time, 0 th(L) A to CLKAB 0 ts(H) Setup Time, 4.0 ts(L) B to CLKBA 4.0 th(H) Hold Time, 0 th(L) B to CLKBA 0 ts(H) Setup Time, A to LEAB 1.5 ts(L) or B to LEBA, CLK High 1.5 th(H) Hold Time, A to LEAB 1.5 th(L) or B to LEBA, CLK High 1.5 ts(H) Setup Time, A to LEAB 4.5 ts(L) or B to LEBA, CLK Low 4.5 th(H) Hold Time, A to LEAB 1.5 th(L) or B to LEBA, CLK Low 1.5 tw(H) Pulse Width, 3.3 tw(L) LEAB or LEBA, High 3.3 Max ns 5 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 Figure 7 ns Figure 7 ns Figure 7 ns Figure 5 www.national.com cmserv Proof 5 AC Operating Requirements Symbol Parameter (Continued) 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V Units Fig. No. ns Figure 5 CL = 50 pF Min tw(H) Pulse Width, CLKAB 3.3 tw(L) or CLKBA, High or Low 3.3 Max Capacitance Typ Units CIN Symbol Input Capacitance Parameter 5.0 pF CI/O (Note 8) Output Capacitance 11.0 pF Conditions, TA = 25˚C VCC = 0.0V VCC = 5.0V Note 8: CI/O is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012. www.national.com 6 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof 6 AC Loading DS100225-4 DS100225-3 FIGURE 5. Propagation Delay, Pulse Width Waveforms *Includes jig and probe capacitance. FIGURE 1. Standard AC Test Load DS100225-6 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times DS100225-5 FIGURE 2. VM = 1.5V Input Pulse Requirements Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS100225-8 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms DS100225-7 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 7 PrintDate=1998/07/14 PrintTime=11:08:56 43605 ds100225 Rev. No. 1 www.national.com cmserv Proof 7 54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE Outputs Physical Dimensions Book Extract End inches (millimeters) unless otherwise noted 56-Lead Cerpack NS Package Number WA56A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com 8 National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. PrintDate=1998/07/14 PrintTime=11:08:56 43605 ds100225 Rev. No. 1 cmserv Proof 8