54FCT373 Octal Transparent Latch with TRI-STATE ® Outputs General Description Features The ’FCT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. n n n n TRI-STATE outputs for bus interfacing TTL input and output level compatible CMOS power consumption Output sink capability of 32 mA, source capability of 12 mA n Standard Microcircuit Drawing (SMD) 5962-8764401 Ordering Code Military Package Number Package Description 54FCT373DMQB J20A 20-Lead Ceramic Dual-In-Line 54FCT373FMQB W20A 20-Lead Cerpack 54FCT373LMQB E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100957-2 DS100957-1 Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 TRI-STATE Latch (Active HIGH) (Active LOW) Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100957 www.national.com 54FCT373 Octal Transparent Latch with TRI-STATE Outputs October 1999 54FCT373 Functional Description Inputs The ’FCT373 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Output LE OE Dn On H L H H H L L L L L X On (no change) X H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance State Logic Diagram DS100957-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 in the HIGH State Current Applied to Output in LOW State (Max) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to VCC twice the rated IOL (mA) Recommended Operating Conditions −65˚C to +150˚C −55˚C to +125˚C Free Air Ambient Temperature Military Supply Voltage Military −55˚C to +175˚C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −55˚C to +125˚C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. −0.5V to +5.5V DC Electrical Characteristics Symbol Parameter FCT240 Min Max Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH Output HIGH Voltage 2.0 VCC V Conditions Recognized HIGH Signal Min 54FCT 4.3 V Min 54FCT 2.4 V Min V Min Recognized LOW Signal IIN = −18 mA IOH = −300 uA IOH = −12 mA IOL = 300 µA VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current −5 µA Max IOZH High Impedance Output Current 10 µA Max IOZL High Impedance Output Current -10 µA Max IOS Output Short-Circuit Current −60 mA Max VIN = 0.0V VIN = 5.5V VIN = 0.0V VOUT = 0.0V ICCQ Power Supply Current 1.5 mA Max VIN = 0.2V or VIN = 5.3V ∆ICC Power Supply Current 2.0 mA Max ICCT Total Power Supply Current 5.6 mA Max 4.0 mA Max 0.25 mA/MHz Max VIN = 3.4V VIN = 3.4V or VIN =GND, OE = GND, fI = 10Mhz, outputs open, one bit toggling, 50% duty cycle VIN = 5.3V or VIN = 0.2V,OE = GND, fI = 10Mhz, outputs open, one bit toggling, 50% duty cycle Outputs Open, OE = GND, one bit toggling, 50% duty Cycle ICCD Dynamic ICC 54FCT 0.2 54FCT 0.5 V Min 5 µA Max 3 IOL = 32 mA VIN = 5.5V www.national.com 54FCT373 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. 54FCT373 AC Electrical Characteristics Symbol Parameter 54FCT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units Fig. No. ns Figure 4 ns Figure 4 ns Figure 6 ns Figure 6 CL = 50 pF Min Max tPLH Propagation Delay 1.5 8.5 tPHL Dn to On 1.5 8.5 tPLH Propagation Delay 2.0 15.0 tPHL LE to On 2.0 15.0 tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ 1.5 13.5 1.5 13.5 1.5 12.5 1.5 12.5 AC Operating Requirements Symbol Parameter 54FCT TA = −55˚C to +125˚C VCC = 4.5V to 5.5V Units Fig. No. ns Figure 7 ns Figure 7 ns Figure 5 CL = 50 pF Min ts(H) Setup Time, HIGH 2.0 ts(L) or LOW Dn to LE 2.0 th(H) Hold Time, HIGH 3.0 th(L) or LOW Dn to LE 3.0 Pulse Width, 6.0 tw(H) LE HIGH Capacitance Symbol Parameter Max Units CIN Input Capacitance 10 pF Conditions (TA = 25˚C) VCC = 0V COUT (Note 3) Output Capacitance 12 pF VCC = 5.0V Note 3: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com 4 Max 54FCT373 AC Loading DS100957-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions DS100957-4 *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load DS100957-5 FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100957-6 FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS100957-7 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times DS100957-9 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.national.com 54FCT373 Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Chip Carrier (L) NS Package Number E20A www.national.com 6 54FCT373 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Dual-In-Line (D) NS Package Number J20A 20-Lead Ceramic Flatpak (F) NS Package Number W20A 7 www.national.com 54FCT373 Octal Transparent Latch with TRI-STATE Outputs Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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