SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
D 2-V to 6-V VCC Operation
D High-Current 3-State Parallel Register
Outputs Can Drive Up To 15 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 14 ns
15
3
14
4
13
5
12
6
11
7
10
8
9
QD
QE
NC
QF
QG
NC
VCC
QA
QC
QB
VCC
QA
OE
RCLK
CCKEN
CCLK
CCLR
RCO
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
OE
RCLK
NC
CCKEN
CCLK
GND
NC
RCO
CCLR
16
2
QH
1
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
8-Bit Counter With Register
Counter Has Direct Clear
SN54HC590A . . . FK PACKAGE
(TOP VIEW)
SN54HC590A . . . J OR W PACKAGE
SN74HC590A . . . D, DW, OR N PACKAGE
(TOP VIEW)
QB
QC
QD
QE
QF
QG
QH
GND
D
D
D
D
NC − No internal connection
description/ordering information
The ’HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register
has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary
counter features direct clear (CCLR) and count-enable (CCKEN) inputs. A ripple-carry output (RCO) is provided
for cascading. Expansion is accomplished easily for two stages by connecting RCO of the first stage to CCKEN
of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage
to the counter clock (CCLK) input of the following stage.
CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together,
the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock
enable.
ORDERING INFORMATION
PACKAGE†
TA
PDIP − N
−40°C to 85°C
TOP-SIDE
MARKING
Tube of 25
SN74HC590AN
Tube of 40
SN74HC590AD
Reel of 2500
SN74HC590ADR
Reel of 250
SN74HC590ADT
Tube of 40
SN74HC590ADW
Reel of 2000
SN74HC590ADWR
CDIP − J
Tube of 25
SNJ54HC590AJ
SNJ54HC590AJ
CFP − W
Tube of 150
SNJ54HC590AW
SNJ54HC590AW
SOIC − D
SOIC − DW
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
SN74HC590AN
HC590A
HC590A
LCCC - FK
Tube of 55
SNJ54HC590AFK
SNJ54HC590AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
(+&%#$ %!(*"# # 234
"** (""!'#'$ "' #'$#'+
&*'$$ #-'/$' #'+, "** #-' (+&%#$
(+&%#
(%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1 "** (""!'#'$,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
timing diagram
OE
CCLR
CCKEN
CCLK
RCLK
COUNTER
(internal)
QA−QH
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Don’t
Care
Hex 00
Don’t
Care
Hex 01
Hex 00
Hex 02
Hex 03
Hex 04
Hex 05
Hex FE
Hex FF
Hex 00
Hex01
Hi-Z
Hex 01
Hex 01
RCO
TIMING SEQUENCE
1. Clear Counter (asynchronous).
2. Count up: 0x01. Store 0x00 in register.
3. Inhibit counter clock (CCKEN = HIGH). Store 0x01 in register.
4. Count 0x02, 0x03.
5. 3-state the outputs
6. Count up: 0x04
7. Enable outputs.
8. Continue up: 0x05
9. Store 0x05 in register.
10. Continue counting: 0x06...0xFD, 0xFE, 0xFF, 0x00, etc.
11. Store 0x00 in register.
2
Hex FD
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Hex 05
Hex 00
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
OE
RCLK
CCKEN
CCLK
CCLR
14
13
12
9
RCO
11
10
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
T
1R
C1
1S
R
R
R
R
R
R
R
R
15
1
2
3
4
5
6
7
QA
QB
QC
QD
QE
QF
QG
QH
Pin numbers shown are for the D, DW, J, N, and W packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC590A
VCC
VIH
Supply voltage
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt‡
Low-level input voltage
MIN
NOM
MAX
2
5
6
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
VCC = 4.5 V
VCC = 6 V
Input voltage
0
Output voltage
0
Input transition (rise and fall) time
SN74HC590A
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
0.5
1.35
1.35
1.8
1.8
0
0
V
V
0.5
VCC
VCC
UNIT
VCC
VCC
1000
1000
500
500
400
400
V
V
V
ns
TA
Operating free-air temperature
−55
125
−40
85
°C
‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CCLK and RCLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −20 µA
VOH
VI = VIH or VIL
RCO, IOH = −4 mA
QA−QH, IOH = −6 mA
RCO, IOH = −5.2 mA
QA−QH, IOH = −7.8 mA
IOL = 20 µA
VOL
VI = VIH or VIL
RCO, IOL = 4 mA
QA−QH, IOL = 6 mA
RCO, IOL = 5.2 mA
QA−QH, IOL = 7.8 mA
II
IOZ
VI = VCC or 0
VO = VCC or 0
ICC
VI = VCC or 0,
Ci
IO = 0
VCC
MIN
TA = 25°C
TYP
MAX
SN54HC590A
MIN
MAX
SN74HC590A
MIN
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
3.98
4.3
3.7
3.84
3.98
4.3
3.7
3.84
5.48
5.8
5.2
5.34
4.5 V
6V
5.48
5.8
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
0.17
0.26
0.4
0.33
0.15
0.26
0.4
0.33
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
6V
±0.01
±0.5
±10
±5
µA
8
160
80
µA
10
10
10
pF
4.5 V
6V
6V
2V
to 6 V
POST OFFICE BOX 655303
3
• DALLAS, TEXAS 75265
V
5
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
CCLK or RCLK high or low
tw
Pulse duration
CCLR low
CCKEN low before CCLK↑
tsu
Setup time
CCLR high (inactive) before CCLK↑
CCLK↑ before RCLK↑†
th
Hold time
CCKEN low after CCLK
CCLK↑
TA = 25°C
MIN
MAX
SN54HC590A
MIN
MAX
SN74HC590A
MIN
MAX
2V
4
2.5
3.2
4.5 V
20
13
16
6V
24
16
19
2V
125
200
155
4.5 V
25
38
31
6V
21
32
26
2V
100
150
125
4.5 V
20
30
25
6V
17
26
21
2V
100
150
125
4.5 V
20
30
25
6V
17
26
21
2V
100
150
125
4.5 V
20
30
25
6V
17
26
21
2V
100
150
125
4.5 V
20
30
25
6V
17
26
21
2V
50
75
60
4.5 V
10
15
12
6V
9
13
11
UNIT
MHz
ns
ns
ns
† This setup time ensures that the register gets stable data from the counter outputs. The clocks may be tied together, in which case the register
is one clock pulse behind the counter.
6
POST OFFICE BOX 655303
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SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54HC590A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
tPLH
tpd
ten
tdis
CCLK↑
RCO
CCLR↓
RCO
RCLK↑
Q
OE↓
Q
OE↑
Q
RCO
tt*
Q
VCC
TA = 25°C
MIN
TYP
MAX
MIN
2V
4
8
2.5
4.5 V
20
35
13
6V
24
40
16
MAX
UNIT
MHz
2V
80
150
225
4.5 V
20
31
45
6V
15
26
38
2V
70
130
195
4.5 V
18
28
39
6V
14
23
33
2V
70
140
210
4.5 V
18
31
42
6V
14
25
36
2V
80
125
185
4.5 V
20
30
37
6V
15
28
31
2V
80
125
185
4.5 V
20
30
37
6V
15
28
31
2V
38
75
110
4.5 V
8
15
22
6V
6
13
19
2V
38
60
90
4.5 V
8
12
18
6V
6
10
15
ns
ns
ns
ns
ns
ns
* This parameter is not production tested for the SN54HC590A.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN74HC590A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
tPLH
tpd
ten
tdis
CCLK↑
CCLR↓
RCLK↑
OE↓
OE↑
RCO
RCO
Q
Q
Q
RCO
tt
Q
8
POST OFFICE BOX 655303
VCC
TA = 25°C
MIN
TYP
MAX
MIN
2V
4
8
3.2
4.5 V
20
35
16
6V
24
40
19
MAX
MHz
2V
80
150
190
4.5 V
20
30
38
6V
15
26
33
2V
70
130
165
4.5 V
18
26
33
6V
14
22
28
2V
70
140
175
4.5 V
18
28
35
6V
14
24
30
2V
80
125
155
4.5 V
20
25
31
6V
15
21
26
2V
80
125
155
4.5 V
20
25
31
6V
15
21
26
2V
38
75
95
4.5 V
8
15
19
6V
6
13
16
2V
38
60
75
4.5 V
8
12
15
6V
6
10
13
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
SN54HC590A
PARAMETER
tpd
ten
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
TYP
MAX
2V
100
300
447
Q
4.5 V
24
60
90
6V
20
51
77
RCLK↑
OE
Q
tt*
Q
MIN
MAX
2V
90
200
300
4.5 V
23
40
60
6V
19
34
51
2V
45
210
315
4.5 V
17
42
63
6V
13
36
53
UNIT
ns
ns
ns
* This parameter is not production tested for the SN54HC590A.
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
SN74HC590A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
tpd
ten
RCLK↑
Q
OE
Q
tt
Q
TA = 25°C
TYP
MAX
MIN
MAX
2V
100
300
380
4.5 V
24
60
76
6V
20
51
65
2V
90
200
250
4.5 V
23
40
50
6V
19
34
43
2V
45
210
265
4.5 V
17
42
53
6V
13
36
45
UNIT
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TEST CONDITIONS
TYP
UNIT
No load
250
pF
9
SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
PARAMETER
S1
Test
Point
From Output
Under Test
ten
RL
tPZH
RL
CL
50 pF
or
150 pF
1 kΩ
tPZL
tdis
S2
tPLZ
1 kΩ
50 pF
−−
50 pF
or
150 pF
tpd or tt
LOAD CIRCUIT
50%
Closed
Closed
Open
Open
Closed
Closed
Open
Open
Open
50%
0V
50%
tsu
0V
tw
Data
50%
Input 10%
VCC
Low-Level
Pulse
50%
50%
50%
0V
tPLH
50%
10%
tPHL
90%
90%
tr
tPHL
90%
tf
50%
10%
Output
Control
(Low-Level
Enabling)
50%
10% V
OL
tf
tPZL
Output
Waveform 1
(See Note B)
VOH
tPZH
VOH
tPLH
50%
10%
90%
90%
VCC
50%
10% 0 V
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VCC
50%
th
tr
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Out-ofPhase
Output
Open
VCC
Reference
Input
VCC
High-Level
Pulse
In-Phase
Output
S2
tPHZ
CL
(see Note A)
Input
S1
90%
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VCC
50%
Output
Waveform 2
(See Note B)
50%
0V
tPLZ
≈VCC
50%
10%
≈VCC
VOL
tPHZ
50%
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-89603012A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
5962-8960301EA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
5962-8960301FA
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
SN54HC590AJ
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SN74HC590AD
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590ADE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590ADR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590ADRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590ADT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590ADTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590ADW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590ADWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590ADWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590ADWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC590AN
ACTIVE
PDIP
N
16
CU NIPDAU
Level-NC-NC-NC
25
Pb-Free
(RoHS)
SN74HC590AN3
OBSOLETE
PDIP
N
16
TBD
Call TI
SN74HC590ANE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Call TI
Level-NC-NC-NC
SNJ54HC590AFK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54HC590AJ
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SNJ54HC590AW
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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