REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) A Added footnotes 14/, 15/, and 16/ to table I. Made changes to footnote 12/ in table I. Corrected pin name on pin 66 in figure 2. Corrected pin number in figure 5. Made editorial changes throughout. – LTG 00-10-23 Thomas M. Hess B Update boilerplate to MIL-PRF-38535 requirements. – LTG 01-03-28 Thomas M. Hess C Add appendix A to document.- LTG 01-06-14 Thomas M. Hess D Add device type 02. – LTG 02-07-18 Thomas M. Hess REV C C C C C C C SHEET 35 36 37 38 39 40 41 REV A SHEET 15 16 17 18 19 20 D B D A B A D 21 22 23 24 25 26 27 28 29 30 APPROVED D D C C 31 32 33 34 REV STATUS REV D D D C B D D D D D D D A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Larry T. Gauder STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil CHECKED BY Thanh V. Nguyen APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, CMOS, RAD HARD MICROCONTROLLER, MONOLITHIC SILICON DRAWING APPROVAL DATE 99-03-05 AMSC N/A REVISION LEVEL D SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 1 OF 5962-98583 41 5962-E502-02 14 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 Federal stock class designator \ RHA designator (see 1.2.1) 98583 01 Device type (see 1.2.2) / Q Device class designator (see 1.2.3) X Case outline (see 1.2.4) X Lead finish (see 1.2.5) \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 02 Generic number Circuit function UT80C196KD or UT80CRH196KD 1/ UT80C196KD or UT80CRH196KD 1/ MIL-TEMP, MCS-96 Based Microcontroller Extended Industrial Temp, MCS-96 Based Microcontroller 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter X Descriptive designator See figure 1 Terminals Package style 68 Quad flatpack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1/ The RH in the Generic number signifies the radiation hardened version of the device. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 2 1.3 Absolute maximum ratings. 1/ DC supply voltage (VDD) - - - - - - - - - - - - - - - - - - - - Voltage on any pin (VI/O) - - - - - - - - - - - - - - - - - - - - DC input current (II) - - - - - - - - - - - - - - - - - - - - - - - Storage temperature (TSTG) - - - - - - - - - - - - - - - - - - Maximum power dissipation (PD) - - - - - - - - - - - - - Maximum junction temperature (TJ) - - - - - - - - - - - - Thermal resistance, junction-to-case (θJC) - - - - - - - - -0.3 V to +6.0 V -0.3 V to VDD +0.3 V ±10 mA -65°C to +150°C 4W +175°C 2°C/W per MIL-STD-883, Method 1012 1.4 Recommended operating conditions. DC supply voltage (VDD) - - - - - - - - - - - - - - - - - - - - Temperature range (TC) - - - - - - - - - - - - - - - - - - - - Temperature range (TC) - - - - - - - - - - - - - - - - - - - - DC input voltage (VIN) - - - - - - - - - - - - - - - - - - - - - - High level input voltage (XTAL1) (VIH) - - - - - - - - - - - - Low level input voltage (XTAL1) (VIL) - - - - - - - - - - - - Min high level input voltage (VIH) - - - - - - - - - - - - - - Max low level input voltage (VIL) - - - - - - - - - - - - - - - 4.5 V to 5.5 V -55°C to +125°C (Device type 01) -40°C to +125°C (Device type 02) 0 V to VDD 0.7VDD 0.3VDD 2.2 V 2/ 0.8 V 2/ 1.5 Radiation features. Total dose (dose rate = 50 to 300 rad(Si)/s) - - - - - - 100 Krads (Si) Single event phenomenon effective linear 2 energy threshold, (LET) no upset - - - - - - - - - - - - 25 MeV-cm /mg 2 Neutron fluence - - - - - - - - - - - - - - - - - - - - - - - - - - 1.0E14 n/cm 1.6 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) - - - - - - - - 95 percent 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 MIL-STD-1835 - 1/ 2/ Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Except XTAL1 and RESET. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 3 HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Load circuit and waveforms. The Load circuit and waveforms shall be as specified on figure 4. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 4 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL B SHEET 5 TABLE IA. Electrical performance characteristics. Test Symbol Conditions 1/ 17/ VDD = 5.0 V ±10% unless otherwise specified Group A subgroups Device type Limits Min Unit Max 0.8 Low level input voltage (except XTAL1, RESET) High level input voltage (except XTAL1, RESET) High level input voltage (XTAL1) Low level input voltage (XTAL1) High level output voltage (Standard outputs) 14/ VIL 1, 2, 3 All VIH 1, 2, 3 All 2.2 V VIH1 1, 2, 3 All .7VDD V VIL1 1, 2, 3 All 1, 2, 3 All High level output current (Open drain outputs 2/ with pullups) IOH Low level output voltage VOL VOH IOH = -200 µA 13/ (CMOS) .3VDD VDD-.3 IOH = -4.0 mA (TTL) Pullups on ADV, RD, RESET, Port 1, Port 2.0, 2.6, 2.7, AD0-15, WR, WRL, BHE, ALE, CLKOUT 13/ Pulldown on INST, NMI, HSO.0-HSO.3, P2.5 13/ Logical 0 input current (Test mode entry) 3/ I/O leakage current, standard inputs and outputs I/O leakage current, with pullups 4/ I/O leakage current, with pulldowns 5/ V V 3.8 VOH = VDD -.3 13/ 1, 2, 3 µA -20 All VOH = VDD -.9 -60 IOL = 200 µA (CMOS) 13/ 1, 2, 3 0.3 All IOL = 4.0 mA (TTL) Positive going threshold RESET Negative going threshold RESET Typical range of Hysteresis RESET 13/ V V 0.4 VT+ 1, 2, 3 All .5VDD .7VDD V VT- 1, 2, 3 All .2VDD .4VDD V VH 1, 2, 3 All .9 V RPU VCC = 5.5 V, VIN = VSS 1, 2, 3 All 6.9 36.7 KΩ RPD VCC = 5.5 V, VIN = VDD 1, 2, 3 All 3.7 27.5 KΩ IIL VIN = VIH 1, 2, 3 All -550 -120 µA ILI VIN = VSS or VDD 1, 2, 3 All -5 +5 µA ILI1 VIN = VSS 1, 2, 3 All -800 -150 µA ILI2 VIN = VDD 1, 2, 3 All 200 1500 µA See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 6 TABLE IA. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ 17/ VDD = 5.0 V ±10% unless otherwise specified Group A Subgroups Device Type Limits 1, 2, 3 All Max 65 mA 1, 2, 3 All 110 mA 1, 3 All 20 µA 2 All 1000 µA Min Unit Power supply current in reset IDDRESET Active power supply current AIDD Quiescent power supply current QIDD M,D,P,L, and R 1 All 1000 µA Power supply current in power down IDDPD CLK @ 20MHz, no active I/O 1, 2, 3 All 6 mA Power supply current in idle mode IDDIDLE CLK @ 20 MHz, no active I/O 1, 2, 3 All 55 mA Pin capacitance CIO @ 1 MHz, 25°C 13/ 4 All 15 pF Short circuit output current, except for pins noted in Note 12 Short circuit output current, for pins noted in Note 12 Functional tests IOS VDD = 5.5 V 11/ 13/ 1, 2, 3 All -100 130 mA IOS1 VDD = 5.5 V 1, 2, 3 All -200 250 mA 7, 8 All Address VALID to READY setup 13/ tAVYV 9, 10, 11 All 2TOSC -30 ns Non-READY time 13/ tYLYH 9, 10, 11 All No upper limit ns READY hold after CLKOUT low 6/ 13/ tCLYX 9, 10, 11 All 0 2TOSC -20 ns READY hold after ALE low 6/ 13/ tLLYX 9, 10, 11 All TOSC 3TOSC -20 ns Address valid to BUSWIDTH setup 13/ tAVGV 9, 10, 11 All 2TOSC -30 ns BUSWIDTH hold after CLKOUT low 13/ Address valid to input data valid 7/ 13/ tCLGX 9, 10, 11 All tAVDV 9, 10, 11 All tRLDV 9, 10, 11 All tCLDV 9, 10, 11 tRHDZ tRXDX RD Active to input data valid 7/ CLKOUT low to input data valid 13/ CLK @ 20 MHz, RESET ≤ VIL CLK @ 20 MHz, typical Program flow 11/ 12/ 13/ See 4.4.1c See figure 4 0 ns 3TOSC -29 ns 5 13/ TOSC-26 ns All 5 TOSC-26 ns 9, 10, 11 All 0 TOSC-10 ns 9, 10, 11 All 0 TOSC-10 ns End of RD to input data float 13/ Data hold after RD inactive 13/ See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 7 TABLE IA. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ 17/ VDD = 5.0 V ±10% unless otherwise specified Group A subgroups Device Type See figure 4 9, 10, 11 All Min 1 16/ Max 20 15/ MHz Limits Unit Frequency on XTAL1 13/ fOSC XTAL1 period (1/fOSC ) 13/ TOSC 9, 10, 11 All 50 15/ 1000 16/ ns XTAL1 high to CLKOUT high or low CLKOUT cycle time 15/ tXHCH 9, 10, 11 All 0 25 ns tCLCL 9, 10, 11 All CLKOUT high period 13/ tCHCL 9, 10, 11 All TOSC-10 TOSC +10 ns CLKOUT falling edge to ALE rising ALE falling edge to CLKOUT rising 13/ ALE cycle time 7/ 15/ tCLLH 9, 10, 11 All -5 +15 ns tLLCH 9, 10, 11 All -10 +10 ns tLHLH 9, 10, 11 All ALE high period 13/ tLHLL 9, 10, 11 All TOSC-10 Address setup to ALE falling edge 13/ Address hold after ALE falling edge tAVLL 9, 10, 11 All TOSC-15 tLLAX 9, 10, 11 All TOSC-20 TOSC+5 ns tLLRL 9, 10, 11 All TOSC-5 TOSC+10 ns tRLCL 9, 10, 11 All -5 +10 ns tRLRH 9, 10, 11 All TOSC-5 tRHLH 9, 10, 11 All TOSC -10 TOSC +10 ns tRLAZ 9, 10, 11 All -5 +5 ns tLLWL 9, 10, 11 All TOSC-10 TOSC +10 ns 2TOSC ns 4TOSC TOSC +15 ns ns ns ALE falling edge to RD falling edge RD low to CLKOUT falling edge ns RD low period 7/ RD rising edge to ALE risng edge 8/ 13/ RD low to address float 13/ ALE falling edge to WR falling edge 13/ See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 8 TABLE IA. Electrical performance characteristics – Continued. Test Conditions 1/ 17/ VDD = 5.0 V ±10% unless otherwise specified Group A subgroups Device Type See figure 4 9, 10, 11 All Min -5 Max +10 tQVWH 9, 10, 11 All TOSC-10 TOSC +10 ns tCHWH 9, 10, 11 All -10 +15 ns tWLWH 9, 10, 11 All TOSC-10 tWHQX 9, 10, 11 All TOSC-10 TOSC +10 ns tWHLH 9, 10, 11 All TOSC-10 TOSC +10 ns tWHBX 9, 10, 11 All TOSC-10 TOSC +10 ns tWHAX 9, 10, 11 All TOSC-25 tRHBX 9, 10, 11 All TOSC-10 tRHAX 9, 10, 11 All TOSC-25 tAVENV 9, 10, 11 All tLHENX 9, 10, 11 All tAVEV 9, 10, 11 All tRXEX 9, 10, 11 All tEVWH 9, 10, 11 tWHEX 9, 10, 11 Symbol tCLWL Limits Unit ns CLKOUT low to WR falling edge Data stable to WR rising edge 7/ CLKOUT high to WR rising edge 13/ ns WR low period 7/ 13/ Data hold after WR rising edge 13/ WR rising edge to ALE rising edge 8/ 13/ BHE, INST after WR rising edge 13/ ns AD8-15 HOLD after WR rising 9/ 13/ BHE, INST after RD rising edge 13/ TOSC +10 ns ns AD8-15 HOLD after RD rising 9/ 13/ 2TOSC -30 Address valid to EDACEN valid 13/ EDACEN hold after ALE high 13/ Address valid to EDAC input valid 7/ 13/ 0 ns 0 TOSC -10 ns All TOSC -10 TOSC +10 ns All TOSC -10 TOSC +10 ns EDAC output stable to WR rising 7/ 13/ EDAC output hold after WR rising 13/ See footnotes at end of table. DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 ns 3TOSC -29 EDAC hold after RD inactive 13/ STANDARD MICROCIRCUIT DRAWING ns SIZE 5962-98583 A REVISION LEVEL D SHEET 9 TABLE IA. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ 17/ VDD = 5.0 V ±10% unless otherwise specified Group A Subgroups Device Type Limits Min Unit Max EXTERNAL CLOCK DRIVE TIMING CHARACTERISTICS Oscillator Frequency fosc Oscillator Period (1/fosc) See figure 4 9, 10, 11 All 1 13/ 20 MHz TOSC 9, 10, 11 All 50 1000 13/ ns High time 13/ tOSCH 9, 10, 11 All 17 ns Low time 13/ tOSCL 9, 10, 11 All 17 ns Rise time 10/ tOSCR 9, 10, 11 All 10 ns Fall time 10/ tOSCF 9, 10, 11 All 10 ns 9, 10, 11 All 25 tCLHAL 9, 10, 11 All -15 15 ns tCLBRL 9, 10, 11 All -15 15 ns tHALAZ 9, 10, 11 All 10 ns tHALBZ 9, 10, 11 All 15 ns tCLHAH 9, 10, 11 All -15 15 ns tCLBRH 9, 10, 11 All -15 15 ns tHAHAX 9, 10, 11 All -15 ns tHAHBV 9, 10, 11 All -10 ns tCLLH 9, 10, 11 All -5 HOLD/HLDA TIMINGS tHVCH See figure 4 ns HOLD setup 13/ CLKOUT low to HLDA low 13/ CLKOUT low to BREQ low 13/ HLDA low to address float 13/ HLDA low to BHE, INST, RD, WR driven weakly 13/ CLKOUT low to HLDA high 13/ CLKOUT low to BREQ high 13/ HLDA high to address no longer float 13/ HLDA high to BHE, INST, RD, WR valid 13/ CLKOUT low to ALE high 13/ See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 15 ns SIZE 5962-98583 A REVISION LEVEL D SHEET 10 TABLE IA. Electrical performance characteristics – Continued. Test Symbol Conditions 1/ 17/ VDD = 5.0 V ±10% unless otherwise specified Group A subgroups Device Type Limits Min Unit Max SERIAL PORT TIMING Serial port clock period (BRR = 8002H) 15/ tXLXL Serial port clock falling edge to rising edge (BRR = 8002H) 13/ 9, 10, 11 All tXLXH 9, 10, 11 All Serial port clock period (BRR = 8001H) 15/ tXLXL 9, 10, 11 All Serial port clock falling edge to rising edge (BRR = 8001H) 13/ tXLXH 9, 10, 11 All 2 TOSC -50 Output data valid to clock rising edge 13/ tQVXH 9, 10, 11 All 2 TOSC -50 ns Output data hold after clock rising edge 13/ tXHQX 9, 10, 11 All 2 TOSC -50 ns Next output data valid after clock rising edge 13/ tXHQV 9, 10, 11 All Input data setup to clock rising edge 13/ tDVXH 9, 10, 11 All TOSC +50 ns Input data hold after clock rising edge 13/ tXHDX 9, 10, 11 All 0 ns Last clock rising to output float 13/ See footnotes on next page. tXHQZ 9, 10, 11 All 2 TOSC -10 See figure 4 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 6 TOSC 4 TOSC -50 ns 4 TOSC +50 4 TOSC ns ns 2 TOSC +50 2 TOSC +50 2 TOSC +10 ns ns ns SIZE 5962-98583 A REVISION LEVEL D SHEET 11 TABLE IA. Electrical performance characteristics – Continued. 1/ Devices supplied to this drawing are characterized at all levels M, D, P, L, and R of irradiation. However, this device is only tested at the 'R' level. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25°C. 2/ Open-drain outputs include Port 1, P2.6 and P2.7. 3/ Test modes are entered at the RESET rising edge by applying VIL to one or more of the following pins TXD, RD, WR, HLDA. To avoid entering a test mode, ensure that these pins remain above VIH during the rising edge of RESET. 4/ Inputs/outputs with pullup resistors include: RESET, Port 1, Port 2.0, P2.6, P2.7, WR, BHE, AD0-15, RD, ALE, CLKOUT. 5/ Inputs/outputs with pulldown resistors include: NMI, HSO.0- HSO.3, P2.5, INST. 6/ If max exceeded, additional wait state occurs. 7/ If wait states are used, add 2 TOSC *N, where N = number of wait states. 8/ Assuming back-to-back bus cycles. 9/ 8-bit only. 10/ Supplied as a design limit but not guaranteed or tested. 11/ Not more than one output may be shorted at a time for maximum duration of one second. 12/ The IOS1 spec applies to pins RESET, BHE, RD, and CLKOUT. 13/ Tested only at initial qualification, and after any design or process changes which may affect this characteristic. 14/ For standard outputs not covered by the IOH spec. 15/ These specs are verified using functional vectors (strobed) only. 16/ Low speed tests performed at 5 MHz. 1 MHz operation is guaranteed by design. 17/ Unless otherwise specified, the temperature conditions for device type 01 is -55°C to +125°C, and -40°C to +125°C for device type 02. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 12 TABLE IB. SEP test limits . 1/ 2/ Device Type All TA = Temperature ±10°C 3/ VCC = 4.5 V Effective LET no Upsets 2 [MeV-m /mg)] = 25 +25°C VCC = 5.5 V Maximum device cross section 2 (Cm ) (LET = 80) -3 3.0 x 10 Effective LET no Latchup 3/ 2 [MeV-cm /mg) > 128 1/ Devices that contain cross coupled resistance must be tested at the maximum rated TA . For SEP test conditions, see 4.4.4.4 herein. 2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity. 3/ Worst case temperature TA = +125°C. WEIBULL AND DEVICE PARAMETERS FOR ERROR-RATE CALCULATION SHAPE PARAMETER 1 WIDTH PARAMETER 14 STRUCTURAL CROSS-SECTION 2 3.66E-7cm /bit STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 ONSET LET 2 14.4MeV-cm /mg DEPLETION DEPTH 0.8µm FUNNEL DEPTH 1.45µm SIZE 5962-98583 A REVISION LEVEL A SHEET 13 Millimeters Symbol A A1 b c L D E e N Min --1.83 0.35 0.18 6.35 21.6 21.6 1.27 TYP 68 Inches Max 2.74 2.24 0.46 0.24 --24.50 24.50 1.27 TYP 68 Min --.072 .014 .007 .250 .850 .850 .050 TYP 68 Max .108 .088 .018 .0095 --.965 .965 .050 TYP 68 NOTES: 1. The U. S. Government preferred system of measurement is the metric SI system. However, since this item was originally designed using inch-pound units of measurement, in the event of conflict between the metric and inchpound units, the inch-pound units shall take precedence. Metric equivalents are for general information only. 2. All leads increase max limit by 0.003 inches measured at the center of the flat when lead finish A is applied. 3. Index area: a notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the area shown. The manufacturer’s identification shall not be used as pin one identification mark. FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL SHEET 14 FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL A SHEET 15 FIGURE 3. Functional Block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL SHEET 16 FIGURE 4. Load circuit and waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL SHEET 17 FIGURE 4. Load circuit and waveforms. - Continued STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL SHEET 18 FIGURE 4. Load circuit and waveforms. - Continued STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL SHEET 19 FIGURE 4. Load circuit and waveforms. - Continued STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL SHEET 20 NOTE: AC Testing inputs are driven at VDD for a Logic "1" and 0.0 V for a Logic "0". Timing measurements on outputs are made at 1.4 V. AC Testing Input, Output Waveforms. FIGURE 4. Load circuit and waveforms. - Continued STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL SHEET 21 Float Waveforms NOTE: For timing purposes a port pin is no longer floating when it changes to a voltage outside reference points shown, and begins to float when it changes to voltage inside the reference points shown; IOL = 4 mA, IOH = -4 mA . FIGURE 4. Load circuit and waveforms. - Continued STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL SHEET 22 Open 2,4-8, 17-23, 26-35, 38-41, 45-63, 65 NOTE: VDD = 5 V ±0.5V 9, 11, 16, 24, 37, 43, 64 GND 3, 10, 15, 25, 42, 44, 66, 67 VDD External Pin 1, 13 GND External Pin 12, 14, 36, 68 Each pin except those labeled “VDD External Pin” and “GND External Pin” will have a resistor of 2.49KΩ ±5% for irradiation. FIGURE 5. Radiation exposure circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 23 4. QUALITY ASSURANCE PROVISIONS 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. (2) TA = +125°C, minimum. b. Interim and final electrical test parameters shall be as specified in table IIA herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL B SHEET 24 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroup 4 (CI/O) shall be measured only for the initial test and after process or design changes which may affect input capacitance. One pin of each input/output driver (buffer) type shall be tested on each sample device. c. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. These tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.6 herein). TABLE IIA. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-PRF-38535, table III) Subgroups (in accordance with MIL-STD-883, method 5005, table I) Device class Q Device Class M ---- Interim electrical Parameters (see 4.2) ---- Device class V ---- Final electrical Parameters (see 4.2) 1/ 1, 2, 3, 7, 8, 9, 10, 11 1/ 1, 2, 3, 7, 8, 9, 10, 11 2/ 3/ 1, 2, 3, 7, 8, 9, 10, 11 Group A test Requirements (see 4.4) 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 Group C end-point electrical Parameters (see 4.4) 1, 2, 7, 8A 1, 2, 7, 8A 1, 2, 7, 8A 3/ Group D end-point electrical Parameters (see 4.4) 1, 2, 7, 8A 1, 2, 7, 8A 1, 2, 7, 8A Group E end-point electrical Parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 7. 3/ Delta limits as specified in Table IIB herein shall be required when specified and the Delta values shall be completed with reference to the zero hour electrical parameter. TABLE IIB. Burn-in delta parameters (+25°C). Parameter QIDD NOTE: Condition TA = 25°C Limits ±10% of measured value or 20 µA whichever is greater If device is tested at or below 20 µA no deltas are required. Delta’s are performed at room temperature. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 25 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. b. TA = +125°C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the post-irradiation end-point electrical parameter limits as defined in table IA at TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019 (condition A) and as specified herein. 4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.4.4.2 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accordance with test method 1020 of MIL-STD-883 and as specified herein (see 1.5). Tests shall be performed on devices, SEC, or approved test structures at technology qualification and after any design or process changes which may effect the RHA capability of the process. 4.4.4.3 Dose rate upset testing. Dose rate upset testing shall be performed in accoradance with test method 1021 of MIL-STD-883 and herein (see 1.5). a. Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes which may effect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified. b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved radiation hardness assurance plan and MIL-PRF-38535. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL A SHEET 26 4.4.4.4 Single event phenomena (SEP). SEP testing shall be required on class V devices (See 1.5). SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup characteristics. The recommended test conditions for SEP are as follows: a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed. b. The fluence shall be ≥ 100 errors or ≥ 10 ions/cm . 6 2 5 2 2 c. The flux shall be between 10 and 10 ions/cm /s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be ≥ 20 microns in silicon. e. The upset test temperature shall be +25°C and the latchup test temperature is maximum rated operating temperature ±10°C. f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. Test four devices with zero failures. h. For SEP test limits, see Table IB herein. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone (614) 692-0547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 , MIL-HDBK-1331, and Table III herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL B SHEET 27 TABLE III. Pin descriptions. Pin Name Description VDD +5 V Supply voltage VSS Circuit ground PORT 0 (P0.0-P0.7) Port 0 is an 8-bit input only port when used in its default mode. When configured for their alternate function, five of the bits are bi-directional EDAC check bits as shown in Table A herein. Port 1 is an 8-bit quasi-bidirectional, I/O port. All pins are quasi-bidirectional unless The alternate function is selected per Table B herein. When the pins are configured for Their alternate functions, they act as standard I/O, not quasibidirectional. Port 2 is an 8-bit, bidirectional, I/O port. These pins are shared with timer 2 Functions, serial data I/O and PWMO output, per Table C herein. The lower 8-bits of the multiplexed address/data bus. The pins on this port are Bidirectional during the data phase of the bus cycle. The upper 8-bits of the multiplexed address/data bus. The pins on this port are Bidirectional during the data phase of the 16 bit bus cycle. When running in 8-bit bus width, these pins are non-multiplexed, dedicated upper address bit outputs. CMOS level input of the oscillator inverter. PORT 1 (P1.0-P1.7) PORT 2 (P2.0-P2.7) AD0-AD7 AD8-AD15 XTAL1 CLKOUT Output of the internal clock generator. The frequency of CLKOUT is one-half the Oscillator frequency. RESET BUSWIDTH Active low reset input and open drain output. Input for the BUSWIDTH selection. If the Chip Configuration Register (CCR) bit 1 Is a logic high, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If the BUSWIDTH is a 0, an 8-bit Cycle occurs. If the CCR bit 1 is a logic low, then the bus is always an 8-bit bus. A positive transition causes a non-maskable interrupt vector through 203EH. NMI INST Output high during an external memory read indicates the read is a "fetch Instruction”. INST is valid throughout the bus cycle. INST is only activated during External memory access and output low for a data fetch. EDACEN EDACEN is an enable input for the error detection and correction functions. Address Latch Enable or Address Valid output, as selected by CCR. Both pin Options provide a signal to demultiplex the address from the address /data bus. When the pin is ADV, it goes inactive, high at the end of the bus cycle. ALE/ADV Is only activated during external memory accesses. ALE/ADV RD Read signal output to external memory. RD is only activated during external Memory reads. Write and Write Low output to external memory, as selected by the CCR. When Selected by the CCR, WR will go low for every external write. However WRL will go low only for external writes where an even byte is being written. WR/WRL is only selected for external memory writes. WR/WRL STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL A SHEET 28 TABLE III Pin descriptions – Continued. Pin Name Description Byte High Enable or Write High output to external memory, as selected by the CCR. When the BHE is selected, a logic low value selects the bank of memory That is connected to the high byte of the data bus, When the WRH function Is selected, the pin will go low if the bus cycle is writing to an odd memory location. When the CCR selects 8-bit BUSWIDTH mode, WRH is asserted for writes to all External memory locations. READY is the input used to lengthen external memory cycles for interfacing to Slow memory. A logic low value will place wait states in the memory cycle. Inputs to the High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI2 And HSI3. Two of these pins (HSI.2 and HSI.3) are shared with the HSO Unit. Two of these pins(HSI.0 and HSI.1) have alternate functions for Timer 2. Outputs from the High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, HSO.3, HSO.4 and HSO.5. Pins HSO.4 and HSO.5 are shared With pins HSI.2 and HSI.3 of the HSI Unit respectively. BHE/WRH READY HSI HSO TABLE A. PORT 0 ALTERNATE FUNCTIONS Port pin P0.0-P0.3, P0.6 P0.4, P0.5 P0.7 Alternate Name ECB0-ECB4 Alternate Function P0.4, P0.5 Input port pin. EXTINT Setting IOC1.1 = 1 will allow P0.7 to be used for EXTINT (INT07). Error detection and correction check bits. TABLE B. PORT 1 ALTERNATE FUNCTIONS P1.0 P1.0 I/O Pin P1.1 P1.1 I/O Pin P1.2 P1.2 I/O Pin P1.3 PWM1 Setting IOC3.2 = 1enables P1.3 as the Pulse Width Modulator (PWM1) output pin. P1.4 PWM2 Setting IOC3.3 = 1enables P1.4 as the Pulse Width Modulator (PWM2) output pin. P1.5 BREQ Bus Request, output activated when the bus controller has a pending external memory Cycle. Bus Hold Acknowledge, output indicating the release of the bus. P1.6 HLDA P1.7 HOLD Bus Hold, input requesting control of the bus. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 29 TABLE III. Pin descriptions – Continued. TABLE C. PORT 2 ALTERNATE FUNCTIONS Port Pin Alternate Name Alternate Function P2.0 TXD Transmit Serial Data. P2.1 RXD Receive Serial Data. P2.2 EXTINT External interrupt, Clearing IOC1.1 will allow P2.2 to be used for EXTINT (INT07). P2.3 T2CLK Timer 2 clock input and Serial port baud rate generator input. P2.4 T2RST Timer 2 Reset. P2.5 PWMO Pulse Width Modulator output 0. P2.6 T2UP-DN P2.7 T2CAPTURE Controls the direction of the Timer 2 counter. Logic High equals count down. Logic Low equals count up. A rising edge on P2.7 causes the value of Timer 2 to be captured into this register, And generates a Timer 2 Capture interrupt (INT11). 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. 6.7 Additional information. A copy of the following additional data shall be maintained and available from the device manufacturer: a. RHA upset levels. b. Test conditions (SEP). c. Number of upsets (SEP). d. Number of transients (SEP). e. Occurrence of latchup (SEP). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL SHEET 30 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-98583 A.1 SCOPE A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers approved QM plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number (PIN). When available a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN. A.1.2 PIN. The PIN shall be as shown in the following example: 5962 - Federal Stock class designator 98583 RHA designator (see A.2.1) 01 Q Device type (see A.2.2) 9 Device class designator (see A.2.3) Die code (See A.2.4) X Die Details (see A.2.5) Drawing Number A.1.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels. A dash (-) indicates a non-RHA die. A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function 01 UT80C196KD or UT80CRH196KD 1/ MIL-TEMP, MCS-96 Based, Microcontroller 02 UT80C196KD or UT80CRH196KD 1/ Extended Industrial Temp, MCS-96 Based, Microcontroller A.1.2.3 Device class designator. Device class Q or V Device requirements documentation Certification and qualification to the die requirements of MIL-PRF-38535. A.1.2.4 Die code. The die code designator shall be number 9 for all devices supplied as die only with no case outline. 1/ The RH in the Generic number signifies the radiation hardened version of the device. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 31 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-98583 A.1.2.5 Die Details. The die details designation shall be a unique letter which designates the die’s physical dimensions, bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product and variant supplied to this appendix. A.1.2.5.1 Die Physical dimensions. Die Types Die detail designator 01 02 Figure number A A A-1 A-1 A.1.2.5.2 Die Bonding pad locations and Electrical functions. Die Types Die detail designator 01 02 A A Figure number A-1 A-1 A.1.2.5.3 Interface Materials. Die Types Die detail designator 01 02 A A Figure number A-1 A-1 A.1.2.5.4 Assembly related information. Die Types Die detail designator 01 02 A A Figure number Substrate potential A-1 A-1 Tied to VSS Tied to VSS A.1.3 Absolute maximum ratings. See paragraph 1.3 within the body of this drawing for details. A.1.4 Recommended operating conditions. See paragraph 1.4 within the body of this drawing for details. A.2 APPLICABLE DOCUMENTS A.2.1 Government specifications, standards, bulletin, and handbooks. Unless otherwise specified, the following specifications, standards, bulletin, and handbook of the issue listed in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL D SHEET 32 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-98583 HANDBOOK DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. (Copies of the specification, standards, bulletin, and handbook required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity). A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. A.3 REQUIREMENTS A.3.1 Item Requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The modification in the QM plan shall not effect the form, fit or function as described herein. A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein. A.3.2.1 Die Physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1. A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as specified in 10.2.4.2 and on figure A-1. A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1. A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and figure A-1. A.3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as defined within paragraph 3.2.5 of the body of this document. A.3.3 Electrical performance characteristics and post- irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this document. A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA. A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed in 10.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535. A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein. A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuit die delivered to this drawing. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 33 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-98583 A.4 QUALITY ASSURANCE PROVISIONS A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The modifications in the QM plan shall not effect the form, fit or function as described herein. A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the manufacturer’s QM plan. As a minimum it shall consist of: a) Wafer Lot acceptance for Class V product using the criteria defined within MIL-STD-883 TM 5007. b) 100% wafer probe (see paragraph A.3.4). c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 TM2010 or the alternate procedures allowed within MIL-STD-883 TM5004. A.4.3 Conformance inspection. A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified within paragraphs 4.4.4.1, 4.4.4.1.1, 4.4.4.2, 4.4.4.3, and 4.4.4.4. A.5. DIE CARRIER A.5.1 Die carrier requirements. The requirements for the die carrier shall be in accordance with the manufacturer’s QM plan or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and electrostatic protection. A.6 NOTES A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications and logistics purposes. A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone (614)-692-0547. A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined with MIL-PRF-38535 and MIL-HDBK-1331. A.6.4 Sources of Supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see 30.6 herein) to DSCC-VA and have agreed to this drawing. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 34 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-98583 DIE BONDING PAD LOCATIONS AND ELECTRICAL FUNCTIONS o DIE PHYSICAL DIMENSIONS Die Size: Die Thickness: 394 mils. x 394 mils. 17.5 +/- 1 mils. o INTERFACE MATERIALS Top Metallization: Si Al Cu 9 kÅ-12.5kÅ Backside Metallization None: Backgrind Glassivation Type: Thickness PSG 10 KÅ +/- 2.kÅ Substrate: EPI on single crystal silicon o ASSEMBLY RELATED INFORMATION Substrate Potential: Tied to VSS Special assembly instructions: None FIGURE A-1. Die bonding pad locations and electrical functions. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 35 Appendix A APPENDIX A FORMS A PART OF SMD 5962-98583 Die bonding pad locations and electrical functions PAD XCENTER YCENTER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 165.0 158.7 152.4 146.1 139.8 133.5 127.2 120.9 114.6 108.3 102.0 95.7 89.4 83.1 76.8 70.5 64.2 57.9 51.6 45.3 39.0 32.7 26.4 20.1 13.8 7.5 1.2 -5.1 -11.4 -17.7 -24.0 -30.3 -36.6 -42.9 -49.2 -55.5 -61.8 -68.1 -74.4 -80.7 -87.0 -93.3 -99.6 -105.9 -112.2 -118.5 -124.8 -131.1 -137.4 -143.7 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 185.9 NOTE: The die center is the coordinate origin (0,0). Figure A-1 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 36 Appendix A APPENDIX A FORMS A PART OF SMD 5962-98583 Die bonding pad locations and electrical functions PAD XCENTER YCENTER 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 -150.0 -156.3 -162.6 -168.9 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 185.9 185.9 185.9 185.9 170.2 163.9 157.4 151.1 144.8 138.5 132.2 125.9 119.6 113.3 107.1 100.8 94.5 88.2 81.9 75.6 69.3 63.0 56.7 50.4 44.1 37.8 31.5 25.2 18.9 12.6 6.3 0.0 -6.3 -12.6 -18.9 -25.2 -31.5 -37.8 -44.1 -50.4 -56.7 -63.0 -69.3 -75.6 -81.9 -88.2 -94.5 -100.8 -107.1 -113.4 NOTE: The die center is the coordinate origin (0,0). Figure A-1 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 37 Appendix A APPENDIX A FORMS A PART OF SMD 5962-98583 Die bonding pad locations and electrical functions PAD XCENTER YCENTER 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 163 143 144 145 146 147 148 149 150 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -184.6 -168.9 -162.6 -156.3 -150.0 -143.7 -137.4 -131.1 -124.8 -118.5 -112.2 -105.9 -99.6 -93.3 -87.0 -80.7 -74.4 -68.1 -61.8 -55.5 -49.2 -42.9 -36.6 -30.3 -24.0 -17.7 -11.4 -5.1 1.2 7.5 13.8 20.1 26.4 165.0 39.0 45.3 51.6 57.9 64.2 70.5 76.8 83.1 -119.7 -126.0 -132.3 -138.6 -144.9 -151.2 -157.5 -164.0 -170.3 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 NOTE: The die center is the coordinate origin (0,0). Figure A-1 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 38 Appendix A APPENDIX A FORMS A PART OF SMD 5962-98583 Die bonding pad locations and electrical functions PAD XCENTER YCENTER 151 152 153 154 155 156 157 158 159 160 161 162 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 89.4 95.7 102.0 108.3 114.6 120.9 127.2 133.5 139.8 146.1 152.4 158.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -186.0 -170.3 -163.8 -157.5 -151.2 -144.9 -138.6 -132.3 -126.0 -119.7 -113.4 -107.1 -100.8 -94.5 -88.2 -81.9 -75.6 -69.3 -63.0 -56.7 -50.4 -44.1 -37.8 -31.5 -25.2 -18.9 -12.6 -6.3 0.0 6.3 12.6 18.9 25.2 31.5 37.8 44.1 50.4 56.7 NOTE: The die center is the coordinate origin (0,0). Figure A-1 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 39 Appendix A APPENDIX A FORMS A PART OF SMD 5962-98583 Die bonding pad locations and electrical functions PAD XCENTER YCENTER 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 180.7 63.0 69.3 75.6 81.9 88.2 94.5 100.8 107.1 113.4 119.7 126.0 132.3 138.6 144.9 151.2 157.6 163.9 170.2 NOTE: The die center is the coordinate origin (0,0). Figure A-1 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 40 Appendix A APPENDIX A FORMS A PART OF SMD 5962-98583 Figure A-1 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 DSCC FORM 2234 APR 97 SIZE 5962-98583 A REVISION LEVEL C SHEET 41 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 02-07-18 Approved sources of supply for SMD 5962-98583 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. Standard Microcircuit drawing PIN 1/ Vendor CAGE Number Vendor Similar PIN 2/ 5962R9858301QXA 65342 UT80CRH196KD-WCA 5962R9858301QXC 65342 UT80CRH196KD-WCC 5962R9858301VXA 65342 UT80CRH196KD-WCA 5962R9858301VXC 65342 UT80CRH196KD-WCC 5962-9858301QXA 65342 UT80C196KD-WCA 5962-9858301QXC 65342 UT80C196KD-WCC 5962R9858301Q9A 65342 UT80CRH196KD_QCDIE 5962R9858301V9A 65342 UT80CRH196KD_VCDIE 5962R9858302QXA 65342 UT80CRH196KD-WWA 5962R9858302QXC 65342 UT80CRH196KD-WWC 5962R9858302VXA 65342 UT80CRH196KD-WWA 5962R9858302VXC 65342 UT80CRH196KD-WWC 5962-9858302QXA 65342 UT80C196KD-WWA 5962-9858302QXC 65342 UT80C196KD-WWC 5962R9858302Q9A 65342 UT80CRH196KD_QWDIE 5962R9858302V9A 65342 UT80CRH196KD_VWDIE 1 of 2 STANDARD MICROCIRCUIT DRAWING BULLETIN – Continued. 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number Vendor name and address 65342 Aeroflex UTMC Microelectronic System Inc. 4350 Centennial Boulevard Colorado Springs, Colorado 80907-3486 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. 2 of 2