Revised September 2000 74ACQ646 • 74ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs General Description Features The ACQ/ACTQ646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental handling functions available are illustrated in Figure 1, Figure 2, Figure 3 and Figure 4. ■ Guaranteed simultaneous switching noise level and dynamic threshold performance The ACQ/ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. ■ Guaranteed pin-to-pin skew AC performance ■ Independent registers for A and B busses ■ Multiplexed real-time and stored data transfers ■ 300 mil slim dual-in-line package ■ Outputs source/sink 24 mA ■ Faster prop delays than the standard AC/ACT646 Ordering Code: Order Number 74ACQ646SC Package Number M24B Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACQ464ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACTQ646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACTQ464ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names A0–A7 Descriptions Data Register A Inputs Data Register A Outputs B0–B7 Data Register B Inputs CPAB, CPBA Clock Pulse Inputs Data Register B Outputs SAB, SBA Transmit/Receive Inputs G Output Enable Input DIR Direction Control Input FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation © 2000 Fairchild Semiconductor Corporation DS010635 www.fairchildsemi.com 74ACQ646 • 74ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs January 1990 74ACQ646 • 74ACTQ646 Logic Symbols IEEE/IEC Function Table Inputs G DIR CPAB CPBA H X H or L H or L H X H X L H L H L H L H L L L L X L L X L L X X X H or L X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Data I/O (Note 1) SAB SBA A0–A7 B0–B7 Input Input Function X X X X X X X L X X L X X H X A Register to Bn (Stored Mode) X H X Clock An Data into A Register and Output to Bn X L X L X H B Register to An (Stored Mode) X H Clock Bn Data into B Register and Output to An X X H or L Isolation Clock An Data into A Register Clock Bn Data into B Register An to Bn—Real Time (Transparent Mode) Input Output Clock An Data into A Register Bn to An—Real Time (Transparent Mode) Output Input Clock Bn Data into B Register Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. www.fairchildsemi.com 2 Real Time Transfer B-Bus to A-Bus FIGURE 1. FIGURE 2. Storage from Bus to Register Transfer from Register to Bus FIGURE 3. FIGURE 4. 74ACQ646 • 74ACTQ646 Real Time Transfer A-Bus to B-Bus Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ACQ646 • 74ACTQ646 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V VO = VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate ∆V/∆t ACQ Devices DC Output Source VIN from 30% to 70% of VCC ±50 mA VCC @ 3.0V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate ∆V/∆t DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACTQ Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V ACQ ACTQ Devices −65°C to +150°C VIN from 0.8V to 2.0V DC Latch-Up Source VCC @ 4.5V, 5.5V ±300 mA or Sink Current Junction Temperature (TJ) 140°C PDIP 125 mV/ns Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for ACQ Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH VCC TA = +25°C (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.85 4.76 0.002 0.1 0.1 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 IIN (Note 5) Maximum Input Leakage Current 5.5 ± 0.1 ± 1.0 µA VI = VCC, GND IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 4) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent (Note 5) Supply Current VIN = VCC or GND IOZT Maximum I/O VIN = VIL or VIH VOL Maximum LOW Level Output Voltage 3.0 IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 3) V IOUT = 50 µA VIN = VIL or VIH Leakage Current IOL = 12 mA V IOL = 24 mA (Note 3) 5.5 8.0 80.0 µA 5.5 ±0.6 ±6.0 µA VI(OE) = VIL, VIH Quiet Output Maximum Dynamic VOL www.fairchildsemi.com VI = VCC, GND VO = VCC, GND (An, Bn Inputs) VOLP IOL = 24 mA 5.0 1.1 1.5 4 V Figures 5, 6 (Note 6)(Note 7) Symbol VOLV Parameter Quiet Output Minimum Dynamic VOL VIHD Minimum HIGH Level Dynamic Input Voltage VILD Maximum LOW Level Dynamic Input Voltage (Continued) TA = +25°C VCC TA = −40°C to +85°C Units Conditions (V) Typ Guaranteed Limits 5.0 −0.6 −1.2 V 5.0 3.1 3.5 V (Note 6)(Note 8) 5.0 1.9 1.5 V (Note 6)(Note 8) Figures 5, 6 (Note 6)(Note 7) Note 3: Maximum of 8 outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 6: Plastic DIP package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 5V (ACQ). Input-under-test switching 5V to threshold (VILD), 0V to threshold (VIHD) f = 1 MHz. DC Electrical Characteristics for ACTQ Symbol VIH VIL VOH Parameter TA = +25°C VCC (V) Typ TA = −40°C to +85°C Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 IOH = −24 mA (Note 9) V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZT Maximum I/O Leakage Current (An, Bn Inputs) IOL = 24 mA (Note 9) 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.6 ±6.0 µA 1.5 mA VI = VCC − 2.1V VOLD = 1.65V Max ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic 5.5 75 mA IOHD Output Current (Note 10) 5.5 −75 mA ICC Maximum Quiescent Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Minimum HIGH Level Dynamic Input Voltage VILD Maximum LOW Level Dynamic Input Voltage 0.6 5.5 8.0 80.0 µA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VOHD = 3.85V Min VIN = VCC or GND Figures 5, 6 5.0 1.1 1.5 V 5.0 −0.6 −1.2 V 5.0 1.7 2.0 V (Note 11)(Note 13) 5.0 1.2 0.8 V (Note 11)(Note 13) (Note 11)(Note 12) Figures 5, 6 (Note 11)(Note 12) Note 9: All outputs loaded; thresholds on input associated with output under test. Note 10: Maximum test duration 2.0 ms, one output loaded at a time. Note 11: Plastic DIP Package. Note 12: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 13: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V ILD), 0V to threshold (VIHD), f = 1 MHz. 5 www.fairchildsemi.com 74ACQ646 • 74ACTQ646 DC Electrical Characteristics for ACQ 74ACQ646 • 74ACTQ646 AC Electrical Characteristics for ACQ Symbol tPLH tPHL tPLH tPHL tPLH Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 14) Min Typ Max Min Max Propagation Delay 3.3 3.5 9.0 12.0 3.5 13.0 Bus to Bus 5.0 2.5 6.5 9.0 2.5 9.5 Propagation Delay 3.3 3.5 9.0 12.0 3.5 13.0 Bus to Bus 5.0 2.5 6.5 9.0 2.5 9.5 Propagation Delay 3.3 3.5 10.0 13.0 3.5 14.0 Clock to Bus 5.0 2.5 7.0 9.5 2.5 10.5 Propagation Delay 3.3 3.5 10.0 13.0 3.5 14.0 Clock to Bus 5.0 2.5 7.0 9.5 2.5 10.5 Propagation Delay 3.3 3.5 9.5 12.5 3.5 13.5 SBA or SAB to An or Bn 5.0 2.5 6.5 9.0 2.5 10.0 Propagation Delay 3.3 3.5 9.5 12.5 3.5 13.5 SBA or SAB to An or Bn 5.0 2.5 6.5 9.0 2.5 10.0 Enable Time 3.3 3.5 10.5 14.5 3.5 15.5 G to An or Bn 5.0 2.5 8.0 10.5 2.5 11.5 Enable Time 3.3 3.5 10.5 14.5 3.5 15.5 G to An or Bn 5.0 2.5 8.0 10.5 2.5 11.5 Disable Time 3.3 2.5 8.0 11.0 2.5 12.0 G to An or Bn 5.0 1.5 5.0 7.5 1.5 8.0 Disable Time 3.3 2.5 8.0 11.0 2.5 12.0 G to An or Bn 5.0 1.5 5.0 7.5 1.5 8.0 Enable Time 3.3 4.5 11.0 15.5 4.5 17.0 DIR to An or Bn 5.0 3.0 8.5 11.0 3.0 11.5 Enable Time 3.3 4.5 11.0 15.5 4.5 17.0 DIR to An or Bn 5.0 3.0 8.5 11.0 3.0 11.5 Disable Time 3.3 1.5 8.0 11.0 1.5 12.0 DIR to An or Bn 5.0 1.0 5.0 7.5 1.0 8.0 Disable Time 3.3 1.5 8.0 11.0 1.5 12.0 DIR to An or Bn 5.0 1.0 5.0 7.5 1.0 8.0 Output to Output Skew (Note 15) 3.3 1.0 1.5 1.5 5.0 0.5 1.0 1.0 Units ns ns ns ns ns (w/An or Bn HIGH or LOW) tPHL ns (w/An or Bn HIGH or LOW) tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tOS ns ns ns ns ns ns ns ns ns Note 14: Voltage Range 3.3 is 3.3V ± 0.3V. Voltage Range 5.0 is 5.0V ± 0.5V Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements for ACQ Symbol tS tH tW Parameter TA = +25°C VCC (Note 16) Typ TA = −40°C to +85°C Guaranteed Minimum Setup Time, HIGH or LOW 3.3 3.0 3.0 Bus to Clock 5.0 3.0 3.0 Hold Time, HIGH or LOW 3.3 1.5 1.5 Bus to Clock 5.0 1.5 1.5 Clock Pulse Width 3.3 4.0 4.0 HIGH or LOW 5.0 4.0 4.0 Note 16: Voltage Range 5.0 is 5.0V ± 0.5V Voltage Range 3.3 is 3.3V ± 0.3V www.fairchildsemi.com 6 Units ns ns ns Symbol Parameter tPLH Propagation Delay tPHL Clock to Bus tPLH Propagation Delay tPHL Bus to Bus tPLH Propagation Delay tPHL SBA or SAB to An or Bn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 17) Min Typ Max Min Max 5.0 2.5 8.5 10.5 2.5 11.0 ns 5.0 2.0 8.0 10.0 2.0 10.5 ns 5.0 2.5 8.5 10.5 2.5 11.0 ns 5.0 2.5 10.0 12.0 2.5 12.5 ns 5.0 1.0 7.0 8.5 1.0 9.0 ns 5.0 2.5 10.0 12.0 2.5 12.5 ns 5.0 1.0 7.0 8.5 1.0 9.0 ns 5.0 0.5 1.0 1.0 ns 5.0 1.0 1.5 1.5 ns (w/An or Bn HIGH or LOW) tPZH Enable Time tPZL G to An or Bn tPHZ Disable Time tPLZ G to An or Bn tPZH Enable Time tPZL DIR to An or Bn tPHZ Disable Time tPLZ DIR to An or Bn tOSHL Output to Output tOSLH Skew (Note 18) Select to Bus or Clock to Bus tOSHL Output to Output tOSLH Skew (Note 18) Bus to Bus Note 17: Voltage Range 5.0 is 5.0V ± 0.5V Note 18: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Not tested. AC Operating Requirements for ACTQ Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 19) tS Setup Time, HIGH or LOW Bus to Clock tH Hold Time, HIGH or LOW Bus to Clock Clock Pulse Width tW HIGH or LOW TA = −40°C to +85°C CL = 50 pF Typ Units Guaranteed Minimum 5.0 3.0 3.0 ns 5.0 1.5 1.5 ns 5.0 4.0 4.0 ns Note 19: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units 4.5 pF VCC = OPEN Input/Output Capacitance 15.0 pF VCC = 5.0V Power Dissipation Capacitance 90.0 pF VCC = 5.0V CIN Input Capacitance CI/O CPD 7 Conditions www.fairchildsemi.com 74ACQ646 • 74ACTQ646 AC Electrical Characteristics for ACTQ 74ACQ646 • 74ACTQ646 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. • First increase the input LOW voltage level, VIL,until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as V ILD. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as V IHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. FIGURE 5. Quiet Output Noise Voltage Waveforms Note 20: VOHV and VOLP are measured with respect to ground reference. Note 21: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 6. Simultaneous Switching Test Circuit www.fairchildsemi.com 8 74ACQ646 • 74ACTQ646 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 9 www.fairchildsemi.com 74ACQ646 • 74ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10