74ACT32701 16-BIT D-TYPE LATCH PULS 16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED) PRELIMINARY DATA ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4.8ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 4.5V BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V FUNCTION COMPATIBLE WITH SERIES 16373 AND 16245 (244) IMPROVED LATCH-UP IMMUNITY IMPROVED ESD IMMUNITY DESCRIPTION The 74ACT16244 is a low voltage CMOS 16-BIT D-TYPE LATCH and 16 BIT BUS TRANSCEIVER with 3-STATE output non inverting fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Both functions can be used as 16 bit or dual octal devices, so the 16 bit transceiver can be used ad 8 bit bus buffer plus 8 bit transceiver, or only 16 bit buffer in select direction. LFBGA96 (Top and Bottom view) ORDER CODES PACKAGE TRAY T&R LFBGA96 74ACT32701LB 74ACT32701LBR This device can be used to integrate in one chip the internal logic component required to STV0701 to work ad P.O.D. interface in Digital TV application. It is ideal for low power and high speed 4.5 to 5.5. applications. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. LOGIC DIAGRAM July 2003 1/9 This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice. 74ACT32701 PIN CONNECTION (Top view) TERMINAL ASSIGNMENT A B C D E F G H J K L M N P R T 6 1D2 1D4 1D6 1D8 2D2 2D4 2D6 2D7 3A2 3A4 3A6 3A8 4A2 4A4 4A6 4A7 5 1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D8 3A1 3A3 3A5 3A7 4A1 4A3 4A5 4A8 4 1LE GND VCC GND GND VCC GND 2LE 3G GND VCC GND GND VCC GND 4G 3 1OE GND VCC GND GND VCC GND 2OE 3DIR GND VCC GND GND VCC GND 4DIR 2 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2B8 3B1 3B3 3B5 3B7 4B1 4B3 4B5 4B8 1 1Q2 1Q4 1Q6 1Q8 2Q2 2Q4 2Q6 2B7 3B2 3B4 3B6 3B8 4B2 4B4 4B6 4B7 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE (each 8bit section of 16bit Latch) INPUTS OUTPUT OE LE D Q L L H H H L L L X H L Q0 H X X Z TRUTH TABLE (each 8bit section of 16bit Transceiver) INPUTS OPERATION G DIR L L H L H X X : Don‘t Care Z : High Impedance 2/9 B data to A bus A data to B bus Isolation 74ACT32701 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 400 mA -65 to +150 °C 300 °C VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) V Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit Supply Voltage 4.5 to 5.5 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature -40 to 85 °C 8 ns/V VCC dt/dv Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1) 1) VIN from 0.8V to 2.0V 3/9 74ACT32701 DC SPECIFICATIONS Test Condition Symbol Parameter VIH High Level Input Voltage VIL Low Level Input Voltage VOH High Level Output Voltage VOL Low Level Output Voltage TA = 25°C VCC (V) 4.5 5.5 4.5 5.5 Value Min. VO = 0.1 V or VCC-0.1V Typ. -40 to 85°C Max. 2.0 2.0 Min. Max. 2.0 2.0 0.8 0.8 VO = 0.1 V or VCC-0.1V Unit V 0.8 0.8 4.5 IO=-50 µA 4.4 4.49 4.4 5.5 IO=-50 µA 5.4 5.49 5.4 4.5 IO=-24 mA 3.86 3.76 5.5 IO=-24 mA 4.86 4.76 4.5 IO=50 µA 0.001 0.1 0.1 5.5 IO=50 µA 0.001 0.1 0.1 V 4.5 IO=24 mA 0.36 0.44 5.5 IO=24 mA 0.36 0.44 V 5.5 VI = VCC or GND ± 0.1 ±1 µA IOZ High Impedance Output Leakage Current 5.5 VI = VIH or VIIL VO = VCC or GND ± 0.5 ±5 µA ICCT Max ICC/Input 5.5 VI = VCC - 2.1V 1 mA ICC Quiescent Supply Current 5.5 VI = VCC or GND 8 80 µA IOLD Dynamic Output Current (note 1, 2) 5.5 II IOHD Input Leakage Current 0.9 VOLD = 1.65 V max 75 mA VOHD = 3.85 V min. -75 mA -40 to 85°C Unit 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol tPLH Parameter Propagation Delay Time tPHL tPZL Output Enable Time tPZH tPLZ Output Disable Time tPHZ (*) Voltage range is 5.0V ± 0.5V 4/9 VCC (V) 5.0(*) 5.0(*) 5.0(*) Value TA = 25°C Min. Typ. Max. Min. Max. 2.0 3.3 5.0 2.0 6.0 3.0 4.8 6.5 3.0 8.0 4.0 6.5 8.7 4.0 9.7 3.0 5.5 7.7 3.0 8.8 4.0 6.0 8.0 4.0 9.2 3.0 4.6 6.4 3.0 7.3 ns ns ns 74ACT32701 CAPACITIVE CHARACTERISTICS Test Condition Symbol CIN COUT CPD Parameter Value TA = 25°C VCC (V) Min. Typ. -40 to 85°C Max. Min. Unit Max. Input Capacitance 5.0 3.6 pF Output Capacitance 5.0 11 pF Power Dissipation Capacitance (note 1) 5.0 42 pF fIN = 10MHz 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) TEST CIRCUIT Test Switch tPLH, tPHL Open tPZL, tPLZ 2VCC tPZH, tPHZ GND CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) 5/9 74ACT32701 WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 6/9 74ACT32701 LFBGA96 MECHANICAL DAT A mm. mils DIM. MIN. TYP MAX. MIN. TYP. MAX. A 13.40 13.60 527.5 535.4 B 5.40 5.60 212.6 220.5 C 1.6 63.0 D 0.5 19.7 E 0.8 31.5 F 0.85 33.5 7/9 74ACT32701 Tape & Reel LFBGA96 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 30.4 0.519 1.196 Ao 5.8 6.0 0.228 0.236 Bo 13.8 14.0 0.543 0.551 Ko 2.1 2.3 0.083 0.091 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 8/9 74ACT32701 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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