INTEGRATED CIRCUITS DATA SHEET 74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state Product specification Supersedes data of 1999 Sep 27 2003 Dec 08 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 The 74AHC/AHCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Balanced propagation delays The 74AHC/AHCT573 consists of eight D-type transparent latches with 3-state true outputs. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. • All inputs have Schmitt-trigger actions • Common 3-state output enable input • Functionally identical to the 74AHC/AHCT563 and 74AHC/AHCT373 • Inputs accepts voltages higher than VCC When pin LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74AHC/AHCT573 is functionally identical to the 74AHC/AHCT533, 74AHC/AHCT563 and 74AHC/AHCT373, but the 74AHC/AHCT533 and 74AHC/AHCT563 have inverted outputs and the 74AHC/AHCT563 and 74AHC/AHCT373 have a different pin arrangement. The 74AHC/AHCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC AHCT tPHL/tPLH propagation delay Dn to Qn; LE to Qn CL = 15 pF; VCC = 5 V 3.9 3.5 ns CI input capacitance VI = VCC or GND 3.0 3.0 pF CO output capacitance 4.0 4.0 pF CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 12 18 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2003 Dec 08 2 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 FUNCTION TABLE See note 1. INPUT OUTPUT OE LE Dn INTERNAL LATCH Enable and read register (transparent mode) L H L L L L H H H H Latch and read register L L I L L L L h H H H L l L Z H L h H Z OPERATING MODE Latch register and disable outputs Q0 to Q7 Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER PINS PACKAGE MATERIAL CODE 74AHC573D 20 SO20 plastic SOT163-1 74AHCT573D 20 SO20 plastic SOT163-1 74AHC573PW 20 TSSOP20 plastic SOT360-1 74AHCT573PW 20 TSSOP20 plastic SOT360-1 2003 Dec 08 3 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 PINNING PIN SYMBOL DESCRIPTION 1 OE 3-state output enable input (active LOW) 2 D0 data input 3 D1 data input 4 D2 data input 5 D3 data input 6 D4 data input 7 D5 8 handbook, halfpage OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 data input D2 4 17 Q2 D6 data input D3 5 9 D7 data input D4 6 15 Q4 10 GND ground (0 V) D5 7 14 Q5 11 LE latch enable input (active HIGH) D6 8 13 Q6 12 Q7 3-state latch output D7 9 12 Q7 13 Q6 3-state latch output 14 Q5 3-state latch output GND 10 11 LE 15 Q4 3-state latch output 16 Q3 3-state latch output 17 Q2 3-state latch output 18 Q1 3-state latch output 19 Q0 3-state latch output 20 VCC supply voltage MNA388 Fig.1 Pin configuration SO20 and TSSSOP20. handbook, halfpage 11 handbook, halfpage 2 3 4 5 6 7 8 9 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 Q6 Q7 D7 11 1 LE D6 16 Q3 573 C1 EN 19 18 2 17 19 1D 3 18 4 17 14 5 16 13 6 15 12 7 14 8 13 9 12 16 15 OE 1 MNA389 MNA390 Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fi 3 L 2003 Dec 08 4 i di Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 handbook, halfpage 2 D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 LATCH 1 to 8 Q3 16 3-STATE OUTPUTS Q4 15 11 LE 1 OE MNA391 Fig.4 Functional diagram. D0 D1 Q D D2 Q D D3 Q D D4 Q D D5 Q D D6 Q D D7 Q D Q D LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MNA392 Fig.5 Logic diagram. 2003 Dec 08 5 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 V VCC supply voltage 2.0 5.0 5.5 VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature see DC and AC −40 characteristics per device −40 +25 +85 −40 +25 +85 °C +25 +125 −40 +25 +125 °C VCC = 3.3 V ±0.3 V − − 100 − − − ns/V VCC = 5 V ±0.5 V − − 20 − − 20 ns/V tr, tf input rise and fall rates LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK input diode current VI < −0.5 V; note 1 − −20 mA IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA IO output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC VCC or GND current − ±75 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 500 Tamb = −40 to +125 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO20packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. 2003 Dec 08 6 mW Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 DC CHARACTERISTICS 74AHC type At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = 25 °C VIH VIL VOH VOL 2.0 1.5 − − V 3.0 2.1 − − V 5.5 3.85 − − V 2.0 − − 0.5 V 3.0 − − 0.9 V 5.5 − − 1.65 V IO = −50 µA 2.0 1.9 2.0 − V IO = −50 µA 3.0 2.9 3.0 − V IO = −50 µA 4.5 4.4 4.5 − V IO = −4.0 mA 3.0 2.58 − − V IO = −8.0 mA 4.5 3.94 − − V IO = 50 µA 2.0 − 0 0.1 V IO = 50 µA 3.0 − 0 0.1 V IO = 50 µA 4.5 − 0 0.1 V IO = 4.0 mA 3.0 − − 0.36 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 8.0 mA 4.5 − − 0.36 V ILI input leakage current VI = VCC or GND 5.5 − − 0.1 µA IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±0.25 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 4.0 µA CI input capacitance − 3 10 pF 2003 Dec 08 − 7 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C VIH VIL VOH VOL 2.0 1.5 − − V 3.0 2.1 − − V 5.5 3.85 − − V 2.0 − − 0.5 V 3.0 − − 0.9 V 5.5 − − 1.65 V IO = −50 µA 2.0 1.9 − − V IO = −50 µA 3.0 2.9 − − V IO = −50 µA 4.5 4.4 − − V IO = −4.0 mA 3.0 2.48 − − V IO = −8.0 mA 4.5 3.8 − − V IO = 50 µA 2.0 − − 0.1 V IO = 50 µA 3.0 − − 0.1 V IO = 50 µA 4.5 − − 0.1 V IO = 4.0 mA 3.0 − − 0.44 V IO = 8.0 mA 4.5 − − 0.44 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VCC or GND 5.5 − − 1.0 µA IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±2.5 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA CI input capacitance − − 10 pF 2003 Dec 08 − 8 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH VOL 2.0 1.5 − − V 3.0 2.1 − − V 5.5 3.85 − − V 2.0 − − 0.5 V 3.0 − − 0.9 V 5.5 − − 1.65 V IO = −50 µA 2.0 1.9 1.9 − V IO = −50 µA 3.0 2.9 2.9 − V IO = −50 µA 4.5 4.4 4.4 − V IO = −4.0 mA 3.0 2.48 2.48 − V IO = −8.0 mA 4.5 3.8 3.8 − V IO = 50 µA 2.0 − − − V IO = 50 µA 3.0 − − 0.1 V IO = 50 µA 4.5 − − 0.1 V IO = 4.0 mA 3.0 − − 0.1 V IO = 8.0 mA 4.5 − − 0.44 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VCC or GND 5.5 − − 2.0 µA IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND 5.5 − − ±10.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 80 µA CI input capacitance − − 10 pF 2003 Dec 08 − 9 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 74AHCT type At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = 25 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage IO = −50 µA 4.5 4.4 4.5 − V IO = −8.0 mA 4.5 3.94 − − V IO = 50 µA 4.5 − 0 0.1 V IO = 8.0 mA 4.5 − − 0.36 V VOL VI = VIH or VIL LOW-level output voltage VI = VIH or VIL ILI input leakage current VI = VIH or VIL 5.5 − − 0.1 µA IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±0.25 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 4.0 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 mA CI input capacitance − − 3 10 pF 4.5 to 5.5 2.0 − − V 4.5 to 5.5 − − 0.8 V IO = −50 µA 4.5 4.4 − − V IO = −8.0 mA 4.5 3.8 − − V 4.5 − − 0.1 V Tamb = −40 to +85 °C VIH HIGH-level input voltage VIL LOW-level input voltage VOH HIGH-level output voltage VOL VI = VIH or VIL LOW-level output voltage VI = VIH or VIL IO = 50 µA IO = 8.0 mA 4.5 − − 0.44 V ILI input leakage current VI = VIH or VIL 5.5 − − 1.0 µA IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±2.5 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.5 mA CI input capacitance − − − 10 pF 2003 Dec 08 10 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage IO = −50 µA 4.5 4.4 − − V IO = −8.0 mA 4.5 3.70 − − V IO = 50 µA 4.5 − − 0.1 V IO = 8.0 mA 4.5 − − 0.55 V VOL VI = VIH or VIL LOW-level output voltage VI = VIH or VIL ILI input leakage current VI = VIH or VIL 5.5 − − 2.0 µA IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±10.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 80 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.5 mA CI input capacitance − − − 10 pF 2003 Dec 08 11 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 AC CHARACTERISTICS 74AHC573 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT CL (pF) VCC = 3.0 to 3.6 V Tamb = 25 °C; note 1 tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 15 − 5.5 11.0 ns propagation delay LE to Qn see Figs 7 and 10 15 − 5.8 11.9 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 15 − 5.8 11.5 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 15 − 6.8 11.0 ns tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 50 − 7.8 14.5 ns propagation delay LE to Qn see Figs 7 and 10 50 − 8.3 15.4 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 50 − 8.3 15.0 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 50 − 9.7 14.5 ns tW enable pulse width HIGH see Figs 7 and 10 50 5.0 − − ns tsu set-up time Dn to LE see Fig.8 50 3.5 − − ns th hold time Dn to LE see Fig.8 50 1.5 − − ns propagation delay Dn to Qn see Figs 6 and 10 15 1.0 − 13.0 ns propagation delay LE to Qn see Figs 7 and 10 15 1.0 − 14.0 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 15 1.0 − 13.5 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 15 1.0 − 13.0 ns tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 50 1.0 − 16.5 ns Tamb = −40 to +85 °C tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 50 1.0 − 17.5 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 50 1.0 − 17.0 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 50 1.0 − 16.5 ns tW enable pulse width HIGH see Figs 7 and 10 50 5.0 − − ns tsu set-up time Dn to LE see Fig.8 50 3.5 − − ns th hold time Dn to LE see Fig.8 50 1.5 − − ns 2003 Dec 08 12 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT CL (pF) Tamb = −40 to +125 °C propagation delay Dn to Qn see Figs 6 and 10 15 1.0 − 14.0 ns propagation delay LE to Qn see Figs 7 and 10 15 1.0 − 15.0 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 15 1.0 − 14.5 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 15 1.0 − 14.0 ns tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 50 1.0 − 18.5 ns tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 50 1.0 − 19.5 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 50 1.0 − 19.0 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 50 1.0 − 18.5 ns tW enable pulse width HIGH see Figs 7 and 10 50 5.0 − − ns tsu set-up time Dn to LE see Fig.8 50 3.5 − − ns th hold time Dn to LE see Fig.8 50 1.5 − − ns propagation delay Dn to Qn see Figs 6 and 10 15 − 3.9 6.8 ns propagation delay LE to Qn see Figs 7 and 10 15 − 4.2 7.7 ns VCC = 4.5 to 5.5 V Tamb = 25 °C; note 2 tPHL/tPLH tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 15 − 4.4 7.7 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 15 − 4.6 7.7 ns tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 50 − 5.5 8.8 ns propagation delay LE to Qn see Figs 7 and 10 50 − 5.9 9.7 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 50 − 6.3 9.7 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 50 − 7.4 9.7 ns tW enable pulse width HIGH see Figs 7 and 10 50 5.0 − − ns tsu set-up time Dn to LE see Fig.8 50 3.5 − − ns th hold time Dn to LE see Fig.8 50 1.5 − − ns propagation delay Dn to Qn see Figs 6 and 10 15 1.0 − 8.0 ns propagation delay LE to Qn see Figs 7 and 10 15 1.0 − 9.0 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 15 1.0 − 9.0 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 15 1.0 − 9.0 ns tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 50 1.0 − 10.0 ns propagation delay LE to Qn see Figs 7 and 10 50 1.0 − 11.0 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 50 1.0 − 11.0 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 50 1.0 − 11.0 ns tW enable pulse width HIGH see Figs 7 and 10 50 5.0 − − ns tsu set-up time Dn to LE see Fig.8 50 3.5 − − ns th hold time Dn to LE see Fig.8 50 1.5 − − ns Tamb = −40 to +85 °C tPHL/tPLH 2003 Dec 08 13 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT CL (pF) Tamb = −40 to +125 °C propagation delay Dn to Qn see Figs 6 and 10 15 1.0 − 8.5 ns propagation delay LE to Qn see Figs 7 and 10 15 1.0 − 10.0 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 15 1.0 − 10.0 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 15 1.0 − 10.0 ns tPHL/tPLH propagation delay Dn to Qn2 see Figs 6 and 10 50 1.0 − 11.0 ns tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 50 1.0 − 12.5 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 50 1.0 − 12.5 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 50 1.0 − 12.5 ns tW enable pulse width HIGH see Figs 7 and 10 50 5.0 − − ns tsu set-up time Dn to LE see Fig.8 50 3.5 − − ns th hold time Dn to LE see Fig.8 50 1.5 − − ns Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. 2003 Dec 08 14 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 74AHCT573 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT CL (pF) VCC = 4.5 to 5.5 V; note 1 Tamb = 25 °C propagation delay Dn to Qn see Figs 6 and 10 15 − 3.5 5.5 ns propagation delay LE to Qn see Figs 7 and 10 15 − 3.9 6.0 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 15 − 4.1 6.5 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 15 − 4.5 6.5 ns tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 50 − 4.9 7.5 ns propagation delay LE to Qn see Figs 7 and 10 50 − 5.5 8.5 ns tPHL/tPLH tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 50 − 5.9 8.5 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 50 − 6.4 9.0 ns tW enable pulse width HIGH see Figs 7 and 9 50 5.0 − − ns tsu set-up time Dn to LE see Fig.8 50 3.5 − − ns th hold time Dn to LE see Fig.8 50 1.5 − − ns propagation delay Dn to Qn see Figs 6 and 10 15 1 − 6.5 ns propagation delay LE to Qn see Figs 7 and 10 15 1 − 7.0 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 15 1 − 7.5 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 15 1 − 7.5 ns tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 50 1 − 8.5 ns propagation delay LE to Qn see Figs 7 and 10 50 1 − 9.5 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 50 1 − 10.0 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 50 1 − 10.0 ns tW enable pulse width HIGH see Figs 7 and 9 50 5.0 − − ns tsu set-up time Dn to LE see Fig.8 50 3.5 − − ns th hold time Dn to LE see Fig.8 50 1.5 − − ns Tamb = −40 to +85 °C tPHL/tPLH 2003 Dec 08 15 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT CL (pF) Tamb = −40 to +125 °C propagation delay Dn to Qn see Figs 6 and 10 15 1 − 7.0 ns propagation delay LE to Qn see Figs 7 and 10 15 1 − 7.5 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 15 1 − 8.5 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 15 1 − 8.5 ns tPHL/tPLH propagation delay Don to Qn see Figs 6 and 10 50 1 − 9.5 ns tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 50 1 − 11.0 ns tPZH/tPZL propagation delay OE to Qn see Figs 9 and 10 50 1 − 11.0 ns tPHZ/tPLZ propagation delay OE to Qn see Figs 9 and 10 50 1 − 11.5 ns tW enable pulse width HIGH see Figs 7 and 9 50 5.0 − − ns tsu set-up time Dn to LE see Fig.8 50 3.5 − − ns th hold time Dn to LE see Fig.8 50 1.5 − − ns Note 1. Typical values at VCC = 5.0 V. 2003 Dec 08 16 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 AC WAVEFORMS VI handbook, halfpage VM Dn input GND tPLH tPHL VOH VM Qn output VOL FAMILY VI INPUT REQUIREMENTS VM INPUT MNA811 VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.6 The data input (Dn) to output (Qn) propagation delays. 1/fmax handbook, full pagewidth VI LE input VM GND tW t PHL t PLH VOH VM Qn output VOL FAMILY VI INPUT REQUIREMENTS VM INPUT MNA812 VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.7 The latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays. 2003 Dec 08 17 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 VI handbook, full pagewidth VM Dn input GND th th t su t su VI LE input VM GND VI INPUT REQUIREMENTS FAMILY MNA814 VM INPUT AHC GND to VCC 50% VCC AHCT GND to 3.0 V 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.8 Data set-up and hold times for the Dn input to the LE input. VI handbook, full pagewidth VM(1) OE input GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM(2) VOL + 0.3 V VOL tPHZ tPZH VOH VOH − 0.3 V output HIGH-to-OFF OFF-to-HIGH VM(2) GND outputs enabled outputs disabled outputs enabled MNA450 FAMILY VI INPUT REQUIREMENTS VM(1) INPUT VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.9 The 3-state enable and disable times. 2003 Dec 08 18 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 S1 handbook, full pagewidth VCC PULSE GENERATOR RL = VI VCC open GND 1 kΩ VO D.U.T. CL RT MNA183 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.10 Load circuitry for switching times. 2003 Dec 08 19 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 2003 Dec 08 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 20 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 2003 Dec 08 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 21 o Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Dec 08 22 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R44/02/pp23 Date of release: 2003 Dec 08 Document order number: 9397 750 12156