INTEGRATED CIRCUITS DATA SHEET 74AHC2G125; 74AHCT2G125 Bus buffer/line driver; 3-state Product specification 2004 Jan 13 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 FEATURES DESCRIPTION • Symmetrical output impedance The 74AHC2G/AHCT2G125 is a high-speed Si-gate CMOS device. • High noise immunity • ESD protection: The 74AHC2G/AHCT2G125 provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH at pin nOE causes the output to assume a high-impedance OFF-state. – HBM EIA/JESD22-A114-A exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V – CDM EIA/JESD22-C101 exceeds 1000 V. • Low power dissipation • Balanced propagation delays • SOT505-2 and SOT765-1 package • Specified from−40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC2G tPHL/tPLH propagation delay nA to nY CL = 15 pF; VCC = 5 V CI input capacitance CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 9 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑(CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. 2004 Jan 13 2 AHCT2G 3.4 3.4 ns 1.5 1.5 pF 11 pF Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 FUNCTION TABLE See note 1. INPUT OUTPUT nOE nA nY L L L L H H H X Z Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING 74AHC2G125DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 A25 74AHCT2G125DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 C25 74AHC2G125DC −40 to +125 °C 8 VSSOP8 plastic SOT765-1 A25 74AHCT2G125DC −40 to +125 °C 8 VSSOP8 plastic SOT765-1 C25 PINNING PIN SYMBOL DESCRIPTION 1 1OE output enable input (active LOW) 2 1A data input 3 2Y data output 4 GND ground (0 V) 5 2A data input 6 1Y data output 7 2OE output enable input (active LOW) 8 VCC supply voltage 2004 Jan 13 3 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 handbook, halfpage handbook, halfpage 1OE 1 2 1A 1 1OE 5 2A 7 2OE 1Y 6 2Y 3 8 VCC 1A 2 7 2OE 125 2Y 3 6 1Y GND 4 5 2A MCE184 MCE185 Fig.1 Pin configuration. handbook, halfpage Fig.2 Logic symbol. 2 6 1 handbook, halfpage 1OE nY nA 5 3 7 nOE 2OE MCE187 MCE186 Fig.3 IEC logic symbol. 2004 Jan 13 Fig.4 Logic diagram. 4 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 RECOMMENDED OPERATING CONDITIONS 74AHC2G125 SYMBOL PARAMETER 74AHCT2G125 CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 V VCC supply voltage 2.0 5.0 5.5 VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature −40 +25 +125 −40 +25 +125 °C tr, tf input rise and fall times see DC and AC characteristics per device VCC = 3.3 ± 0.3 V − − 100 − − − ns/V VCC = 5 ± 0.5 V − − 20 − − 20 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK input diode current − −20 mA IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA IO output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC, IGND VCC or GND current − ±75 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 250 VI < −0.5 V Tamb = −40 to +125 °C Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2004 Jan 13 5 mW Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 DC CHARACTERISTICS Type 74AHC2G125 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = 25 °C VIH VIL VOH VOL HIGH-level input voltage 2.0 − − V 3.0 2.1 − − V 5.5 3.85 − − V 2.0 − − 0.5 V 3.0 − − 0.9 V 5.5 − − 1.65 V IO = −50 µA 2.0 1.9 2.0 − V IO = −50 µA 3.0 2.9 3.0 − V IO = −50 µA 4.5 4.4 4.5 − V IO = −4.0 mA 3.0 2.58 − − V IO = −8.0 mA 4.5 3.94 − − V IO = 50 µA 2.0 − 0 0.1 V IO = 50 µA 3.0 − 0 0.1 V IO = 50 µA 4.5 − 0 0.1 V IO = 4.0 mA 3.0 − − 0.36 V LOW-level input voltage HIGH-level output voltage 1.5 VI = VIH or VIL LOW-level output voltage VI = VIH or VIL IO = 8.0 mA 4.5 − − 0.36 V IOZ 3-state output OFF-state current VI = VCC or GND 5.5 − − 0.25 µA ILI input leakage current VI = VCC or GND 5.5 − − 0.1 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 1.0 µA CI input capacitance − − 1.5 10 pF 2004 Jan 13 6 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C VIH VIL VOH VOL 2.0 1.5 − − V 3.0 2.1 − − V 5.5 3.85 − − V 2.0 − − 0.5 V 3.0 − − 0.9 V 5.5 − − 1.65 V IO = −50 µA 2.0 1.9 − − V IO = −50 µA 3.0 2.9 − − V IO = −50 µA 4.5 4.4 − − V IO = −4.0 mA 3.0 2.48 − − V IO = −8.0 mA 4.5 3.8 − − V IO = 50 µA 2.0 − − 0.1 V IO = 50 µA 3.0 − − 0.1 V IO = 50 µA 4.5 − − 0.1 V IO = 4.0 mA 3.0 − − 0.44 V IO = 8.0 mA 4.5 − − 0.44 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL IOZ 3-state output OFF-state current VI = VCC or GND 5.5 − − 2.5 µA ILI input leakage current VI = VCC or GND 5.5 − − 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 10 µA CI input capacitance − − − 10 pF 2004 Jan 13 7 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH VOL 2.0 1.5 − − V 3.0 2.1 − − V 5.5 3.85 − − V 2.0 − − 0.5 V 3.0 − − 0.9 V 5.5 − − 1.65 V IO = −50 µA 2.0 1.9 − − V IO = −50 µA 3.0 2.9 − − V IO = −50 µA 4.5 4.4 − − V IO = −4.0 mA 3.0 2.40 − − V IO = −8.0 mA 4.5 3.70 − − V IO = 50 µA 2.0 − − 0.1 V IO = 50 µA 3.0 − − 0.1 V IO = 50 µA 4.5 − − 0.1 V IO = 4.0 mA 3.0 − − 0.55 V IO = 8.0 mA 4.5 − − 0.55 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL IOZ 3-state output OFF-state current VI = VCC or GND 5.5 − − 10 µA ILI input leakage current VI = VCC or GND 5.5 − − 2.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA CI input capacitance − − − 10 pF 2004 Jan 13 8 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 Type 74AHCT2G125 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC (V) OTHER Tamb = 25 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage VOL LOW-level output voltage VI = VIH or VIL IO = −50 µA 4.5 4.4 4.5 − V IO = −8.0 mA 4.5 3.94 − − V VI = VIH or VIL IO = 50 µA 4.5 − 0 0.1 V IO = 8.0 mA 4.5 − − 0.36 V 5.5 − − 0.25 µA IOZ 3-state output OFF-state current VI = VCC or GND ILI input leakage current VI = VIH or VIL 5.5 − − 0.1 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 1.0 µA ∆ICC additional quiescent supply VI = 3.4 V; other inputs at current per input pin VCC or GND; IO = 0 5.5 − − 1.35 mA CI input capacitance − 1.5 10 pF Tamb = −40 to +85 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage IO = −50 µA 4.5 4.4 − − V IO = −8.0 mA 4.5 3.8 − − V IO = 50 µA 4.5 − − 0.1 V IO = 8.0 mA 4.5 − − 0.44 V VOL LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IOZ 3-state output OFF-state current VI = VCC or GND 5.5 − − 2.5 µA ILI input leakage current VI = VIH or VIL 5.5 − − 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 10 µA ∆ICC additional quiescent supply VI = 3.4 V; other inputs at current per input pin VCC or GND; IO = 0 5.5 − − 1.5 mA CI input capacitance − − − 10 pF 2004 Jan 13 9 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage IO = −50 µA 4.5 4.4 − − V IO = −8.0 mA 4.5 3.70 − − V IO = 50 µA 4.5 − − 0.1 V IO = 8.0 mA 4.5 − − 0.55 V VOL LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IOZ 3-state output OFF-state current VI = VCC or GND 5.5 − − 10 µA ILI input leakage current VI = VIH or VIL 5.5 − − 2.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA ∆ICC additional quiescent supply VI = 3.4 V; other inputs at current per input pin VCC or GND; IO = 0 5.5 − − 1.5 mA CI input capacitance − − − 10 pF 2004 Jan 13 10 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 AC CHARACTERISTICS Type 74AHC2G125 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT CL (pF) Tamb = 25 °C VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 15 − 4.7 8.0 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 15 − 5.0 8.0 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 15 − 6.0 9.7 ns tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 50 − 6.6 11.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 50 − 6.9 11.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 50 − 8.3 13.2 ns VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 15 − 3.4 5.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 15 − 3.6 5.1 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 15 − 4.1 6.8 ns tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 50 − 4.8 7.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 50 − 4.9 7.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 50 − 5.7 8.8 ns Tamb = −40 to +85 °C VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 15 1.0 − 9.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 9.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 11.5 ns tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 50 1.0 − 13.0 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 13.0 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 15.0 ns VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 15 1.0 − 6.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 6.0 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 8.0 ns tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 50 1.0 − 8.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 8.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 10.0 ns 2004 Jan 13 11 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT CL (pF) Tamb = −40 to +125 °C VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 15 1.0 − 11.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 11.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 12.5 ns tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 50 1.0 − 14.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 14.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 16.5 ns VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 15 1.0 − 7.0 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 6.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 8.5 ns tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 50 1.0 − 9.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 9.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 11.0 ns Notes 1. All typical values are measured at VCC = 3.3 V. 2. All typical values are measured at VCC = 5.0 V. Type 74AHCT2G125 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT CL (pF) Tamb = 25 °C VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 15 − 3.4 5.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 15 − 3.9 5.1 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 15 − 4.5 6.8 ns tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 50 − 4.8 7.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 50 − 5.1 7.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 50 − 6.1 8.8 ns Tamb = −40 to +85 °C VCC = 4.5 to 5.5 V tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 15 1.0 − 6.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 6.0 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 8.0 ns tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 50 1.0 − 8.5 ns 2004 Jan 13 12 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT CL (pF) tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 8.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 10.0 ns Tamb = −40 to +125 °C VCC = 4.5 to 5.5 V tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 15 1.0 − 6.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 6.0 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 15 1.0 − 8.0 ns tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 50 1.0 − 8.5 ns tPZH/tPZL propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 8.5 ns tPHZ/tPLZ propagation delay nOE to nY see Figs 6 and 7 50 1.0 − 10.0 ns Note 1. All typical values are measured at VCC = 5.0 V. AC WAVEFORMS handbook, halfpage VI VM nA input GND tPHL tPLH VOH VM nY output VOL FAMILY VI INPUT REQUIREMENTS MNA230 VM INPUT VM OUTPUT AHC2G125 GND to VCC 50% VCC 50% VCC AHCT2G125 GND to 3.0 V 1.5 V 50% VCC Fig.5 The input (nA) to output (nY) propagation delays. 2004 Jan 13 13 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 VI handbook, full pagewidth VM OE input GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VOL +0.3 V tPHZ tPZH VOH −0.3 V output HIGH-to-OFF OFF-to-HIGH VM GND output enabled output enabled output disabled MNA122 FAMILY VI INPUT REQUIREMENTS VM INPUT VM OUTPUT AHC2G125 GND to VCC 50% VCC 50% VCC AHCT2G125 GND to 3.0 V 1.5 V 50% VCC Fig.6 The 3-state enable and disable times. S1 handbook, full pagewidth VCC PULSE GENERATOR VI RL = 1000 Ω VO VCC open GND D.U.T. CL RT MNA232 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit: RL = load resistance. CL = load capacitance including jig and probe capacitance (see Chapter “AC characteristics” for the value). RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2004 Jan 13 14 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 PACKAGE OUTLINES TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 2004 Jan 13 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- 15 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 2004 Jan 13 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 16 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74AHC2G125; 74AHCT2G125 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Jan 13 17 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R44/01/pp18 Date of release: 2004 Jan 13 Document order number: 9397 750 12426