INTEGRATED CIRCUITS 74ALVCH16841 20-bit bus interface D-type latch (3-State) Product specification IC24 Data Handbook 1998 Jul 27 Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) FEATURES 74ALVCH16841 PIN CONFIGURATION • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • Wide supply voltage range of 1.2V to 3.6V • CMOS low power consumption • Direct interface with TTL levels • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and GND pins for minimum noise and ground bounce • Current drive ±24 mA at 3.0 V • All inputs have bus hold circuitry • Output drive capability 50Ω transmission lines @ 85°C • 3-State non-inverting outputs for bus oriented applications DESCRIPTION The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appears at the outputs. When nOE is High the outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 1OE 1 56 1LE 1Q0 2 55 1D0 1Q1 3 54 1D1 GND 4 53 GND 1Q2 5 52 1D2 1Q3 6 51 1D3 VCC 7 50 VCC 1Q4 8 49 1D4 1Q5 9 48 1D5 1Q6 10 47 1D6 GND 11 46 GND 1Q7 12 45 1D7 1Q8 13 44 1D8 1Q9 14 43 1D9 2Q0 15 42 2D0 2Q1 16 41 2D1 2Q2 17 40 2D2 GND 18 39 GND 2Q3 19 38 2D3 2Q4 20 37 2D4 2Q5 21 36 2D5 VCC 22 35 VCC 2Q6 23 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2Q9 27 30 2D9 2OE 28 29 2LE SA00076 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns PARAMETER SYMBOL Propagation delay tPHL/tPLH nDn to nQn Propagation delay tPHL/tPLH nLE to nQn CI Input capacitance CPD Power dissipation dissi ation capacitance ca acitance per er buffer CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF VI = GND to VCC1 Outputs enabled Outputs disabled TYPICAL 2.5 2.4 2.5 2.4 5.0 19 3 UNIT ns ns pF pF F NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES 56-Pin Plastic TSSOP Type II 1998 Jul 27 TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER –40°C to +85°C 74ALVCH16841 DGG ACH16841 DGG SOT364-1 2 853-2093 19785 Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) PIN DESCRIPTION 74ALVCH16841 LOGIC SYMBOL (IEEE/IEC) PIN NUMBER SYMBOL 1 1OE FUNCTION Output enable inputs (active-LOW) Latch enable inputs (active HIGH) 56 1LE 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 1D0 – 1D9 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 1Q0 – 1Q9 4, 11, 18, 25, 32, 39, 46, 53 GND 1OE 1 1LE 56 C1 28 EN4 29 C3 2OE 2LE Data inputs 1D0 7, 22, 35, 50 Data outputs Positive supply voltage VCC 28 29 1D2 52 5 1D3 51 6 1D4 49 8 1D5 48 9 1Q5 47 10 1Q6 2OE Output enable inputs (active-LOW) 1D7 45 12 1D8 44 13 2LE Latch enable inputs (active HIGH) 43 14 Data inputs 2D0 42 2D1 2D2 2D0 – 2D9 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 2Q0 – 2Q9 1D9 Data outputs L H L X Z = = = = H H H H L L X Q0 H X X High voltage level Low voltage level Don’t care High impedance “off” state 2Q2 38 19 37 20 36 21 34 23 33 24 2Q7 2D8 31 26 2Q8 2D9 30 27 2Q9 54 Z LOGIC DIAGRAM nD0 D 52 51 49 48 47 1D0 1D1 1D2 1D3 1D4 1D5 1D6 56 1LE 1 1OE 4∇ 3D 45 44 43 1D7 1D8 LE 1D9 nLE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 nOE 2 3 5 6 8 9 10 12 13 14 42 41 40 38 37 36 34 33 31 30 nQ0 2D0 2D1 2D2 2D3 2D4 2D5 2D6 29 2LE 28 2OE 2D7 2D8 SH00151 2D9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 15 16 17 19 20 21 23 24 26 27 SH00023 1998 Jul 27 2Q3 2Q4 2Q5 2Q6 SH00152 LOGIC SYMBOL 55 1Q9 2Q1 2D7 L 1Q8 17 Q L 1Q7 40 2D6 L 1Q4 2Q0 OUTPUT Dx 1Q3 16 2D5 LE 1Q2 41 2D4 INPUTS 1Q1 15 2D3 FUNCTION TABLE 1Q0 3 1D6 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 nOE 2 2∇ 1D 54 1D1 Ground (0V) 55 EN2 3 Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) 74ALVCH16841 BUS HOLD CIRCUIT VCC Data Input To internal circuit SW00044 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN MAX DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) 2.3 2.7 DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) 3.0 3.6 UNIT V VI DC Input voltage range 0 VCC V VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V Tamb Operating free-air temperature range tr, tf Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK PARAMETER CONDITIONS DC supply voltage DC input diode current VI 0 For control pins1 VI DC in input ut voltage IOK DC output diode current VO VCC or VO 0 VO DC output voltage Note 1 IO DC output source or sink current VO = 0 to VCC IGND, ICC Tstg PTOT For data inputs1 DC VCC or GND current Storage temperature range Power dissipation per package –plastic medium-shrink (SSOP) –plastic thin-medium-shrink (TSSOP) For temperature range: –40 to +125 °C above +55°C derate linearly with 11.3 mW/K above +55°C derate linearly with 8 mW/K NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jul 27 4 RATING UNIT –0.5 to +4.6 V –50 mA –0.5 to +4.6 –0.5 to VCC +0.5 50 V mA –0.5 to VCC +0.5 V 50 mA 100 mA –65 to +150 °C 850 600 mW Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) 74ALVCH16841 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VIH HIGH level Input voltage VIL LOW level Input voltage VOH O HIGH level output voltage TEST CONDITIONS Temp = -40°C to +85°C MIN TYP1 VCC = 2.3 to 2.7V 1.7 1.2 VCC = 2.7 to 3.6V 2.0 1.5 UNIT MAX V VCC = 2.3 to 2.7V 1.2 0.7 VCC = 2.7 to 3.6V 1.5 0.8 V 3 to 3 6V; VI = VIH or VIL; IO = –100µA 100µA VCC = 2 2.3 3.6V; 02 VCC0.2 VCC VCC = 2.3V; VI = VIH or VIL; IO = –6mA VCC0.3 VCC0.08 VCC = 2.3V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC0.26 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC0.5 VCC0.14 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC0.09 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC1.0 VCC0.28 V VCC = 2 2.3 3 to 3 3.6V; 6V; VI = VIH or VIL; IO = 100µA GND 0 20 0.20 V VCC = 2.3V; VI = VIH or VIL; IO = 6mA 0.07 0.40 V VCC = 2.3V; VI = VIH or VIL; IO = 12mA 0.15 0.70 VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.14 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.27 0.55 Input leakage g current VCC = 2 2.3 3 to 3 3.6V; 6V; VI = VCC or GND 0.1 5 µA µ IOZ 3-State output OFF-state current VCC = 2.3 to 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 10 µA ICC Quiescent supply current VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 0.2 40 µA ∆ICC Additional quiescent supply current VCC = 2.3V to 3.6V; VI = VCC – 0.6V; IO = 0 150 750 µA IBHL2 Bus hold LOW sustaining current IBHH2 Bus hold HIGH sustaining current IBHLO2 IBHHO2 VOL II LOW level output voltage VCC = 2.3V; VI = 0.7V 45 – VCC = 3.0V; VI = 0.8V 75 150 VCC = 2.3V; VI = 1.7V –45 VCC = 3.0V; VI = 2.0V –75 Bus hold LOW overdrive current VCC = 3.6V 500 µA Bus hold HIGH overdrive current VCC = 3.6V –500 µA NOTES: 1. All typical values are at Tamb = 25°C. 2. Valid for data inputs of bus hold parts. 1998 Jul 27 V 5 –175 µA µA Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) 74ALVCH16841 AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF LIMITS SYMBOL PARAMETER WAVEFORM VCC = 2.3 to 2.7V UNIT MIN TYP1 MAX tPLH/tPHL Propagation delay nDn to nQn 1, 5 1.0 2.5 5.0 ns tPLH/tPHL Propagation delay nLE to nQn 2, 5 1.0 2.5 5.6 ns tPZH/tPZL 3-State output enable time nOEn to nQn 4, 5 1.0 2.7 6.2 ns tPHZ/tPLZ 3-State output disable time nOEn to nQn 4, 5 1.1 2.2 5.3 ns tW nLE pulse width HIGH 2, 5 3.3 1.5 – ns tSU Set up time nDn to nLE 3, 5 1.3 0.1 – ns Th Hold time nDn to nLE 3, 5 1.4 0.3 – ns NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF SYMBOL PARAMETER WAVEFORM LIMITS LIMITS VCC = 3.3 ± 0.3V VCC = 2.7V UNIT MIN TYP1, 2 MAX MIN TYP1 MAX tPLH/tPHL Propagation delay nDn to nQn 1, 5 1.0 2.4 3.9 1.0 2.6 4.7 ns tPLH/tPHL Propagation delay nLE to nQn 2, 5 1.0 2.4 4.3 1.0 2.6 5.1 ns tPZH/tPZL 3-State output enable time nOEn to nQn 4, 5 1.0 2.3 4.9 1.0 3.1 6.0 ns tPHZ/tPLZ 3-State output disable time nOEn to nQn 4, 5 1.3 2.9 4.1 1.3 3.1 4.3 ns tW nLE pulse width HIGH 2, 5 3.3 1.5 – 3.3 1.5 – ns tSU Set up time nDn to nLE 3, 5 1.0 0.6 – 1.1 0.1 – ns th Hold time nDn to nLE 3, 5 1.4 0.2 – 1.7 0.2 – ns NOTES: 1. All typical values are measured Tamb = 25°C. 2. Typical value is measured at VCC = 3.3V 1998 Jul 27 6 Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) AC WAVEFORMS FOR VCC = 2.3V TO 2.7V AND VCC < 2.3V RANGE 74ALVCH16841 VI VM = 0.5 VCC VX = VOL + 0.15V VY = VOH –0.15V VOL and VOH are the typical output voltage drop that occur with the output load. VM nOE INPUT GND tPLZ AC WAVEFORMS FOR VCC = 3.0V TO 3.6V AND VCC = 2.7V RANGE tPZL VCC OUTPUT LOW-to-OFF OFF-to-LOW VM = 1.5 V VX = VOL + 0.3V VY = VOH –0.3V VOL and VOH are the typical output voltage drop that occur with the output load. V = 2.7V I V =V I CC VM VX VOL tPHZ tPZH VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VI VY VM GND Dn INPUT outputs enabled VM outputs disabled outputs enabled SH00137 GND tPHL tPLH Waveform 4. 3-State enable and disable times VOH Qn OUTPUT TEST CIRCUIT VM S1 VCC VOL SH00153 Waveform 1. The input (Dn) to output (Qn) propagation delay RL = 500 Ω VO VI PULSE GENERATOR D.U.T. VI VM LE INPUT RT VM tPHL tPLH Test Circuit for switching times DEFINITIONS VOH Qn OUTPUT RL = Load resistor VM CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VOL SWITCH POSITION SH00150 TEST Waveform 2. The latch enable (LE) pulse width, the latch enable input to output (Qn) propagation delay tPLH/tPHL ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ VI VM th tSU Open tPLZ/tPZL 2 VCC tPHZ/tPZH GND VCC VI < 2.7V VCC 2.7–3.6V 2.7V Waveform 5. Load circuitry for switching times th tSU VI VM GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SH00149 Waveform 3. The data set up and hold times for the Dn input to the LE input 1998 Jul 27 S1 SV00906 GND LE INPUT RL = 500 Ω CL tW GND Dn INPUT 2 * VCC Open GND 7 Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Jul 27 8 74ALVCH16841 SOT364-1 Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) NOTES 1998 Jul 27 9 74ALVCH16841 Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) 74ALVCH16841 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Jul 27 10 Date of release: 07-98 9397-750-04561