INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT195 4-bit parallel access shift register Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 4-bit parallel access shift register 74HC/HCT195 by the state of the parallel load enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is HIGH and shifted one bit in the direction Q0 → Q1 → Q2 → Q3 following each LOW-to-HIGH clock transition. The J and K inputs provide the flexibility of the JK type input for special applications and by tying the pins together, the simple D-type input for general applications. The “195” appears as four common clocked D flip-flops when the PE input is LOW. FEATURES • Asynchronous master reset • J, K, (D) inputs to the first stage • Fully synchronous serial or parallel data transfer • Shift right and parallel load capability • Complement output from the last stage • Output capability: standard • ICC category: MSI After the LOW-to-HIGH clock transition, data on the parallel inputs (D0 to D3) is transferred to the respective Q0 to Q3 outputs. Shift left operation (Q3 → Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input LOW. GENERAL DESCRIPTION The 74HC/HCT195 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. All parallel and serial data transfers are synchronous, occurring after each LOW-to-HIGH clock transition. There is no restriction on the activity of the J, K, Dn and PE inputs for logic operation other than the set-up and hold time requirements. A LOW on the asynchronous master reset (MR) input sets all Q outputs LOW, independent of any other input condition. The 74HC/HCT195 performs serial, parallel, serial-to-parallel or parallel-to-serial data transfer at very high speeds. The “195” operates on two primary modes: shift right (Qo→Q1) and parallel load, which are controlled QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CP to Qn fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per package CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1,5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 HCT 15 15 ns 57 57 MHz 3.5 3.5 pF 105 105 pF Philips Semiconductors Product specification 4-bit parallel access shift register 74HC/HCT195 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 MR master reset input (active LOW) 2 J first stage J-input (active HIGH) 3 K first stage K-input (active LOW) 4, 5, 6, 7 D0 to D3 parallel data inputs 8 GND ground (0 V) 9 PE parallel enable input (active LOW) 10 CP clock input (LOW-to-HIGH edge-triggered) 11 Q3 inverted output from the last stage 15, 14, 13, 12 Q0 to Q3 parallel outputs 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 4-bit parallel access shift register 74HC/HCT195 Fig.4 Functional diagram. APPLICATIONS • Serial data transfer • Parallel data transfer • Serial-to-parallel data transfer • Parallel-to-serial data transfer FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES MR CP PE J K Dn Q0 Q1 Q2 Q3 Q3 asynchronous reset L X X X X X L L L L H shift, set first stage shift, reset first stage shift, toggle first stage shift, retain first stage H H H H ↑ ↑ ↑ ↑ h h h h h l h l h l l h X X X X H L q0 q0 q0 q0 q0 q0 q1 q1 q1 q1 q2 q2 q2 q2 q2 q2 q2 q2 parallel load H ↑ l X X dn d0 d1 d2 d3 d3 Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition q, d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW-to-HIGH clock transition X = don’t care ↑ = LOW-to-HIGH clock transition December 1990 4 Philips Semiconductors Product specification 4-bit parallel access shift register 74HC/HCT195 Fig.5 Logic diagram. December 1990 5 Philips Semiconductors Product specification 4-bit parallel access shift register 74HC/HCT195 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. max. −40 to +125 UNIT V WAVEFORMS CC (V) min. max. tPHL/ tPLH propagation delay CP to Qn 50 18 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.6 tPHL propagation delay MR to Qn 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.8 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 tW clock pulse width HIGH or LOW 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tW master reset pulse width LOW 80 16 14 11 4 3 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.8 trem removal time MR to CP 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.8 tsu set-up time J to CP 100 20 17 33 12 10 125 25 21 150 30 26 ns 2.0 4.5 6.0 Figs 8 and 9 tsu set-up time K, PE, Dn to CP 80 16 14 25 9 7 100 20 17 120 24 20 ns 2.0 4.5 6.0 Figs 8 and 9 th hold time J, K, PE, Dn to CP 3 3 3 −8 −3 −2 3 3 3 3 3 3 ns 2.0 4.5 6.0 Figs 8 and 9 fmax maximum clock pulse frequency 6 30 35 17 52 62 5 24 28 4 20 24 MHz 2.0 4.5 6.0 Fig.6 December 1990 6 Philips Semiconductors Product specification 4-bit parallel access shift register 74HC/HCT195 DC CHARACTERISTICS FOR HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT PE all others 0.65 0.35 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 −40 to +125 typ. max. min. max. min. max. UNIT V WAVEFORMS CC (V) tPHL/ tPLH propagation delay CP to Qn 18 32 40 48 ns 4.5 Fig.6 tPHL propagation delay MR to Qn 17 35 44 53 ns 4.5 Fig.8 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 20 6 25 30 ns 4.5 Fig.6 tW master reset pulse width LOW 16 6 20 24 ns 4.5 Fig.8 trem removal time MR to CP 16 6 20 24 ns 4.5 Fig.8 tsu set-up time J, K, PE to CP 20 12 25 30 ns 4.5 Figs 8 and 9 tsu set-up time Dn to CP 16 6 20 24 ns 4.5 Figs 8 and 9 th hold time J, K, PE, Dn to CP 3 −5 3 3 ns 4.5 Figs 8 and 9 fmax maximum clock pulse frequency 27 52 22 18 MHz 4.5 Fig.6 December 1990 7 Philips Semiconductors Product specification 4-bit parallel access shift register 74HC/HCT195 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.6 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for J, K and Dn inputs. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V. Fig.9 Waveforms showing the set-up and hold times from the parallel enable input (PE) to the clock (CP). December 1990 8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time Philips Semiconductors Product specification 4-bit parallel access shift register 74HC/HCT195 PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 9