INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT40104 4-bit bidirectional universal shift register; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state 74HC/HCT40104 In the parallel-load mode (S0 and S1 are HIGH), data is loaded into the associated flip-flop and appears at the output after the positive transition of the clock input (CP). FEATURES • Synchronous parallel or serial operating • 3-state outputs During loading, serial data flow is inhibited. Shift-right and shift-left are accomplished synchronously on the positive clock edge with serial data entered at the shift-right (DSR) and shift-left (DSL) serial inputs, respectively. • Output capability: bus driver • ICC category: MSI Clearing the register is accomplished by setting both mode controls (S0 and S1) LOW and clocking the register. When the output enable input (OE) is LOW, all outputs assume the high-impedance OFF-state (Z). GENERAL DESCRIPTION The 74HC/HCT40104 are high-speed Si-gate CMOS devices and are pin compatible with the “40104” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. APPLICATIONS The 74HC/HCT40104 are universal shift registers featuring parallel inputs, parallel outputs, shift-right and shift-left serial inputs and 3-state outputs allowing the devices to be used in bus-organized systems. • Arithmetic unit bus registers • Serial/parallel conversion • General-purpose register for bus organized systems • General-purpose registers QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CP to Qn CL = 15 pF; VCC = 5 V fmax maximum clock frequency CI input capacitance CPD power dissipation capacitance per package notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 HCT 13 15 ns 62 57 MHz 3.5 3.5 pF 75 75 pF Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state 74HC/HCT40104 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 OE 3-state output enable input (active HIGH) 2 DSR serial data shift-right input 3, 4, 5, 6 D0 to D3 parallel data inputs 7 DSL serial data shift-left input 8 GND ground (0 V) 9, 10 S0, S1 mode control inputs 11 CP clock input (LOW-to-HIGH, edge-triggered) 15, 14, 13, 12 Q0 to Q3 3-state parallel outputs 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state 74HC/HCT40104 FUNCTION TABLE INPUTS (OE = HIGH) OUTPUTS at tn+1 OPERATING MODES S1 S0 DSR DSL D0 to D3 Q0 Q1 Q2 Q3 reset L L X X X L L L shift left H H L L X X L H X X Q1 Q 2 Q1 Q2 Q3 Q3 L H shift right L L H H L H X X X X L H Q0 Q0 Q1 Q1 Q2 Q2 parallel load H H H H X X X X L H L H L H L H L H L Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care tn+1 = state after next LOW-to-HIGH transition of CP Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state 74HC/HCT40104 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay CP to Qn 44 16 13 170 34 29 215 43 37 255 51 43 ns 2.0 4.5 6.0 Fig.6 tPZH/ tPZL 3-state output enable time OE to Qn 33 12 10 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.8 tPHZ/ tPLZ 3-state output disable time OE to Qn 50 18 14 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.8 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6 tW clock pulse width HIGH or LOW 80 16 14 11 4 3 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tsu set-up time Dn, DSR, DSL to CP 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.8 tsu set-up time S0, S1 to CP 80 16 14 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.8 th hold time Dn, DSR, DSL to CP 2 2 2 −8 −3 −2 2 2 2 2 2 2 ns 2.0 4.5 6.0 Fig.8 th hold time S0, S1 to CP 2 2 2 −14 −5 −4 2 2 2 2 2 2 ns 2.0 4.5 6.0 Fig.8 fmax maximum clock pulse frequency 6.0 30 35 19 56 67 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.6 December 1990 5 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state 74HC/HCT40104 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT D0 to D3 DSR, DSL CP S0, S1 OE 0.35 0.35 0.35 0.70 1.40 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay CP to Qn 18 34 43 51 ns 4.5 Fig.6 tPZH/ tPZL 3-state output enable time OE to Qn 12 30 38 45 ns 4.5 Fig.8 tPHZ/ tPLZ 3-state output disable time OE to Qn 21 35 44 53 ns 4.5 Fig.8 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 16 7 20 24 ns 4.5 Fig.6 tsu set-up time Dn, DSR, DSL to CP 16 8 20 24 ns 4.5 Fig.8 tsu set-up time S0, S1 to CP 20 9 25 30 ns 4.5 Fig.8 th hold time Dn, DSR, DSL to CP 2 −2 2 2 ns 4.5 Fig.8 th hold time S0, S1 to CP 2 −5 2 2 ns 4.5 Fig.8 fmax maximum clock pulse frequency 27 52 22 18 MHz 4.5 Fig.6 December 1990 6 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state 74HC/HCT40104 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the set-up and hold times from the Dn, DSR, DSL and Sn inputs to the clock (CP). December 1990 7 Philips Semiconductors Product specification 4-bit bidirectional universal shift register; 3-state PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 8 74HC/HCT40104