DIODES 74LVC1G10W6

74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Description
Pin Assignments
The 74LVC1G10 is a single 3-input positive NAND gate with
a standard totem pole output. The device is designed for
operation with a power supply range of 1.65V to 5.5V. The
inputs are tolerant to 5.5V allowing this device to be used in a
mixed voltage environment. The device is fully specified for
NEW PRODUCT
partial power down applications using IOFF.
The IOFF
circuitry disables the output preventing damaging current
backflow when the device is powered down.
The gate performs the positive Boolean function:
Y = A •B •C
or
Y = A +B+C
Features
Applications
•
Wide Supply Voltage Range from 1.65V to 5.5V
•
Voltage Level Shifting
•
± 24mA Output Drive at 3.3V
•
General Purpose Logic
•
CMOS low power consumption
•
Power Down Signal Isolation
•
IOFF Supports Partial-Power-Down Mode Operation
•
Wide array of products such as:
•
Inputs accept up to 5.5V
o
PCs, networking, notebooks, netbooks, PDAs
•
ESD Protection Exceeds JESD 22
o
Computer peripherals, hard drives, CD/DVD ROM
200-V Machine Model (A115-A)
o
TV, DVD, DVR, set top box
2000-V Human Body Model (A114-A)
o
Cell Phones, Personal Navigation / GPS
•
Latch-Up Exceeds 100mA per JESD 78, Class II
o
MP3 players ,Cameras, Video Recorders
•
Range of Package Options
•
SOT26, SOT363, and DFN1010: Available in “Green”
•
Lead Free Finish/ RoHS Compliant (Note 1)
Molding Compound (no Br, Sb)
Notes:
1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at
http://www.diodes.com/products/lead_free.html.
74LVC1G10
Document number: DS35121 Rev. 1 - 2
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Pin Descriptions
NEW PRODUCT
Pin Name
A
GND
B
Y
Vcc
C
Description
Data Input
Ground
Data Input
Data Output
Supply Voltage
Data Input
Logic Diagram
1
A
4
3
6
B
C
Y
Function Table
Inputs
B
H
X
L
X
A
H
L
X
X
C
H
X
X
L
Output
Y
L
H
H
H
Absolute Maximum Ratings (Note 2)
Symbol
Description
Rating
Unit
2
KV
200
V
Supply Voltage Range
-0.5 to 6.5
V
VI
Input Voltage Range
-0.5 to 6.5
V
Vo
Voltage applied to output in high impedance or IOFF state
-0.5 to 6.5
V
Vo
Voltage applied to output in high or low state
-0.3 to VCC +0.5
V
IIK
Input Clamp Current VI<0
-50
mA
IOK
Output Clamp Current
-50
mA
IO
Continuous output current
±50
mA
Continuous current through Vdd or GND
±100
mA
Operating Junction Temperature
-40 to 150
°C
Storage Temperature
-65 to 150
°C
ESD HBM
Human Body Model ESD Protection
ESD MM
Machine Model ESD Protection
VCC
TJ
TSTG
Notes:
2. Stresses beyond the absolute maximum may result in immediate failure or reduced reliability. These are stress values and device
operation should be within recommend values.
74LVC1G10
Document number: DS35121 Rev. 1 - 2
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Recommended Operating Conditions (Note 3)
NEW PRODUCT
Symbol
VCC
Operating Voltage
VIH
High-level Input Voltage
VIL
Low-level input voltage
VI
VO
Input Voltage
Output Voltage
Parameter
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Min
1.65
1.5
0.65 X VCC
1.7
2
0.7 X VCC
0
0
VCC = 1.65 V
VCC = 2.3 V
IOH
High-level output current
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
IOL
Low-level output current
Δt/ΔV
TA
Notes:
Input transition rise or fall
rate
VCC = 3 V
VCC = 4.5 V
VCC = 1.8 V ± 0.15V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
Operating free-air
temperature
-40
Max
5.5
Unit
V
V
V
0.35 X VCC
0.7
0.8
0.3 X VCC
5.5
VCC
-4
-8
-16
-24
-32
4
8
16
24
32
20
10
5
125
V
V
V
mA
mA
ns/V
ºC
3. Unused inputs should be held at Vcc or Ground.
74LVC1G10
Document number: DS35121 Rev. 1 - 2
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Electrical Characteristics
Symbol
Parameter
TA=-40 °C to 85 °C
Test Conditions
IOH = -100μA
VOH
High Level Output
Voltage
(All typical values are at Vcc = 3.3V, TA = 25°C)
Vcc
Min
1.65V to 5.5V
VCC – 0.1
IOH = -4mA
1.65V
1.2
IOH = -8mA
2.3V
1.9
IOH = -16mA
3V
NEW PRODUCT
IOH = -24mA
VOL
High-level Input Voltage
1.65V to 5.5V
0.1
IOL = 4mA
1.65V
0.45
IOL = 8mA
2.3V
0.3
3V
Input Current
VI = 5.5 V or GND
IOFF
Power Down Leakage
Current
VI or VO = 5.5V
ICC
Supply Current
VI = 5.5V of GND
IO=0
Additional Supply
Current
Input at VCC –0.6 V
74LVC1G10
Document number: DS35121 Rev. 1 - 2
2.3
IOL = 100μA
IOL = 16mA
Unit
V
2.4
4.5V
IOL = 32mA
ΔICC
Max
IOH = -32mA
IOL = 24mA
II
Typ.
3.8
0.4
V
0.55
4.5V
0.55
0 to 5.5V
±5
μA
0
± 10
μA
1.65V to 5.5V
10
μA
3 V to 5.5V
500
μA
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Electrical Characteristics
Symbol
NEW PRODUCT
VOH
VOL
II
IOFF
ICC
ΔICC
Ci
θJA
θJC
Notes:
Parameter
TA=-40 °C to 125 °C
(All typical values are at Vcc = 3.3V, TA = 25°C)
Test Conditions
IOH = -100μA
IOH = -4mA
IOH = -8mA
High Level Output
Voltage
IOH = -16mA
IOH = -24mA
IOH = -32mA
IOL = 100μA
IOL = 4mA
IOL = 8mA
High-level Input Voltage
IOL = 16mA
IOL = 24mA
IOL = 32mA
Input Current
VI = 5.5 V or GND
VI or VO = 5.5V
Power Down Leakage
Current
VI = 5.5V of GND
Supply Current
IO=0
Additional Supply
Input at VCC –0.6 V
Current
Input Capacitance
Vi = VCC – or GND
SOT26
Thermal Resistance
SOT363
Junction-to-Ambient
DFN1010
SOT26
Thermal Resistance
SOT363
Junction-to-Case
DFN1010
Vcc
Min
1.65V to 5.5V
1.65V
2.3V
VCC – 0.1
0.95
1.7
1.9
2.0
3.4
3V
4.5V
1.65V to 5.5V
1.65V
2.3V
Typ.
Max
Unit
V
4.5V
0 to 5.5V
0.1
0.70
0.45
0.60
0.80
0.80
± 20
μA
0
± 20
μA
1.65V to 5.5V
40
μA
3 V to 5.5V
5000
μA
3V
3.3
(Note 4)
(Note 4)
4
166
333
231
46
102
TBD
V
pF
o
C/W
o
C/W
4. Test condition for SOT26, SOT363 and DFN1010 : Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad
layout.
74LVC1G10
Document number: DS35121 Rev. 1 - 2
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Switching Characteristics
TA=-40 °C to 85 °C , CL = 15pF (see Figure 1)
Parameter
tpd
From
(Input)
TO
(OUTPUT)
Any
Y
Vcc = 1.8 V
± 0.15V
Vcc = 2.5 V
± 0.2V
Vcc = 3.3 V
± 0.3V
Vcc = 5 V
± 0.5V
Min
Max
Min
Max
Min
Max
Min
Max
1.0
14.8
0.7
5.5
0.7
3.8
0.7
2.7
Unit
ns
NEW PRODUCT
TA=-40 °C to 85 °C , CL = 30 or 50pF (see Figure 2)
Parameter
tpd
From
(Input)
TO
(OUTPUT)
Any
Y
Vcc = 1.8 V
± 0.15V
Vcc = 2.5 V
± 0.2V
Vcc = 3.3 V
± 0.3V
Vcc = 5 V
± 0.5V
Min
Max
Min
Max
Min
Max
Min
Max
1.0
18.0
0.7
6.5
0.7
5
0.7
3.6
Unit
ns
TA=-40 °C to 125 °C , CL = 15 pF (see Figure 1)
Parameter
From
(Input)
TO
(OUTPUT)
tpd
Any
Y
Vcc = 1.8 V
± 0.15V
Min
Max
1.0
17.7
Vcc = 2.5 V
± 0.2V
Min
Max
0.7
6.6
Vcc = 3.3 V
± 0.3V
Min
Max
0.7
4.6
Vcc = 5 V
± 0.5V
Min
Max
0.7
3.3
Vcc = 2.5 V
± 0.2V
Min
Max
0.7
7.8
Vcc = 3.3 V
± 0.3V
Min
Max
0.7
6.0
Vcc = 5 V
± 0.5V
Min
Max
0.7
4.3
Unit
ns
TA=-40 °C to 125 °C , CL = 30 or 50pF (see Figure 2)
Parameter
From
(Input)
TO
(OUTPUT)
tpd
Any
Y
Vcc = 1.8 V
± 0.15V
Min
Max
1.0
21.6
Unit
ns
Operating Characteristics
TA = 25 ºC
Parameter
Cpd
Power dissipation
capacitance
74LVC1G10
Document number: DS35121 Rev. 1 - 2
Test
Conditions
Vcc = 1.8 V
Vcc = 2.5 V
Vcc = 3.3 V
Vcc = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
17
18
19
22
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Unit
pF
December 2010
© Diodes Incorporated
74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
NEW PRODUCT
Parameter Measurement Information
Inputs
Vcc
1.8V±0.15V
2.5V±0.2V
3.3V±0.3V
5V±0.5V
VI
tr/tf
VCC
VCC
3V
VCC
≤2ns
≤2ns
≤2.5ns
≤2.5ns
VM
CL
RL
VCC/2
VCC/2
1.5V
VCC/2
15pF
15pF
15pF
15pF
1MΩ
1MΩ
1MΩ
1MΩ
Voltage Waveform
Pulse Duration
Voltage Waveform
Propagation Delay Times
Inverting and Non Inverting Outputs
Notes:
A.
B.
C.
D.
Includes test lead and test apparatus capacitance.
All pulses are supplied at pulse repetition rate ≤ 10 MHz
Inputs are measured separately one transition per measurement
tPLH and tPHL are the same as tPD
Figure 1. Load Circuit and Voltage Waveforms
74LVC1G10
Document number: DS35121 Rev. 1 - 2
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
NEW PRODUCT
Parameter Measurement Information (Continued)
Inputs
Vcc
1.8V±0.15V
2.5V±0.2V
3.3V±0.3V
5V±0.5V
VI
VCC
VCC
3V
VCC
tr/tf
≤2ns
≤2ns
≤2.5ns
≤2.5ns
VM
CL
RL
VCC/2
VCC/2
1.5V
VCC/2
30pF
30pF
50pF
50pF
1KΩ
500Ω
500Ω
500Ω
Voltage Waveform
Pulse Duration
Voltage Waveform
Propagation Delay Times
Inverting and Non Inverting Outputs
Notes: A . Includes test lead and test apparatus capacitance.
B. All pulses are supplied at pulse repetition rate ≤ 10 MHz
C. Inputs are measured separately one transition per measurement
D. tPLH and tPHL are the same as tPD
Figure 2. Load Circuit and Voltage Waveforms
74LVC1G10
Document number: DS35121 Rev. 1 - 2
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Ordering Information
74LVC1G 10 XXX - 7
Function
NEW PRODUCT
Logic Device
74 : Logic Prefix
LVC : 1.65 to 5.5V
Family
1G : One gate
Package
10 : 3-Input
NAND-Gate
Packing
W6 : SOT26
DW : SOT363
FW4 : DFN1010
7 : Tape & Reel
7” Tape and Reel
Package
Code
Packaging
(Note 7)
Quantity
Part Number Suffix
74LVC1G10W6-7
W6
SOT26
3000/Tape & Reel
-7
74LVC1G10DW-7
DW
SOT363
3000/Tape & Reel
-7
74LVC1G10FW4-7
FW4
DFN1010
5000/Tape & Reel
-7
Device
Notes:
7. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
74LVC1G10
Document number: DS35121 Rev. 1 - 2
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Marking Information
NEW PRODUCT
(1) SOT26, SOT363
Part Number
Package
Identification Code
74LVC1G10W6
74LVC1G10DW
SOT26
SOT363
TU
TU
Part Number
74LVC1G10FW4
Package
DFN1010
Identification Code
TU
(2) DFN1010
74LVC1G10
Document number: DS35121 Rev. 1 - 2
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Package Outline Dimensions (All Dimensions in mm)
NEW PRODUCT
(1) Package Type: SOT26
(2) Package Type: SOT363
C
L
0.10/0.30
CL
1.9
C
L
1.15/1.35
6x-0.42
C
L
6x-0.60
2.0/2.2
4x-0.65
PIN 1
0.40/0.45
0.65Bsc.
Land Pattern Recommendation
(unit:mm)
1.8/2.2
0.1/0.22
0.9/1.0
0/0.1
1.10Max.
CL
"A"
Detail"A"
74LVC1G10
Document number: DS35121 Rev. 1 - 2
0°/8
0.25/0.40
°
0.25
Gauge Plane
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Package Outline Dimensions (All Dimensions in mm)
Seating Plane
Side View
0.08 C
C
0.08 C
Pin1
0.35Typ.
74LVC1G10
Document number: DS35121 Rev. 1 - 2
0.14/0.20(6x)
0.15Min.
A
0.35Typ.
Pin1
0.15
0.95/1.05
0.15Min.
0.07Typ.
0.35/0.45(6x)
2x-
0.20(6x)
0.235
0.95/1.05
B
0.05/0.15
2X-
NEW PRODUCT
0/0.05
0.08 C
0.45(6x)
0.40Max.
0.05 C
6x-
0.13Typ.
(3) Package Type: DFN1010
Land Pattern Recommendation
(unit:mm)
Top View
0.07
C A B
Bottom View
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
Taping Orientation (Note 8)
NEW PRODUCT
For DFN1010
Notes:
8. The taping orientation of the other package type can be found on our website at http://www.diodes.com/datasheets/ap02007.pdf
74LVC1G10
Document number: DS35121 Rev. 1 - 2
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74LVC1G10
SINGLE 3 INPUT POSITIVE NAND GATE
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS
DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
NEW PRODUCT
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other
changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability
arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any
license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described
herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies
whose products are represented on Diodes Incorporated website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized
sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names
and markings noted herein may also be covered by one or more United States, international or foreign trademarks.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without
the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided
in the labeling can be reasonably expected to result in significant injury to the user.
B.
A critical component is any component in a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or
systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements
concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems,
notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further,
Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes
Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2010, Diodes Incorporated
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Document number: DS35121 Rev. 1 - 2
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