74LVC2G66
Bilateral switch
Rev. 5 — 16 June 2010
Product data sheet
1. General description
The 74LVC2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device.
The 74LVC2G66 provides two single pole, single-throw analog switch functions. Each
switch has two input/output terminals (nY and nZ) and an active HIGH enable input (nE).
When nE is LOW, the analog switch is turned off.
Schmitt-trigger action at the enable inputs makes the circuit tolerant of slower input rise
and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 Ω (typical) at VCC = 2.7 V
6.5 Ω (typical) at VCC = 3.3 V
6 Ω (typical) at VCC = 5 V
Switch current capability of 32 mA
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD78 Class I
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Enable input accepts voltages up to 5.5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC2G66
NXP Semiconductors
Bilateral switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC2G66DP
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G66DC
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVC2G66GT
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm
SOT833-1
74LVC2G66GD
−40 °C to +125 °C
XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
SOT996-2
74LVC2G66GM
−40 °C to +125 °C
XQFN8U plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74LVC2G66DP
V66
74LVC2G66DC
V66
74LVC2G66GT
V66
74LVC2G66GD
V66
74LVC2G66GM
V66
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
#
1
X1
1
#
1
X1
001aah808
001aah807
Fig 1.
Logic symbol
74LVC2G66
Product data sheet
Fig 2.
IEC logic symbol
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
2 of 26
74LVC2G66
NXP Semiconductors
Bilateral switch
nZ
nY
nE
VCC
Fig 3.
mna658
Logic diagram (one switch)
6. Pinning information
6.1 Pinning
74LVC2G66
1Y
1
8
VCC
1Z
2
7
1E
2E
3
6
2Z
GND
4
5
2Y
74LVC2G66
1Y
1
8
VCC
1Z
2
7
1E
2E
3
6
2Z
GND
4
5
2Y
001aaf567
Transparent top view
001aaa529
Fig 4.
Pin configuration SOT505-2 and SOT765-1
Fig 5.
Pin configuration SOT833-1
74LVC2G66
1
8
VCC
1Z
2
7
1E
2E
3
6
2Z
GND
4
5
2Y
2Z
2Y
001aai248
Pin configuration SOT996-2
74LVC2G66
Product data sheet
7
1Y
2
6
1Z
3
5
2E
001aaf568
Transparent top view
Transparent top view
Fig 6.
8
1
GND
1Y
1E
4
74LVC2G66
VCC
terminal 1
index area
Fig 7.
Pin configuration SOT902-1
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
3 of 26
74LVC2G66
NXP Semiconductors
Bilateral switch
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT505-2, SOT765-1, SOT996-2 and
SOT833-1
SOT902-1
1Y
1
7
independent input or output
1Z
2
6
independent input or output
2E
3
5
enable input (active HIGH)
GND
4
4
ground (0 V)
2Y
5
3
independent input or output
2Z
6
2
independent input or output
1E
7
1
enable input (active HIGH)
VCC
8
8
supply voltage
7. Functional description
Table 4.
Function table[1]
Input nE
Switch
L
OFF-state
H
ON-state
[1]
H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
IIK
input clamping current
VI < −0.5 V or VI > VCC + 0.5 V
ISK
switch clamping current
VI < −0.5 V or VI > VCC + 0.5 V
Min
[1]
[2]
Max
Unit
−0.5
+6.5
V
−0.5
+6.5
V
−50
-
mA
-
±50
mA
−0.5
VCC + 0.5
V
-
±50
mA
VSW
switch voltage
enable and disable mode
ISW
switch current
VSW > −0.5 V or
VSW < VCC + 0.5 V
ICC
supply current
-
100
mA
IGND
ground current
−100
-
mA
Tstg
storage temperature
−65
+150
°C
-
250
mW
total power dissipation
Ptot
Tamb = −40 °C to +125 °C
[3]
[1]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[2]
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3]
For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
4 of 26
74LVC2G66
NXP Semiconductors
Bilateral switch
9. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VSW
switch voltage
Tamb
ambient temperature
Δt/ΔV
Conditions
[1][2]
input transition rise and fall rate
Min
Max
Unit
1.65
5.5
V
0
5.5
V
0
VCC
V
−40
+125
°C
VCC = 1.65 V to 2.7 V
[3]
-
20
ns/V
VCC = 2.7 V to 5.5 V
[3]
-
10
ns/V
[1]
To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no
limit for the voltage drop across the switch.
[2]
For overvoltage tolerant switch voltage capability, refer to 74LVCV2G66.
[3]
Applies to control signal levels.
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
HIGH-level
input voltage
LOW-level
input voltage
−40 °C to +85 °C
Conditions
VCC = 1.65 V to 1.95 V
−40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
0.65 × VCC
-
-
0.65 × VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.7 × VCC
-
-
0.7 × VCC
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35 × VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC = 4.5 V to 5.5 V
0.35 × VCC V
-
-
0.3 × VCC
-
0.3 × VCC
V
-
±0.1
±5
-
±100
μA
II
input leakage
current
pin nE; VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
[2]
IS(OFF)
OFF-state
leakage
current
VCC = 5.5 V; see Figure 8
[2]
-
±0.1
±5
-
±200
μA
IS(ON)
ON-state
leakage
current
VCC = 5.5 V; see Figure 9
[2]
-
±0.1
±5
-
±200
μA
ICC
supply current
VI = 5.5 V or GND;
VSW = GND or VCC;
VCC = 1.65 V to 5.5 V
[2]
-
0.1
10
-
200
μA
ΔICC
additional
supply current
pin nE; VI = VCC − 0.6 V;
VSW = GND or VCC;
VCC = 5.5 V
[2]
-
5
500
-
5000
μA
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Min
Typ[1]
Max
Min
Max
Unit
CI
input
capacitance
-
2.0
-
-
-
pF
CS(OFF)
OFF-state
capacitance
-
5.0
-
-
-
pF
CS(ON)
ON-state
capacitance
-
9.5
-
-
-
pF
[1]
All typical values are measured at Tamb = 25 °C.
[2]
These typical values are measured at VCC = 3.3 V.
10.1 Test circuits
VCC
VCC
nE
VIL
nZ
VI
nE
VIH
nY
IS
GND
IS
VO
VI
001aag488
Product data sheet
GND
VO
VI = VCC or GND and VO = open circuit.
Test circuit for measuring OFF-state leakage
current
74LVC2G66
nY
001aag489
VI = VCC or GND and VO = GND or VCC.
Fig 8.
nZ
Fig 9.
Test circuit for measuring ON-state leakage
current
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© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
10.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 11 to Figure 16.
Symbol
Parameter
RON(peak) ON resistance
(peak)
RON(rail)
ON resistance
(rail)
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Min
Typ[1]
Max
Min
Max
-
34.0
130
-
195
Unit
VI = GND to VCC; see Figure 10
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
12.0
30
-
45
Ω
ISW = 12 mA; VCC = 2.7 V
-
10.4
25
-
38
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
7.8
20
-
30
Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
6.2
15
-
23
Ω
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
8.2
18
-
27
Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
7.1
16
-
24
Ω
VI = GND; see Figure 10
ISW = 12 mA; VCC = 2.7 V
-
6.9
14
-
21
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
6.5
12
-
18
Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
5.8
10
-
15
Ω
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
10.4
30
-
45
Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
7.6
20
-
30
Ω
ISW = 12 mA; VCC = 2.7 V
-
7.0
18
-
27
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
6.1
15
-
23
Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
4.9
10
-
15
Ω
ISW = 4 mA;
VCC = 1.65 V to 1.95 V
-
26.0
-
-
-
Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
5.0
-
-
-
Ω
ISW = 12 mA; VCC = 2.7 V
-
3.5
-
-
-
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
2.0
-
-
-
Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
1.5
-
-
-
Ω
VI = VCC; see Figure 10
RON(flat)
ON resistance
(flatness)
[2]
VI = GND to VCC
[1]
Typical values are measured at Tamb = 25 °C and nominal VCC.
[2]
Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
10.3 ON resistance test circuit and graphs
mna673
40
RON
(Ω)
30
VSW
(1)
20
VCC
nE
VIH
(2)
(3)
nY
10
nZ
(4)
GND
VI
(5)
ISW
0
0
1
2
3
4
5
VI (V)
001aag490
RON = VSW/ISW.
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 10. Test circuit for measuring ON resistance
001aaa712
55
Fig 11. Typical ON resistance as a function of input
voltage; Tamb = 25 °C
001aaa708
15
RON
(Ω)
RON
(Ω)
45
13
35
11
(4)
(3)
(2)
(1)
(1)
(2)
25
9
(3)
(4)
15
7
5
5
0
0.4
0.8
1.2
1.6
2.0
0
0.5
VI (V)
(1) Tamb = 125 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(4) Tamb = −40 °C.
Fig 12. ON resistance as a function of input voltage;
VCC = 1.8 V
Product data sheet
1.5
2.0
2.5
VI (V)
(2) Tamb = 85 °C.
74LVC2G66
1.0
Fig 13. ON resistance as a function of input voltage;
VCC = 2.5 V
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© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
001aaa709
13
001aaa710
10
RON
(Ω)
RON
(Ω)
11
8
(1)
(1)
9
(2)
(2)
6
(3)
(3)
7
(4)
(4)
5
4
0
0.5
1.0
1.5
2.0
2.5
3.0
VI (V)
0
1
2
3
4
VI (V)
(1) Tamb = 125 °C.
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
(4) Tamb = −40 °C.
Fig 14. ON resistance as a function of input voltage;
VCC = 2.7 V
Fig 15. ON resistance as a function of input voltage;
VCC = 3.3 V
001aaa711
7
RON
(Ω)
6
5
(1)
(2)
(3)
4
(4)
3
0
1
2
3
4
5
VI (V)
(1) Tamb = 125 °C.
(2) Tamb = 85 °C.
(3) Tamb = 25 °C.
(4) Tamb = −40 °C.
Fig 16. ON resistance as a function of input voltage; VCC = 5.0 V
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
11. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 19.
Symbol Parameter
−40 °C to +85 °C
Conditions
Min
Max
Min
Max
VCC = 1.65 V to 1.95 V
-
0.8
2.0
-
3.0
ns
VCC = 2.3 V to 2.7 V
-
0.4
1.2
-
2.0
ns
VCC = 2.7 V
-
0.4
1.0
-
1.5
ns
VCC = 3.0 V to 3.6 V
-
0.3
0.8
-
1.5
ns
-
0.2
0.6
-
1.0
ns
VCC = 1.65 V to 1.95 V
1.0
4.6
10
1.0
13.0
ns
VCC = 2.3 V to 2.7 V
1.0
2.7
5.6
1.0
7.5
ns
VCC = 4.5 V to 5.5 V
enable time
ten
[4]
nE to nY or nZ;
see Figure 18
VCC = 2.7 V
1.0
2.7
5.0
1.0
6.5
ns
VCC = 3.0 V to 3.6 V
1.0
2.4
4.4
1.0
6.0
ns
1.0
1.8
3.9
1.0
5.0
ns
VCC = 1.65 V to 1.95 V
1.0
3.8
9.0
1.0
11.5
ns
VCC = 2.3 V to 2.7 V
1.0
2.1
5.5
1.0
7.0
ns
VCC = 2.7 V
1.0
3.5
6.5
1.0
8.5
ns
VCC = 3.0 V to 3.6 V
1.0
3.0
6.0
1.0
8.0
ns
VCC = 4.5 V to 5.5 V
1.0
2.2
5.0
1.0
6.5
ns
VCC = 4.5 V to 5.5 V
disable time
tdis
power dissipation
capacitance
CPD
Unit
[2][3]
propagation delay nY to nZ or nZ to nY;
see Figure 17
tpd
−40 °C to +125 °C
Typ[1]
[5]
nE to nY or nZ; see
Figure 18
CL = 50 pF; fi = 10 MHz;
VI = GND to VCC
[6]
VCC = 2.5 V
-
9.0
-
-
-
pF
VCC = 3.3 V
-
11.0
-
-
-
pF
VCC = 5.0 V
-
15.7
-
-
-
pF
[1]
Typical values are measured at Tamb = 25 °C and nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4]
ten is the same as tPZH and tPZL.
[5]
tdis is the same as tPLZ and tPHZ.
[6]
CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ{(CL + CS(ON)) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS(ON) = maximum ON-state switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
Σ{(CL + CS(ON)) × VCC2 × fo} = sum of the outputs.
11.1 Waveforms and test circuit
VI
nY or nZ
input
VM
VM
GND
t PLH
t PHL
VOH
nZ or nY
output
VM
VM
VOL
001aaa541
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Input (nY or nZ) to output (nZ or nY) propagation delays
VI
nE input
VM
GND
t PLZ
t PZL
VCC
output
LOW-to-OFF
OFF-to-LOW
nY or nZ
VM
VX
VOL
t PZH
t PHZ
nY or nZ
output
HIGH-to-OFF
OFF-to-HIGH
VOH
VY
VM
GND
switch
enabled
switch
disabled
switch
enabled
001aaa542
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 18. Enable and disable times
Table 10.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
1.65 V to 1.95 V
0.5 × VCC
0.5 × VCC
VOL + 0.15 V
VOH − 0.15 V
2.3 V to 2.7 V
0.5 × VCC
0.5 × VCC
VOL + 0.15 V
VOH − 0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
4.5 V to 5.5 V
0.5 × VCC
0.5 × VCC
VOL + 0.3 V
VOH − 0.3 V
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
VM
VM
10 %
0V
tW
VEXT
VCC
PULSE
GENERATOR
VI
RL
VO
DUT
RT
CL
RL
001aae235
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 19. Test circuit for measuring switching times
Table 11.
Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
1.65 V to 1.95 V
VCC
≤ 2.0 ns
30 pF
1 kΩ
open
GND
2 × VCC
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
GND
2 × VCC
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6V
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6V
4.5 V to 5.5 V
VCC
≤ 2.5 ns
50 pF
500 Ω
open
GND
2 × VCC
74LVC2G66
Product data sheet
Load
VEXT
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Bilateral switch
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
THD
RL = 10 kΩ; CL = 50 pF; fi = 1 kHz; see Figure 20
total harmonic distortion
Min
Typ
Max
Unit
VCC = 1.65 V
-
0.032
-
%
VCC = 2.3 V
-
0.008
-
%
VCC = 3.0 V
-
0.006
-
%
VCC = 4.5 V
-
0.005
-
%
VCC = 1.65 V
-
0.068
-
%
VCC = 2.3 V
-
0.009
-
%
VCC = 3.0 V
-
0.008
-
%
VCC = 4.5 V
-
0.006
-
%
VCC = 1.65 V
-
135
-
MHz
VCC = 2.3 V
-
145
-
MHz
VCC = 3.0 V
-
150
-
MHz
VCC = 4.5 V
-
155
-
MHz
RL = 10 kΩ; CL = 50 pF; fi = 10 kHz; see Figure 20
f(−3dB)
−3 dB frequency response
RL = 600 Ω; CL = 50 pF; see Figure 21
RL = 50 Ω; CL = 10 pF; see Figure 21
VCC = 1.65 V
-
200
-
MHz
VCC = 2.3 V
-
350
-
MHz
VCC = 3.0 V
-
410
-
MHz
VCC = 4.5 V
-
440
-
MHz
VCC = 1.65 V
-
> 500
-
MHz
VCC = 2.3 V
-
> 500
-
MHz
VCC = 3.0 V
-
> 500
-
MHz
VCC = 4.5 V
-
> 500
-
MHz
VCC = 1.65 V
-
−46
-
dB
VCC = 2.3 V
-
−46
-
dB
VCC = 3.0 V
-
−46
-
dB
VCC = 4.5 V
-
−46
-
dB
VCC = 1.65 V
-
−37
-
dB
VCC = 2.3 V
-
−37
-
dB
VCC = 3.0 V
-
−37
-
dB
VCC = 4.5 V
-
−37
-
dB
RL = 50 Ω; CL = 5 pF; see Figure 21
αiso
isolation (OFF-state)
RL = 600 Ω; CL = 50 pF; fi = 1 MHz; see Figure 22
RL = 50 Ω; CL = 5 pF; fi = 1 MHz; see Figure 22
74LVC2G66
Product data sheet
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Bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
Vct
between digital inputs and switch; RL = 600 Ω;
CL = 50 pF; fi = 1 MHz; tr = tf = 2 ns; see Figure 23
Xtalk
crosstalk voltage
crosstalk
Min
Typ
Max
Unit
VCC = 1.65 V
-
-
-
mV
VCC = 2.3 V
-
91
-
mV
VCC = 3.0 V
-
119
-
mV
VCC = 4.5 V
-
205
-
mV
-
-
-
dB
between switches; RL = 600 Ω; CL = 50 pF;
fi = 1 MHz; see Figure 24
VCC = 1.65 V
VCC = 2.3 V
-
−56
-
dB
VCC = 3 V
-
−56
-
dB
VCC = 4.5 V
-
−56
-
dB
VCC = 1.65 V
-
-
-
dB
VCC = 2.3 V
-
−29
-
dB
VCC = 3 V
-
−28
-
dB
VCC = 4.5 V
-
−28
-
dB
VCC = 1.8 V
-
3.3
-
pC
VCC = 2.5 V
-
4.1
-
pC
VCC = 3.3 V
-
5.0
-
pC
VCC = 4.5 V
-
6.4
-
pC
VCC = 5.5 V
-
7.5
-
pC
between switches; RL = 50 Ω; CL = 5 pF;
fi = 1 MHz; see Figure 24
Qinj
charge injection
74LVC2G66
Product data sheet
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω; fi = 1 MHz;
RL = 1 MΩ; see Figure 25
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Rev. 5 — 16 June 2010
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Bilateral switch
11.3 Test circuits
VCC
0.5VCC
nE
VIH
RL
nY/nZ
10 μF
nZ/nY
VO
600 Ω
fi
D
CL
001aag492
Test conditions:
VCC = 1.65 V: Vi = 1.4 V (p-p).
VCC = 2.3 V: Vi = 2 V (p-p).
VCC = 3 V: Vi = 2.5 V (p-p).
VCC = 4.5 V: Vi = 4 V (p-p).
Fig 20. Test circuit for measuring total harmonic distortion
VCC
nE
VIH
0.1 μF
fi
0.5VCC
RL
nY/nZ
nZ/nY
VO
50 Ω
CL
dB
001aag491
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB.
Fig 21. Test circuit for measuring the frequency response when switch is in ON-state
0.5VCC
VCC
RL VIL
0.1 μF
fi
0.5VCC
nE
nY/nZ
RL
nZ/nY
50 Ω
VO
CL dB
001aag493
Adjust fi voltage to obtain 0 dBm level at input.
Fig 22. Test circuit for measuring isolation (OFF-state)
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
VCC
nE
nY/nZ
G
logic
input
50 Ω
nZ/nY
600 Ω
VO
RL
0.5VCC
CL
0.5VCC
001aag494
Fig 23. Test circuit for measuring crosstalk voltage (between digital inputs and switch)
0.5VCC
1E
VIH
0.1 μF
Ri
1Y or 1Z
600 Ω
fi
RL
1Z or 1Y
CHANNEL
ON
50 Ω
CL
50 pF
VO1
0.5VCC
2E
VIL
RL
2Y or 2Z
2Z or 2Y
CHANNEL
OFF
Ri
600 Ω
CL
50 pF
VO2
001aag496
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 24. Test circuit for measuring crosstalk between switches
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
VCC
nE
Rgen
G
logic
input
nY/nZ
nZ/nY
VO
RL
1 MΩ
Vgen
CL
0.1 nF
001aag495
a. Test circuit
logic
input (nE)
off
on
off
ΔVO
VO
mna675
b. Input and output pulse definitions
Qinj = ΔVO × CL.
ΔVO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 25. Test circuit for measuring charge injection
74LVC2G66
Product data sheet
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Bilateral switch
12. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Fig 26. Package outline SOT505-2 (TSSOP8)
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVC2G66
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Bilateral switch
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Fig 27. Package outline SOT765-1 (VSSOP8)
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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Bilateral switch
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
1
2
SOT833-1
b
4
3
4×
(2)
L
L1
e
8
7
6
e1
5
e1
e1
8×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
Fig 28. Package outline SOT833-1 (XSON8)
74LVC2G66
Product data sheet
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Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
B
D
SOT996-2
A
A
E
A1
detail X
terminal 1
index area
e1
v
w
b
e
L1
1
4
8
5
C
C A B
C
M
M
y
y1 C
L2
L
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
L2
v
w
y
y1
mm
0.5
0.05
0.00
0.35
0.15
2.1
1.9
3.1
2.9
0.5
1.5
0.5
0.3
0.15
0.05
0.6
0.4
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT996-2
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-18
07-12-21
Fig 29. Package outline SOT996-2 (XSON8U)
74LVC2G66
Product data sheet
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© NXP B.V. 2010. All rights reserved.
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74LVC2G66
NXP Semiconductors
Bilateral switch
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
B
D
SOT902-1
A
terminal 1
index area
A
E
A1
detail X
L1
e
e
C
∅v M C A B
∅w M C
L
4
y1 C
y
5
3
metal area
not for soldering
e1
b
2
6
e1
7
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
v
w
y
y1
mm
0.5
0.05
0.00
0.25
0.15
1.65
1.55
1.65
1.55
0.55
0.5
0.35
0.25
0.15
0.05
0.1
0.05
0.05
0.05
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT902-1
---
MO-255
---
EUROPEAN
PROJECTION
ISSUE DATE
05-11-25
07-11-14
Fig 30. Package outline SOT902-1 (XQFN8U)
74LVC2G66
Product data sheet
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Bilateral switch
13. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
TTL
Transistor-Transistor Logic
HBM
Human Body Model
ESD
ElectroStatic Discharge
MM
Machine Model
DUT
Device Under Test
14. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC2G66 v.5
20100616
Product data sheet
-
74LVC2G66 v.4
Modifications:
•
Conditions for ICC and ΔICC corrected.
74LVC2G66 v.4
20080701
Product data sheet
-
74LVC2G66 v.3
74LVC2G66 v.3
20080310
Product data sheet
-
74LVC2G66 v.2
74LVC2G66 v.2
20070828
Product data sheet
-
74LVC2G66 v.1
74LVC2G66 v.1
20040629
Product data sheet
-
-
74LVC2G66
Product data sheet
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Bilateral switch
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
74LVC2G66
Product data sheet
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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NXP Semiconductors
Bilateral switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Product data sheet
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Bilateral switch
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
11
11.1
11.2
11.3
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance test circuit and graphs. . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms and test circuit . . . . . . . . . . . . . . . 11
Additional dynamic characteristics . . . . . . . . . 13
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Contact information. . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 June 2010
Document identifier: 74LVC2G66