74LVC2GU04 Dual inverter Rev. 05 — 27 October 2009 Product data sheet 1. General description The 74LVC2GU04 provides two inverters. Each inverter is a single stage with unbuffered output. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. 2. Features n n n n n n n n n Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Input accepts voltages up to 5 V Multiple package options ESD protection: u HBM JESD22-A114F exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2GU04GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC2GU04GV −40 °C to +125 °C TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC2GU04GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74LVC2GU04GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1 × 0.5 mm SOT891 74LVC2GU04 NXP Semiconductors Dual inverter 4. Marking Table 2. Marking codes Type number Marking[1] 74LVC2GU04GW YD 74LVC2GU04GV VU4 74LVC2GU04GM YD 74LVC2GU04GF YD [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1A 1 VCC VCC 6 1Y 1 1 6 100 Ω Y A 2A 3 4 2Y 1 3 mnb107 mnb106 Fig 1. 4 Logic symbol Fig 2. mna636 IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74LVC2GU04 74LVC2GU04 1A GND 2A 1 6 2 5 3 4 1 6 1Y GND 2 5 VCC 2A 3 4 2Y VCC 2Y Pin configuration SOT363 and SOT457 001aab681 Fig 5. Pin configuration SOT886 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 001aag421 Transparent top view Transparent top view 74LVC2GU04_5 Product data sheet 74LVC2GU04 1Y 001aab680 Fig 4. 1A Fig 6. Pin configuration SOT891 © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 2 of 16 74LVC2GU04 NXP Semiconductors Dual inverter 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output 7. Functional description Table 4. Function table[1] Input Output nA nY L H H L [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO < 0 V Min Max Unit −0.5 +6.5 V −50 - mA −0.5 +6.5 V −50 - mA −0.5 VCC + 0.5 V - ±50 mA supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature Ptot total power dissipation VO output voltage Active mode IO output current VO = 0 V to VCC ICC [1][2] Tamb = −40 °C to +125 °C [3] −65 +150 °C - 250 mW [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 3 of 16 74LVC2GU04 NXP Semiconductors Dual inverter 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature ∆t/∆V input transition rise and fall rate Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V 0 - VCC V −40 - +125 °C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V Active mode 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 Conditions Min Typ Max Unit °C[1] VIH HIGH-level input voltage VCC = 1.65 V to 5.5 V 0.75 × VCC - - V VIL LOW-level input voltage VCC = 1.65 V to 5.5 V - - 0.25 × VCC V VOH HIGH-level output voltage VI = VIH or VIL VCC − 0.1 - - V IO = −100 µA; VCC = 1.65 V to 5.5 V VOL LOW-level output voltage IO = −4 mA; VCC = 1.65 V 1.2 - - V IO = −8 mA; VCC = 2.3 V 1.9 - - V IO = −12 mA; VCC = 2.7 V 2.2 - - V IO = −24 mA; VCC = 3.0 V 2.3 - - V IO = −32 mA; VCC = 4.5 V 3.8 - - V - - 0.1 V VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V - - 0.55 V - ±0.1 ±5 µA IO = 32 mA; VCC = 4.5 V [2] II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 10 µA CI input capacitance VCC = 3.3 V; VI = GND to VCC - 5 - pF 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 4 of 16 74LVC2GU04 NXP Semiconductors Dual inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +125 °C VIH HIGH-level input voltage VCC = 1.65 V to 5.5 V 0.8 × VCC - - V VIL LOW-level input voltage VCC = 1.65 V to 5.5 V - - 0.2 × VCC V VOH HIGH-level output voltage VI = VIH or VIL VCC − 0.1 - - V IO = −100 µA; VCC = 1.65 V to 5.5 V LOW-level output voltage VOL IO = −4 mA; VCC = 1.65 V 0.95 - - V IO = −8 mA; VCC = 2.3 V 1.7 - - V IO = −12 mA; VCC = 2.7 V 1.9 - - V IO = −24 mA; VCC = 3.0 V 2.0 - - V IO = −32 mA; VCC = 4.5 V 3.4 - - V - - 0.1 V VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V - - 0.7 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.8 V IO = 32 mA; VCC = 4.5 V - - 0.8 V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - ±20 µA ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - - 40 µA [1] All typical values are measured at Tamb = 25 °C. [2] These typical values are measured at VCC = 3.3 V. 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 5 of 16 74LVC2GU04 NXP Semiconductors Dual inverter 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter −40 °C to +85 °C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 0.5 2.3 5.0 0.5 6.3 ns VCC = 2.3 V to 2.7 V 0.3 1.8 4.0 0.3 5.0 ns VCC = 2.7 V 0.3 2.6 4.5 0.3 5.6 ns VCC = 3.0 V to 3.6 V 0.3 2.3 3.7 0.3 4.5 ns VCC = 4.5 V to 5.5 V 0.3 1.7 3.0 0.3 3.8 ns - 7.8 - [2] propagation delay nA to nY; see Figure 7 tpd power dissipation capacitance CPD −40 °C to +125 °C Unit Typ[1] [3] VI = GND to VCC; VCC = 3.3 V [1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. pF 12. Waveforms VI VM nA input VM GND t PHL t PLH VOH VM nY output VOL VM mna344 Measurement points are given in Table 9. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The input (nA) to output (nY) propagation delay times 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 6 of 16 74LVC2GU04 NXP Semiconductors Dual inverter Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 × VCC 0.5 × VCC VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 10. Load circuitry for switching times Test data Supply voltage Input Load VEXT VCC VI tr = t f CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 7 of 16 74LVC2GU04 NXP Semiconductors Dual inverter mnb108 160 gfs (mA/V) 120 Rbias = 560 kΩ 80 VCC 40 0.47 µF input VI 0 0 1 2 3 4 5 6 VCC (V) Tamb = 25 °C. output 100 µF A IO mna638 ∆I O g fs = --------∆V I fi = 1 kHz. VO is constant. Fig 9. Typical forward transconductance as a function of supply voltage Fig 10. Test set-up for measuring forward transconductance 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 8 of 16 74LVC2GU04 NXP Semiconductors Dual inverter 13. Application information Some applications are: • Linear amplifier (see Figure 11) • In crystal oscillator design (see Figure 12) Remark: All values given are typical unless otherwise specified. R2 R1 VCC 1 µF R2 R1 U04 U04 C1 ZL C2 out mna053 mna052 Vo(p-p) = VCC − 1.5 V centered at 0.5VCC. C1 = 47 pF (typical). A OL A u = – ----------------------------------------R1 1 + ------- ( 1 + A OL ) R2 C2 = 22 pF (typical). R1 = 1 MΩ to 10 MΩ (typical). R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC is typically 2 mA at VCC = 3.3 V and f = 10 MHz). AOL = open loop amplification. Au = voltage amplification. R1 ≥ 3 kΩ, R2 ≤ 1 MΩ. ZL > 10 kΩ; AOL = 20 (typical). Typical unity gain bandwidth product is 5 MHz. Fig 11. Linear amplifier configuration Fig 12. Crystal oscillator configuration 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 9 of 16 74LVC2GU04 NXP Semiconductors Dual inverter 14. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT363 JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 13. Package outline SOT363 (SC-88) 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 10 of 16 74LVC2GU04 NXP Semiconductors Dual inverter Plastic surface-mounted package (TSOP6); 6 leads D SOT457 E B y A HE 6 X v M A 4 5 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT457 JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 14. Package outline SOT457 (TSOP6) 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 11 of 16 74LVC2GU04 NXP Semiconductors Dual inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 4 e1 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 15. Package outline SOT886 (XSON6) 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 12 of 16 74LVC2GU04 NXP Semiconductors Dual inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 4 e1 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 16. Package outline SOT891 (XSON6) 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 13 of 16 74LVC2GU04 NXP Semiconductors Dual inverter 15. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 16. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2GU04_5 20091027 Product data sheet - 74LVC4GU04_4 Modifications: • • • Section 2: JESD22-A114E changed to JESD22-A114F Section 4 “Marking”: marking code for 74LVC2GU04GV changed from YU4 into VU4 Figure 8: drawing amended/improved 74LVC2GU04_4 20070521 Product data sheet - 74LVC4GU04_3 74LVC2GU04_3 20040921 Product specification - 74LVC2GU04_2 74LVC2GU04_2 20040524 Product specification - 74LVC2GU04_1 74LVC2GU04_1 20030829 Product specification - - 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 14 of 16 74LVC2GU04 NXP Semiconductors Dual inverter 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC2GU04_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 15 of 16 74LVC2GU04 NXP Semiconductors Dual inverter 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 27 October 2009 Document identifier: 74LVC2GU04_5