SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
D Member of the Texas Instruments
D Bus Hold on Data Inputs Eliminates the
Widebus+ Family
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC )
Supports Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
D
D
D
D
D
GKE OR ZKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
D
D
D
D
Need for External Pullup/Pulldown
Resistors
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
terminal assignments
1
2
3
4
5
6
A
A
1Q2
1Q1
1OE
1CLK
1D1
1D2
B
B
1Q4
1Q3
GND
GND
1D3
1D4
C
C
1Q6
1Q5
D
1Q7
VCC
GND
1D6
1Q8
VCC
GND
1D5
D
1D7
1D8
E
E
2Q2
2Q1
GND
GND
2D1
2D2
F
2Q4
2Q3
2Q5
VCC
GND
2D4
2Q6
VCC
GND
2D3
G
2D5
2D6
H
2Q7
2Q8
2OE
2CLK
2D8
2D7
J
3Q2
3Q1
3OE
3CLK
3D1
3D2
K
3Q4
3Q3
GND
GND
3D3
3D4
L
3Q6
3Q5
3Q7
VCC
GND
3D6
3Q8
VCC
GND
3D5
M
3D7
3D8
F
G
H
J
K
L
M
N
4Q2
4Q1
GND
GND
4D1
4D2
N
P
4Q4
4Q3
4D4
R
4Q6
4Q5
VCC
GND
4D3
P
VCC
GND
4D5
4D6
R
T
4Q7
4Q8
4OE
4CLK
4D8
4D7
T
NC − No internal connection
description/ordering information
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
LFBGA − GKE
−40°C to 85°C
LFBGA − ZKE (Pb-free)
TOP-SIDE
MARKING
SN74LVTH322374KR
Tape and reel
74LVTH322374ZKER
HW374
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#'
+&%#$ %! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$
$#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+'
#'$#0 "** (""!'#'$
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The SN74LVTH322374 is a 32-bit edge-triggered D-type flip-flop with 3-state outputs designed for low-voltage
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. It is
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive
transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
(each 8-bit flip-flop)
INPUTS
2
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
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• DALLAS, TEXAS 75265
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1OE
1CLK
1D1
A3
2OE
A4
A5
2CLK
C1
A2
1D
1Q1
H3
H4
C1
2D1
E5
3CLK
3D1
J3
4OE
J4
J5
4CLK
C1
J2
1D
2Q1
To Seven Other Channels
To Seven Other Channels
3OE
E2
1D
3Q1
To Seven Other Channels
T3
T4
C1
4D1
N5
1D
N2
4Q1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): GKE/ZKE package . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
MIN
MAX
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
5.5
V
IOH
IOL
High-level output current
−12
mA
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
−40
High-level input voltage
2
V
0.8
Low-level output current
Outputs enabled
V
V
12
mA
10
ns/V
µs/V
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
−1.2
V
VIK
VOH
VCC = 2.7 V,
VCC = 3 V,
II = −18 mA
IOH = −12 mA
VOL
VCC = 3 V,
VCC = 0 or 3.6 V,
IOL = 12 mA
VI = 5.5 V
0.8
VCC = 3.6 V,
VI = VCC or GND
VI = VCC
±1
Control inputs
II
Data inputs
Ioff
VCC = 3.6 V
VCC = 0,
VCC = 3 V
II(hold)
Data inputs
2
V
1
VI = 0
VI or VO = 0 to 4.5 V
VI = 0.8 V
VI = 2 V
V
10
µA
A
−5
±100
µA
75
−75
500
−750
µA
VCC = 3.6 V‡,
VI = 0 to 3.6 V
IOZH
IOZL
VCC = 3.6 V,
VCC = 3.6 V,
VO = 3 V
VO = 0.5 V
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care
±100
µA
ICC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
Outputs high
Ci
VI = 3 V or 0
VO = 3 V or 0
Co
−5
µA
±100
µA
10
Outputs disabled
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
µA
0.38
Outputs low
∆ICC§
5
mA
0.38
0.2
3
pF
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
4
POST OFFICE BOX 655303
9
mA
• DALLAS, TEXAS 75265
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
MIN
MAX
VCC = 2.7 V
MIN
160
UNIT
MAX
fclock
tw
Clock frequency
3
3
ns
tsu
th
Setup time, data before CLK↑
High or low
1.8
2
ns
Hold time, data after CLK↑
High or low
0.8
0.1
ns
Pulse duration, CLK high or low
160
MHz
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
TYP†
MAX
2
3.4
5.3
6.2
2.2
3.3
4.9
5.1
1.8
3.5
5.6
6.9
1.8
3.5
4.9
6
2.4
4.2
5.4
5.7
2
3.8
5
5.1
MIN
160
CLK
Q
OE
Q
OE
Q
tsk(o)
† All typical values are at VCC = 3.3 V, TA = 25°C.
POST OFFICE BOX 655303
UNIT
MAX
160
0.5
• DALLAS, TEXAS 75265
MIN
MHz
ns
ns
ns
ns
5
SCBS754B − MARCH 2002 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
2.7 V
Input
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
VOH
Output
1.5 V
1.5 V
VOL
1.5 V
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZL
tPLZ
3V
1.5 V
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
tPHL
2.7 V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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