Revised June 2005 74LVX161284A Low Voltage IEEE 161284 Translating Transceiver General Description Features The LVX161284A contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard, with the exception of output slew rate, and is intended to be used in an Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). ■ Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals with the exception of output slew rate Outputs on the cable side can be configured to be either open drain or high drive (r 14 mA) and are connected to a separate power supply pin (VCCcable) to allow these outputs to be driven by a higher supply voltage than the Aside. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCCcable supply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the A1–A8/B1–B8 transceiver pins. ■ B and Y output resistance optimized to drive external cable ■ Translation capability allows outputs on the cable side to interface with 5V signals ■ All inputs have hysteresis to provide noise margin ■ B and Y outputs in high impedance mode during power down ■ Inputs and outputs on cable side have internal pull-up resistors ■ Flow-through pin configuration allows easy interface between the “Peripheral and Host” ■ Replaces the function of two (2) 74ACT1284 devices Ordering Code Order Number Package Number 74LVX161284AMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 74LVX161284AMTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Package Description Connection Diagram Pin Descriptions Pin Names HD © 2005 Fairchild Semiconductor Corporation DS500204 Description High Drive Enable Input (Active HIGH) DIR Direction Control Input A1–A8 Inputs or Outputs B1–B8 Inputs or Outputs A9–A13 Inputs Y9–Y13 Outputs A14–A17 Outputs C14–C17 Inputs PLHIN Peripheral Logic HIGH Input PLH Peripheral Logic HIGH Output HLHIN Host Logic HIGH Input HLH Host Logic HIGH Output www.fairchildsemi.com 74LVX161284A Low Voltage IEEE 161284 Translating Transceiver June 1999 74LVX161284A Logic Symbol Truth Table Inputs Outputs DIR HD L L B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode L H B1–B8 Data to A1–A8, and A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 H L A1–A8 Data to B1–B8 (Note 2) A9–A13 Data to Y9–Y13 (Note 1) C14–C17 Data to A14–A17 PLH Open Drain Mode H H A1–A8 Data to B1–B8 A9–A13 Data to Y9–Y13 C14–C17 Data to A14–A17 Note 1: Y9–Y13 Open Drain Outputs Note 2: B1–B8 Open Drain Outputs Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions Supply Voltage 0.5V to 4.6V 0.5V to 7.0V VCC VCC—Cable Supply Voltage VCC—Cable Must Be t VCC Input Voltage (VI)—(Note 4) 0.5V to VCC 0.5V 0.5V to 5.5V (DC) 2.0V to 7.0V* A1–A13, PLHIN , DIR, HD B1–B8, C14–C17, HLHIN B1–B8, C14–C17, HLHIN VCC 3.0V to 3.6V VCC—Cable 3.0V to 5.5V DC Input Voltage (VI) 0V to VCC Open Drain Voltage (VO) 0V to 5.5V 40qC to 85qC Operating Temperature (TA) *40 ns Transient Output Voltage (VO) 0.5V to VCC 0.5V 0.5V to 5.5V (DC) 2.0V to 7.0V* A1–A8, A14–A17, HLH B1–B8, Y9–Y13, PLH B1–B8, Y9–Y13, PLH *40 ns Transient DC Output Current (IO) r25 mA r50 mA A1–A8, HLH B1–B8, Y9–Y13 PLH (Output LOW) 84 mA PLH (Output HIGH) 50 mA Input Diode Current (IIK)—(Note 4) DIR, HD, A9–A13, PLH, HLH, C14–C17 20 mA Output Diode Current (IOK) r50 mA 50 mA A1–A8, A14–A17, HLH B1–B8, Y9–Y13, PLH DC Continuous VCC or Ground Current Storage Temperature Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. r200 mA 65qC to 150qC ESD (HBM) Last Passing Voltage Note 4: Either voltage limit or current limit is sufficient to protect inputs. 2000V DC Electrical Characteristics Symbol VIK Parameter Input Clamp VIL 'VT VOH (V) VCC—Cable TA 40qC to 85qC (V) Guaranteed Limits 3.0 3.0 1.2 An, Bn, PLHIN, DIR, HD 3.0–3.6 3.0–5.5 2.0 HIGH Level Cn 3.0–3.6 3.0–5.5 2.3 Input Voltage HLHIN 3.0–3.6 3.0–5.5 2.6 Maximum An, Bn, PLHIN, DIR, HD 3.0–3.6 3.0–5.5 0.8 LOW Level Cn 3.0–3.6 3.0–5.5 0.8 Input Voltage HLHIN 3.0–3.6 3.0–5.5 1.6 Diode Voltage VIH VCC Minimum Units V Conditions Ii 18 mA V V VT–VT Minimum Input An, Bn, PLHIN, DIR, HD 3.3 5.0 0.4 Hysteresis Cn 3.3 5.0 0.8 HLHIN 3.3 5.0 0.2 Minimum HIGH An, HLH 3.0 3.0 2.8 IOH 50 PA 3.0 3.0 2.4 IOH 4 mA Bn, Yn 3.0 3.0 2.0 IOH 14 mA Bn, Yn 3.0 4.5 2.23 IOH 14 mA PLH 3.15 3.15 3.1 IOH 500 PA Level Output Voltage 3 V VT–VT VT–VT V www.fairchildsemi.com 74LVX161284A Absolute Maximum Ratings(Note 3) 74LVX161284A DC Electrical Characteristics Symbol (Continued) Parameter VCC (V) VOL Maximum LOW RD Maximum Output IIH IIL IOZH IOZL IOFF IOFF 0.2 IOL 50 PA 0.4 IOL 4 mA Bn, Yn 3.0 3.0 0.8 IOL 14 mA Bn, Yn 3.0 4.5 0.77 IOL 14 mA PLH 3.0 3.0 0.95 IOL 84 mA PLH 3.0 4.5 0.9 IOL 84 mA B1–B8, Y9–Y13 3.3 3.3 60 3.3 5.0 55 3.3 3.3 30 B1–B8, Y9–Y13 3.3 5.0 35 B1–B8, Y9–Y13, 3.3 3.3 1650 Resistance C14–C17 3.3 5.0 1650 Minimum Pull-Up B1–B8, Y9–Y13 3.3 3.3 1150 3.3 5.0 1150 3.6 3.6 1.0 Resistance C14–C17 Maximum Input A9–A13, PLHIN, Current in HD, DIR, HLHIN HIGH State C14–C17 3.6 3.6 50.0 C14–C17 3.6 5.5 100 A9–A13, PLHIN, (Note 5)(Note 7) : PA VI 3.6V VI 3.6V VI 5.5V HD, DIR, HLHIN 3.6 3.6 1.0 PA VI 0.0V C14–C17 3.6 3.6 3.5 mA VI 0.0V C14–C17 3.6 5.5 5.0 mA VI 0.0V Maximum Output A1–A8 3.6 3.6 20 PA VO 3.6V Disable Current B1–B8 3.6 3.6 50 PA VO 3.6V (HIGH) B1–B8 3.6 5.5 100 PA VO 5.5V Maximum A1–A8 3.6 3.6 20 PA VO 0.0V Output Disable B1–B8 3.6 3.6 3.5 mA Current (LOW) B1–B8 3.6 5.5 5.0 mA Power Down B1–B8, Y9–Y13, Output Leakage PLH 0.0 0.0 100 PA VO 5.5V 0.0 0.0 100 PA VI 0.0 0.0 250 PA (Note 6) Power Down C14–C17, HLHIN PowerDown Power Down Leakage 5.5V 0.0 0.0 250 PA (Note 6) Maximum Supply 3.6 3.6 45 mA VI VCC or GND Current 3.6 5.5 70 VI VCC or GND to VCC—Cable ICC (Note 5)(Note 7) : LOW State Leakage to VCC IOFF—ICC2 V Current in Input Leakage IOFF—ICC Conditions 3.0 Maximum Pull-Up Maximum Input Units 3.0 Impedance RP 40qC to 85qC Guaranteed Limits 3.0 Impedance Minimum Output (V) 3.0 An, HLH Level Output Voltage VCC—Cable TA Note 5: Output impedance is measured with the output active LOW and active HIGH (HD HIGH). Note 6: Power-down leakage to V CC or VCC—Cable is tested by simultaneously forcing all pins on the cable-side (B1–B8, Y9–Y13, PLH, C14–C17 and HLHIN) to 5.5V and measuring the resulting ICC or ICC—Cable. Note 7: This parameter is guaranteed but not tested, characterized only. www.fairchildsemi.com 4 TA Symbol 40qC to 85qC VCC Parameter 3.0V–3.6V VCC—Cable Units Figure Number Figure 1 4.5V–5.5V Min Max tPHL A1–A8 to B1–B8 1.0 8.5 ns tPLH A1–A8 to B1–B8 1.0 8.5 ns Figure 2 tPHL B1–B8 to A1–A8 1.0 14.0 ns Figure 3 tPLH B1–B8 to A1–A8 1.0 14.0 ns Figure 3 tPHL A9–A13 to Y9–Y13 1.0 8.5 ns Figure 1 tPLH A9–A13 to Y9–Y13 1.0 8.5 ns Figure 2 tPHL C14–C17 to A14–A 17 1.0 10.0 ns Figure 3 tPLH C14–C17 to A14–A 17 1.0 10.0 ns Figure 3 tSKEW LH-LH or HL-HL 2.0 ns (Note 8) tPHL PLHIN to PLH 8.5 ns Figure 1 tPLH PLHIN to PLH 1.0 8.5 ns Figure 2 tPHL HLHIN to HLH 1.0 10.0 ns Figure 3 tPLH HLHIN to HLH 1.0 12.0 ns Figure 3 tPHZ Output Disable Time 1.0 10.0 ns Figure 4 ns Figure 5 ns Figure 6 1.0 tPLZ DIR to A1–A8 1.0 10.0 tPZH Output Enable Time 1.0 10.0 tPZL DIR to A1–A8 1.0 10.0 tPHZ Output Disable Time 1.0 13.0 tPLZ DIR to B1–B8 1.0 10.0 tpEN Output Enable Time 1.0 8.0 ns Figure 2 1.0 12.0 ns Figure 2 HD to B1–B8, Y9–Y13 tpDIS Output Disable Time HD to B1–B8, Y9–Y13 Note 8: tSKEW is measured for common edge output transitions and compares the measured propagation delay for a given path type: (i) A1–A8 to B1–B8, A9–A13 to Y9–Y13 (ii) B1–B8 to A1–A8 (iii) C14–C17 to A14–A17 Capacitance Symbol Parameter CIN Input Capacitance CI/O (Note 9) I/O Pin Capacitance Note 9: CI/O is measured at frequency Typ Units 3 pF VCC 0.0V (HD, DIR, A9–A13, C14–C17, PLHIN and HLHIN) Conditions 5 pF VCC 3.3V 1 MHz, per MIL-STD-883B, Method 3012 5 www.fairchildsemi.com 74LVX161284A AC Electrical Characteristics 74LVX161284A AC Loading and Waveforms Pulse Generator for all pulses: Rate d1.0 MHz; ZO d 50:; tf d 2.5 ns, tr d 2.5 ns. FIGURE 1. Port A to B and A to Y Propagation Delay Waveforms FIGURE 2. Port A to B and A to Y Output Waveforms FIGURE 3. Port B to A, C to A and HLHin to HLH Propagation Delay Waveforms www.fairchildsemi.com 6 74LVX161284A AC Loading and Waveforms (Continued) FIGURE 4. tPHZ and tPLZ Test Load and Waveforms, DIR to A1 - A8 FIGURE 5. tPHZ and tPLZ Test Load and Waveforms, DIR to A1 - A8 7 www.fairchildsemi.com 74LVX161284A AC Loading and Waveforms (Continued) FIGURE 6. tPHZ and tPLZ Test Load and Waveforms, DIR to B1–B8 www.fairchildsemi.com 8 74LVX161284A Low Voltage IEEE 161284 Translating Transceiver Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com