Revised June 2005
74VCX16240
Low Voltage 16-Bit Inverting Buffer/Line Driver with
3.6V Tolerant Inputs and Outputs
General Description
Features
The VCX16240 contains sixteen inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74VCX16240 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V.
■ 1.2V to 3.6V VCC supply operation
The 74VCX16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
■ 3.6V tolerant inputs and outputs
■ tPD
2.5 ns max for 3.0V to 3.6V VCC
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
■ Static Drive (IOH/IOL)
r24 mA @ 3.0V VCC
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model ! 2000V
Machine model ! 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package Number
Package Descriptions
74VCX16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
Pin Descriptions
DS500099
Pin Names
Description
OEn
Output Enable Input (Active LOW)
I0–I15
Inputs
O0–O15
Outputs
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74VCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
January 1998
74VCX16240
Connection Diagram
Truth Tables
Inputs
Outputs
OE1
I0–I3
O0–O3
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE2
I4–I7
O4–O7
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE3
I8–I11
O8–O11
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE4
I12–I15
O12–O15
L
L
H
L
H
L
H
X
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial (HIGH or LOW, inputs may not float)
Z High Impedance
Functional Description
trolled by an Output Enable (OEn) input. When OEn is
LOW, the outputs are in the 2-state mode. When OEn is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the inputs.
The 74VCX16240 contains sixteen inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
each other. The control pins may be shorted together to
obtain full 16-bit operation.The 3-STATE outputs are con-
Logic Diagram
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2
Recommended Operating
Conditions (Note 4)
0.5V to 4.6V
0.5V to 4.6V
Supply Voltage (VCC)
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Operating
Outputs 3-STATED
Outputs Active (Note 3)
DC Input Diode Current (IIK) VI 0V
0.5V to 4.6V
0.5V to VCC 0.5V
50 mA
Output Voltage (VO)
Output in Active States
DC Output Diode Current (IOK)
50 mA
50 mA
VO ! VCC
r50 mA
(IOH/IOL)
0.0V to 3.6V
Output Current in IOH/IOL
DC Output Source/Sink Current
DC VCC or GND Current per
Storage Temperature Range (TSTG)
0V to VCC
Output in 3-STATE
VO 0V
Supply Pin (ICC or GND)
1.2V to 3.6V
0.3V to 3.6V
Input Voltage
r100 mA
65qC to 150qC
VCC
3.0V to 3.6V
VCC
2.3V to 2.7V
VCC
1.65V to 2.3V
VCC
1.4V to 1.6V
VCC
1.2V
Free Air Operating Temperature (TA)
r24 mA
r18 mA
r6 mA
r2 mA
r100 PA
40qC to 85qC
Minimum Input Edge Rate ('t/'V)
VIN
0.8V to 2.0V, VCC
3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
Parameter
Conditions
VCC
Min
Max
Units
(V)
VIH
VIL
HIGH Level Input Voltage
2.7 - 3.6
LOW Level Input Voltage
2.0
2.3 - 2.7
1.6
1.65 - 2.3
0.65 u VCC
1.4 - 1.6
0.65 u VCC
1.2
0.65 u VCC
2.7–3.6
0.8
2.3–2.7
0.7
1.652.3
0.35 u V CC
1.4 - 1.6
0.35 u V CC
HIGH Level Output Voltage
IOH
100 PA
2.7–3.6
VCC 0.2
IOH
12 mA
2.7
2.2
IOH
18 mA
3.0
2.4
IOH
24 mA
3.0
2.2
IOH
100 PA
2.3–2.7
VCC 0.2
IOH
6 mA
2.3
2.0
IOH
12 mA
2.3
1.8
IOH
18 mA
2.3
1.7
IOH
100 PA
1.652.3
VCC 0.2
IOH
6 mA
IOH
100 PA
IOH
2 mA
1.4
1.05
IOH
100 PA
1.2
VCC 0.2
3
V
0.05 u V CC
1.2
VOH
V
1.65
1.25
1.4 - 1.6
VCC 0.2
V
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74VCX16240
Absolute Maximum Ratings(Note 2)
74VCX16240
DC Electrical Characteristics
Symbol
(Continued)
Parameter
Conditions
VCC
Min
Max
Units
(V)
VOL
LOW Level Output Voltage
IOL
100 PA
2.7–3.6
0.2
IOL
12 mA
2.7
0.4
IOL
18 mA
3.0
0.4
IOL
24 mA
3.0
0.55
IOL
100 PA
2.3–2.7
0.2
IOL
12 mA
2.3
0.4
IOL
18 mA
2.3
0.6
IOL
100 PA
1.652.3
0.2
IOL
6 mA
1.65
0.3
IOL
100 PA
IOL
2 mA
IOL
100 PA
II
Input Leakage Current
0 d VI d 3.6V
IOZ
3-STATE Output Leakage
0 d VO d 3.6V
VI
VIH or VIL
IOFF
Power-OFF Leakage Current
0 d (VI, VO) d 3.6V
ICC
Quiescent Supply Current
VI
'ICC
Increase in ICC per Input
VIH
VCC or GND
VCC d (VI, VO) d 3.6V (Note )
VCC 0.6V
Note 5: Outputs disabled or 3-STATE only.
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4
1.4 - 1.6
0.2
1.4
0.35
V
1.2
0.05
1.2–3.6
r5.0
PA
1.2–3.6
r10
PA
0
10
PA
1.2–3.6
20
1.2–3.6
r20
2.7–3.6
750
PA
PA
Symbol
tPHL
(Note 6)
Parameter
Propagation Delay
VCC
Conditions
CL
30 pF, RL
500:
tPZL
Output Enable Time
CL
15 pF, RL
30 pF, RL
tPLZ
Output Disable Time
CL
15 pF, RL
30 pF, RL
tOSHL
Output to Output Skew
tOSLH
(Note 7)
CL
CL
Note 6: For CL
15 pF, RL
30 pF, RL
15 pF, RL
2.5
0.8
1.0
3.0
1.8 r 0.15
1.5
6.0
1.5 r 0.1
1.0
12.0
1.2
1.5
30.0
2k:
500:
0.8
3.5
1.0
4.1
1.8 r 0.15
1.5
8.2
1.5 r 0.1
1.0
16.4
1.2
1.5
41.0
3.5
500:
ns
3.3 r 0.3
0.8
1.0
3.8
1.8 r 0.15
1.5
6.8
1.5 r 0.1
1.0
13.6
1.2
1.5
34.2
500:
3.3 r 0.3
Figures
5, 7, 8
Figures
1, 3, 4
ns
Figures
5, 7, 8
0.5
2.5 r 0.2
0.5
1.8 r 0.15
0.75
1.5 r 0.1
1.5
1.2
1.5
2k:
Figures
5, 6
Figures
1, 3, 4
2.5 r 0.2
2k:
Figure
Number
Figures
1, 2
3.3 r 0.3
2k:
Units
ns
2.5 r 0.2
tPHZ
CL
Max
3.3 r 0.3
tPZH
CL
40qC to 85qC
Min
2.5 r 0.2
tPLH
CL
TA
(V)
ns
50PF, add approximately 300 ps to the AC maximum specification.
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
VOHV
Parameter
VCC
Conditions
Quiet Output Dynamic Peak VOL
CL
Quiet Output Dynamic Valley VOL
CL
Quiet Output Dynamic Valley VOH
CL
30 pF, VIH
VCC, VIL
30 pF, VIH
VCC, VIL
30 pF, VIH
VCC, VIL
0V
0V
0V
TA
25qC
(V)
Typical
1.8
0.25
2.5
0.6
3.3
0.8
1.8
0.25
2.5
0.6
3.3
0.8
1.8
1.5
2.5
1.9
3.3
2.2
Units
V
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
COUT
Output Capacitance
VI
0V or VCC, VCC
1.8, 2.5V or 3.3V, VI
CPD
Power Dissipation Capacitance
VI
0V or VCC, f
5
0V or VCC
1.8V, 2.5V or 3.3V
10 MHz, VCC
1.8V, 2.5V or 3.3V
TA
25qC
Typical
Units
6.0
pF
7.0
pF
20.0
pF
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74VCX16240
AC Electrical Characteristics
74VCX16240
AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC 3.3 r 0.3V;
VCC x 2 at VCC 2.5 r 0.2V; 1.8V r 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
Symbol
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VCC
3.3V r 0.3V
2.5V r 0.2V
1.8V r 0.15V
Vmi
1.5V
VCC/2
VCC/2
Vmo
1.5V
VCC/2
VCC/2
VX
VOL 0.3V
VOL 0.15V
VOL 0.15V
VY
VOH 0.3V
VOH 0.15V
VOH 0.15V
6
74VCX16240
AC Loading and Waveforms (VCC 1.5V to 1.2V r 0.1V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VCC x 2 at VCC
tPZH, tPHZ
1.5 r 0.1V
GND
FIGURE 5. AC Test Circuit
FIGURE 6. Waveform for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V r 0.1V
VCC/2
Vmi
Vmo
VCC/2
VX
VOL 0.1V
VY
VOH 0.1V
7
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74VCX16240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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8