Revised November 2002 74VCX32374 Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs General Description Features The VCX32374 contains thirty-two non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to each byte and can be shorted together for full 32-bit operation. The 74VCX32374 is designed for low voltage (1.2V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX32374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 1.2V to 3.6V VCC supply operation ■ 3.6V tolerant inputs and outputs ■ tPD 3.0 ns max for 3.0V to 3.6V VCC ■ Power-off high impedance inputs and outputs ■ Supports live insertion and withdrawal (Note 1) ■ Static Drive (IOH/IOL) ±24 mA @ 3.0V VCC ■ Uses patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 300 mA ■ ESD performance: Human body model > 2000V Machine model > 200V ■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number 74VCX32374G (Note 2)(Note 3) BGA96A Package Descriptions 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Note 2: Ordering code “G” indicates Trays. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2002 Fairchild Semiconductor Corporation DS500402 www.fairchildsemi.com 74VCX32374 Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs December 2000 74VCX32374 Connection Diagram Pin Descriptions Pin Names Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0–I31 Inputs O0–O31 Outputs FBGA Pin Assignments (Top Thru View) 1 2 3 4 5 6 A O1 O0 OE1 CP1 I0 I1 B O3 O2 GND GND I2 I3 C O5 O4 VCC VCC I4 I5 D O7 O6 GND GND I6 I7 E O9 O8 GND GND I8 I9 F O11 O10 VCC VCC I10 I11 G O13 O12 GND GND I12 I13 H O14 O15 OE2 CP2 I15 I14 J O17 O16 OE3 CP3 I16 I17 K O19 O18 GND GND I18 I19 L O21 O20 VCC VCC I20 I21 M O23 O22 GND GND I22 I23 N O25 O24 GND GND I24 I25 P O27 O26 VCC VCC I26 I27 R O29 O28 GND GND I28 I29 T O30 O31 OE4 CP4 I31 I30 Truth Tables Inputs CP1 Outputs OE1 I0–I7 O0–O7 L H H L L L L L X O0 X H X Z OE3 I16–I23 O16–O23 L H H L L L L L X O0 X H X Z Inputs CP3 Inputs CP2 I8–I15 O8–O15 L H H L L L L L X O0 X H X Z OE4 I24–I31 O24–O31 L H H L L L L L X O0 X H X Z Outputs Inputs CP4 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP www.fairchildsemi.com Outputs OE2 2 Outputs flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. The 74VCX32374 consists of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 32-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each Logic Diagrams Byte 1 (0:7) Byte 2 (8:15) Byte 3 (16:23) Byte 4 (24:31) Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74VCX32374 Functional Description 74VCX32374 Absolute Maximum Ratings(Note 4) Recommended Operating Conditions (Note 6) Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Power Supply −0.5V to +4.6V Input Voltage Output Voltage (VO) Operating Outputs 3-STATED Outputs Active (Note 5) −0.5V to VCC +0.5V DC Input Diode Current (IIK) VI < 0V Output Voltage (VO) −50 mA Output in Active States DC Output Diode Current (IOK) 0V to VCC Output in 3-STATE VO < 0V −50 mA VO > VCC +50 mA ±50 mA (IOH/IOL) 0.0V to 3.6V Output Current in IOH/IOL DC Output Source/Sink Current VCC = 3.0V to 3.6V ±24 mA VCC = 2.3V to 2.7V ±18 mA VCC = 1.65V to 2.3V ±6 mA VCC = 1.4V to 1.6V DC VCC or GND Current per ±100 mA Supply Pin (ICC or GND) Storage Temperature Range (TSTG) 1.2V to 3.6V −0.3V to +3.6V ±2 mA VCC = 1.2V −65°C to +150 °C ±100 µA Free Air Operating Temperature (TA) −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused inputs must be held HIGH or LOW. DC Electrical Characteristics Symbol Parameter Conditions VCC Min Max Units (V) VIH VIL HIGH Level Input Voltage 2.7 - 3.6 LOW Level Input Voltage 2.0 2.3 - 2.7 1.6 1.65 - 2.3 0.65 x VCC 1.4 - 1.6 0.65 x VCC 1.2 0.65 x VCC 2.7 - 3.6 0.8 2.3 - 2.7 0.7 1.65 - 2.3 0.35 x VCC 1.4 - 1.6 0.35 x VCC 1.2 VOH HIGH Level Output Voltage 2.7 - 3.6 VCC - 0.2 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOH = −100 µA 2.3 - 2.7 VCC - 0.2 IOH = −6 mA 2.3 2.0 IOH = −12 mA 2.3 1.8 IOH = −18 mA 2.3 1.7 IOH = −100 µA 1.65 - 2.3 VCC - 0.2 IOH = −100 µA www.fairchildsemi.com 1.65 1.25 1.4 - 1.6 VCC - 0.2 IOH = −2 mA 1.4 1.05 IOH = −100 µA 1.2 VCC - 0.2 4 V 0.05 x VCC IOH = −100 µA IOH = −6 mA V V Symbol (Continued) Parameter VCC Conditions Min Max Units (V) VOL LOW Level Output Voltage IOL = 100 µA 2.7 − 3.6 0.2 IOL = 12 mA 2.7 0.4 IOL = 18 mA 3.0 0.4 IOL = 24 mA 3.0 0.55 IOL = 100 µA 2.7 - 2.7 0.2 IOL = 12 mA 2.3 0.4 IOL = 18 mA 2.3 0.6 IOL = 100 µA 1.65 - 2.3 0.2 IOL = 6 mA V 1.65 0.3 1.4 - 1.6 0.2 IOL = 2 mA 1.4 0.35 IOL = 100 µA 1.2 0.05 1.2 - 3.6 ±5.0 µA 1.2 - 3.6 ±10 µA µA IOL = 100 µA II Input Leakage Current 0 ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V VI = V IH or VIL IOFF Power-OFF Leakage Current 0 ≤ (VI, VO) ≤ 3.6V 0 10 ICC Quiescent Supply Current VI = V CC or GND 1.2 - 3.6 40 µA VCC ≤ (VI, VO) ≤ 3.6V (Note 7) 1.2 - 3.6 ±40 µA VIH = VCC −0.6V 2.7 - 3.6 750 µA ∆ICC Increase in ICC per Input Note 7: Outputs disabled or 3-STATE only. AC Electrical Characteristics Symbol fMAX Parameter Maximum Clock Frequency (Note 8) VCC Conditions Min 3.3 ± 0.3 250 2.5 ± 0.2 200 1.8 ± 0.15 100 CL = 15 pF, RL = 2kΩ 1.5 ± 0.1 80 1.2 40 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 0.8 3.0 2.5 ± 0.2 1.0 3.9 CL = 30 pF, RL = 500Ω Setup Time tPHL, Propagation Delay tPLH CL = 15 pF, RL = 2kΩ tPZL, Output Enable Time CL = 30 pF, RL = 500Ω tPZH CL = 15 pF, RL = 2kΩ tPLZ, Output Disable Time CL = 30 pF, RL = 500Ω tPHZ CL = 15 pF, RL = 2kΩ tS Setup Time TA = −40°C to +85°C (V) CL = 30 pF, RL = 500Ω CL = 15 pF, RL = 500Ω 5 Max Units Figure Number MHz 1.8 ± 0.15 1.5 7.8 1.5 ± 0.1 1.0 15.6 1.2 1.5 39 3.3 ± 0.3 0.8 3.5 2.5 ± 0.2 1.0 4.6 1.8 ± 0.15 1.5 9.2 1.5 ± 0.1 1.0 18.4 1.2 1.5 46 3.3 ± 0.3 0.8 3.5 2.5 ± 0.2 1.0 3.8 1.8 ± 0.15 1.5 6.8 1.5 ± 0.1 1.0 13.6 1.2 1.5 34 3.3 ± 0.3 1.5 2.5 ± 0.2 1.5 1.8 ± 0.15 2.5 1.5 ± 0.1 3 1.2 6 Figures 1, 2 ns Figures 7, 8 Figures 1, 3, 4 ns Figures 7, 9, 10 Figures 1, 3, 4 ns Figures 7, 9, 10 Figures 1, 6 ns Figures 6, 7 www.fairchildsemi.com 74VCX32374 DC Electrical Characteristics 74VCX32374 AC Electrical Characteristics Symbol Parameter VCC Conditions CL = 30 pF, RL = 500Ω Hold Time tH (Continued) CL = 15 pF, RL = 500Ω tW CL = 30 pF, RL = 500Ω Pulse Width CL = 15 pF, RL = 500Ω TA = −40°C to +85°C (V) Min 3.3 ± 0.3 1.0 2.5 ± 0.2 1.0 1.8 ± 0.15 1.0 1.5 ± 0.1 2.0 1.2 6 3.3 ± 0.3 1.5 2.5 ± 0.2 1.5 1.8 ± 0.15 4.0 1.5 ± 0.1 4.0 1.2 8 Units Max Figure Number Figures 1, 6 ns Figures 6, 7 Figures 1, 5 ns Figures 5, 7 Note 8: For CL = 50PF, add approximately 300 ps to the AC maximum specification. Dynamic Switching Characteristics Symbol VOLP VOLV VOHV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Quiet Output Dynamic Valley VOH Conditions CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V V CC (V) TA = +25°C Units Typical 1.8 0.25 2.5 0.6 3.3 0.8 1.8 −0.25 2.5 −0.6 3.3 −0.8 1.8 1.5 2.5 1.9 3.3 2.2 V V V Capacitance Symbol Parameter Conditions TA = +25°C Units Typical CIN Input Capacitance VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC 6 pF COUT Output Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V 7 pF CPD Power Dissipation Capacitance 20 pF VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V www.fairchildsemi.com 6 74VCX32374 AC Loading and Waveforms (VCC 3.3V ± 0.3V to 1.8V ± 0.15V) TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3V ± 0.3V; VCC x 2V at VCC = 2.5V ± 0.2V; 1.8V ± 0.15V tPZH, tPHZ GND FIGURE 1. AC Test Circuit FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms Symbol VCC 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VX VOL + 0.3V VOL + 0.15V VOL + 0.15V VY VOH − 0.3V VOH − 0.15V VOH − 0.15V 7 www.fairchildsemi.com 74VCX32374 AC Loading and Waveforms (VCC 1.5V± 0.1V to 1.2V) TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VCC x 2V at VCC = 1.5V ± 0.1V tPZH, tPHZ GND FIGURE 7. AC Test Circuit FIGURE 8. Waveform for Inverting and Non-Inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic VCC Symbol 1.5V ± 0.1V VCC/2 Vmi www.fairchildsemi.com Vmo VCC/2 VX VOL + 0.1V VY VOH − 0.1V 8 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74VCX32374 Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted