IRF 74VCX16827

Revised October 2002
74VCX16827
Low Voltage 20-Bit Buffer/Line Driver with
3.6V Tolerant Inputs and Outputs
General Description
Features
The VCX16827 contains twenty non-inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver carrying parity. The device is byte controlled. Each
byte has NOR output enables for maximum control flexibility.
The 74VCX16827 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX16827 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
■ 1.2V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ tPD
2.5 ns max for 3.0V to 3.6V VCC
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
■ Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package Number
Package Description
74VCX16827MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
© 2002 Fairchild Semiconductor Corporation
DS500131
Description
OEn
Output Enable Input (Active LOW)
I0–I19
Inputs
O0–O19
Outputs
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74VCX16827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
March 1998
74VCX16827
Connection Diagram
Truth Tables
Inputs
Outputs
OE1
OE2
I0–I9
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
Inputs
O0–O9
Outputs
OE3
OE4
I0–I9
O10–O19
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Functional Description
The 74VCX16827 contains twenty non-inverting buffers
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of each
other. The control pins may be shorted together to obtain
full 16-bit operation. The 3-STATE outputs are controlled by
Output Enable (OEn) inputs. When OE1, and OE2 are
LOW, O0—O10 are in the 2-state mode. When either OE1
or OE2 are HIGH, the standard outputs are in the high
impedance mode but this does not interfere with entering
new data into the inputs. The same applies for byte two
with OE3 and OE4.
Logic Diagrams
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2
Recommended Operating
Conditions (Note 4)
Supply Voltage (VCC)
−0.5V to +4.6V
DC Input Voltage (VI)
−0.5V to +4.6V
Power Supply
−0.5V to +4.6V
Input Voltage
Output Voltage (VO)
Operating
Outputs 3-STATED
Outputs Active (Note 3)
−0.5V to VCC + 0.5V
DC Input Diode Current (IIK) VI < 0V
Output Voltage (VO)
−50 mA
Output in Active States
DC Output Diode Current (IOK)
0V to VCC
Output in 3-STATE
VO < 0V
−50 mA
VO > VCC
+50 mA
±50 mA
(IOH/IOL)
0.0V to 3.6V
Output Current in IOH/IOL
DC Output Source/Sink Current
VCC = 3.0V to 3.6V
±24 mA
VCC = 2.3V to 2.7V
±18 mA
VCC = 1.65V to 2.3V
±6 mA
VCC = 1.4V to 1.6V
DC VCC or GND Current per
±100 mA
Supply Pin (ICC or GND)
Storage Temperature Range (TSTG)
1.2V to 3.6V
−0.3V to +3.6V
±2 mA
VCC = 1.2V
−65°C to +150°C
± 100 µA
Free Air Operating Temperature (TA)
−40°C to +85°C
Minimum Input Edge Rate (∆t/∆V)
VIN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
Parameter
Conditions
VCC
Min
Max
Units
(V)
VIH
VIL
HIGH Level Input Voltage
2.7 - 3.6
LOW Level Input Voltage
2.0
2.3 - 2.7
1.6
1.65 - 2.3
0.65 x VCC
1.4 - 1.6
0.65 x VCC
1.2
0.65 x VCC
2.7 - 3.6
0.8
2.3 - 2.7
0.7
1.65 - 2.3
0.35 x VCC
1.4 - 1.6
0.35 x VCC
1.2
VOH
HIGH Level Output Voltage
2.7 - 3.6
VCC - 0.2
IOH = −12 mA
2.7
2.2
IOH = −18 mA
3.0
2.4
IOH = −24 mA
3.0
2.2
IOH = −100 µA
2.3 - 2.7
VCC - 0.2
IOH = −6 mA
2.3
2.0
IOH = −12 mA
2.3
1.8
IOH = −18 mA
2.3
1.7
IOH = −100 µA
1.65 - 2.3
VCC - 0.2
IOH = −100 µA
1.65
1.25
1.4 - 1.6
VCC - 0.2
IOH = −2 mA
1.4
1.05
IOH = −100 µA
1.2
VCC - 0.2
3
V
0.05 x VCC
IOH = −100 µA
IOH = −6 mA
V
V
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74VCX16827
Absolute Maximum Ratings(Note 2)
74VCX16827
DC Electrical Characteristics
Symbol
(Continued)
Parameter
Conditions
VCC
Min
Max
Units
(V)
VOL
LOW Level Output Voltage
IOL = 100 µA
2.7 - 3.6
0.2
IOL = 12 mA
2.7
0.4
IOL = 18 mA
3.0
0.4
IOL = 24 mA
3.0
0.55
IOL = 100 µA
2.3 - 2.7
0.2
IOL = 12 mA
2.3
0.4
IOL = 18 mA
2.3
0.6
IOL = 100 µA
1.65 - 2.3
0.2
IOL = 6 mA
1.65
0.3
1.4 - 1.6
0.2
IOL = 2 mA
1.4
0.35
IOL = 100 µA
1.2
0.05
1.2 - 3.6
±5.0
µA
1.2 − 3.6
±10
µA
µA
IOL = 100 µA
II
Input Leakage Current
0 ≤ VI ≤ 3.6V
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
IOFF
Power-OFF Leakage Current
0 ≤ (VI, VO) ≤ 3.6V
0
10
ICC
Quiescent Supply Current
VI = VCC or GND
1.2 - 3.6
20
VCC ≤ (VI, VO) ≤ 3.6V (Note 5)
1.2 - 3.6
±20
∆ICC
Increase in ICC per Input
VIH = VCC −0.6V
2.7 - 3.6
750
Note 5: Outputs disabled or 3-STATE only.
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V
4
µA
µA
Symbol
tPHL,
Parameter
(Note 6)
VCC
Conditions
CL = 30 pF, RL = 500Ω
Propagation Delay
tPLH
CL = 15 pF, RL = 2kΩ
tPZL,
CL = 30 pF, RL = 500Ω
Output Enable Time
tPZH
CL = 15 pF, RL = 2kΩ
TA = −40°C to +85°C
(V)
Min
Max
3.3 ± 0.3
0.8
2.5
2.5 ± 0.2
1.0
3.0
1.8 ± 0.15
1.5
6.0
1.5 ± 0.1
1.0
12.0
1.2
1.5
30
3.3 ± 0.3
0.8
3.8
2.5 ± 0.2
1.0
4.9
1.8 ± 0.15
1.5
9.8
1.5 ± 0.1
1.0
19.6
1.2
tPLZ,
Output Disable Time
CL = 30 pF, RL = 500Ω
tPHZ
CL = 15 pF, RL = 2kΩ
tOSHL
Output to Output Skew
tOSLH
(Note 7)
CL = 30 pF, RL = 500Ω
CL = 15 pF, RL = 2kΩ
Units
Figures
1, 2
ns
Figures
5, 6
Figures
1, 3, 4
ns
Figures
5, 7, 8
49
3.3 ± 0.3
0.8
2.5 ± 0.2
1.0
4.2
1.8 ± 0.15
1.5
7.6
1.5 ± 0.1
1.0
15.2
Figure
Number
3.7
1.2
38
3.3 ± 0.3
0.5
2.5 ± 0.2
0.5
1.8 ± 0.15
0.75
1.5 ± 0.1
1.5
1.2
1.5
Figures
1, 3, 4
ns
Figures
5, 7, 8
ns
Note 6: For CL = 50 PF, add approximately 300 ps to the AC maximum specification.
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
VOHV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCC
TA = +25°C
(V)
Typical
1.8
0.25
2.5
0.6
3.3
0.8
1.8
−0.25
2.5
−0.6
3.3
−0.8
1.8
1.5
2.5
1.9
3.3
2.2
Units
V
V
V
Capacitance
Symbol
Parameter
Conditions
TA = +25°C
Typical
Units
CIN
Input Capacitance
VCC = 1.8, 2.5V or 3.3V, VI = 0V or VCC
6
pF
COUT
Output Capacitance
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
7
pF
CPD
Power Dissipation Capacitance
VI = 0V or VCC, f = 10 MHz,
20
pF
VCC = 1.8V, 2.5V or 3.3V
5
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74VCX16827
AC Electrical Characteristics
74VCX16827
AC Loading and Waveforms (VCC 3.3V ± 0.3V to 1.8V ± 0.15V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3V ± 0.3V;
VCC x 2 at VCC = 2.5V ± 0.2V; 1.8V ± 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
Symbol
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VCC
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
Vmi
1.5V
VCC/2
VCC/2
Vmo
1.5V
VCC/2
VCC/2
VX
VOL + 0.3V
VOL + 0.15V
VOL + 0.15V
VY
VOH − 0.3V
VOH − 0.15V
VOH − 0.15V
6
74VCX16827
AC Loading and Waveforms (VCC 1.5V ± 0.1V to 1.2V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VCC x 2 at VCC = 1.5V ± 0.1V
tPZH, tPHZ
GND
FIGURE 5. AC Test Circuit
FIGURE 6. Waveform for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
2.5V ± 0.2V
VCC/2
Vmi
Vmo
VCC/2
VX
VOL + 0.15V
VY
VOH − 0.15V
7
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74VCX16827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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