ETC 7P160FLF1201C25

PCMCIA Flash Memory Card
FLF10 Series
High Density FLASH Memory Card
32, 64, 96, 128, 160, 192 MEGABYTE
General Description
Features
WEDC’s Flash memory cards - FLF10 Series - offer high density
linear Flash memory for code and data storage, high performance
disk emulation, mobile PC and embedded applications.
• Low cost, high density Linear Flash
Card
The WEDC FLF10 series is based on Intel’s Multi Level Cell
(MLC) Flash memory technology, providing high density Flash
components at a significantly lower cost per megabyte. MLC
technology allows for two bits of information to be stored in a single
cell. This leads to reduced die size and reduced cost per megabyte.
WEDC’s FLF10 series cards are built with Intel’s 128Mb memory
component, 28F128J3A, with a manufacturer/device ID of 89/18H.
The FLF10 series is available in densities of 32, 64, 96, 128, 160,
and 192MB.
WEDC’s FLF10 series provides densities from 32MB to 192MB, in
32MB increments. The cards up to the 64MB density operate in the
regular PCMCIA mode. The densities beyond the 64MB density
are implemented using a “paging scheme”, which is also supported
by the PCMCIA standard. By writing a page address to the
Configuration Option Register (address 4000H), an additional page
of memory can be accessed. The current FLF10 series supports
densities to 192MB: total of 3 pages: page 0 := 64MB, page 1 :=
64MB, and page 2 := 64MB.
The FLF10 series card operates in a wide, universal voltage range,
from 3V to 5V, allowing full “plug and play” functionality and
upgrade solutions in all mobile, battery powered applications.
Each memory component in the card also has a 128-bit Protection
Register, containing 64 bits of User Programmable OTP (One Time
Programmable) Cells. These cells can be programmed with a
numeric security measure, such as an electronic signature.
To provide a 16 bit word wide access supported by the PCMCIA
standard, devices are paired on the card. Therefore, the Flash array
is structured in 128K word (256kB) blocks. Write, read and block
erase operations can be performed as either a word or byte wide
operation.
• Universal 3V to 5V operating range
providing full “plug and play”
exchangeability between different
systems
• Based on Intel 28F128J3A (MLC)
Components
• Fast Read Performance
- 250ns Maximum Access Time
- (200ns optional)
•PCMCIA compatible
- x8/ x16 Data Interface
• 32-Byte Write Buffer (per Memory
Device)
- 6µs per Byte Effective Write Time
•128-bit Protection Register (per Memory
Device)
-64-bit Unique Device Identifier
-64-bit User Programmable OTP
Cells
•Cross-Compatible Command Support
- Common Flash Interface (CFI)
- Intel Basic Command Set
- Scaleable Command Set
• Power-Down Mode
- Reset, Power Down Registers
• 100,000 Erase Cycles per Block
• 128K word symmetrical Block
Architecture
• PC Card Standard Type I Form Factor
The FLF10 series cards conform to the PC Card 95 Standard
supported by PCMCIA and JEIDA, providing electrical and
physical compatibility. The PC Card form factor offers an industry
standard pinout and mechanical outline, allowing density upgrades
without system design changes.
WEDC’s standard cards are shipped with WEDC’s Flash Logo.
Cards are also available with blank housings (no Logo). The blank
housings are available in both, a recessed (for label) or flat housing.
Please contact your WEDC sales representative for further
information on Custom artwork.
November 2000 Rev. 3 - ECO #13392
1
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
Block Diagram
N x 28F128J3A
Device Pair (N/2 - 1)
CLn
Device (N-1)
CH0
Device (N-2)
(B26)
+
ADDRESS BUS
(A1-A25)
(A1-A25)
A1-A23
A1-A25
ADDRESS
BUFFER
A24, A25, B26
B26, (B27..)
D5-D0=Page Number (PN)
SRes
LvReq
D7
/WRi
/RDi
M Res
Ai
CH0
CLn
Device 3
CL1
Device 2
CL0
D4
Q2
Q0
Ctrl
control
logic
CL0
Device 1
SR Clr
Reg Clr
/REG
At/Reg enable
Registers
D1
D0
Register NAME
Config. and Status Reg.
Configuration Option Register
attrib. mem
CIS
E²PROM 2kB
0000h
DATA
BUS
Q0-Q7
ADDRESS
4008h
4006h
4004h
4002h
4000h
Management
4000h
Device 0
DATA
BUS
Q8-Q15
D2
/CE2
/CE1
Device Pair 0
CH0
D3
/WE
/OE
Qn
CH0
- Page Number (PN) D5
Configuration Option Register: A=4000h (Read/Write)
CHn
Device Pair 1
D6
control
Q0-Q7
A0
I/O buffer
DATA
BUS
D8-D15
DATA
BUS
D0-D7
Reset
220k
M Res
SR Clr
Reg Clr
reset circuit
C
R
Vcc
D0 - D15
Configuration Option Register: ADRS=4000h
Read/Write
CD1
CD2
SRes
D7
(3V-5V)
Vcc
Vcc
LvReq
D6
D7
OPEN
R/B(N-1)
D6
VS1
VS2
R/B1
R/B0
OPEN
OPEN
Vpp2
Vpp1
Configuration index
D5-D2 reserved
D0:D1
Page Number Config. (PN)
Power On default =0
Configuration Status Register: ADRS=4002h
Read/Write
10k
BVD1
BVD2
D0
LevelReq (not supported)
D5-D0
R/BUSY
- Page Number (PN) D4
D3
D2
D1
Soft Reset, active High
1=Reset State
0=End Reset State
GND
WAIT
D5
Vcc
D7
D2
N.C.
N.C.
reserved
PwrDwn reserved
D6
D5
D4
D3
D2
D1
D0
Power Down; active High
1 = Place all memory devices in power down mode
0 = normal operation
Power On default=0
/CE1, /CE2,/OE, /WE, /Reg:
pull up
A0:
pull down typ 100k
typ 100k
Manufacturer ID
Reset:
pull down typ 220k
Device ID
R/Busy - Open Drain output
pull up
typ 100k
Intel
89H
28F128J3A
18H
FLF10 Flash Card
based on Strata Flash 28F128J3A
November 2000 Rev. 3 - ECO #13392
2
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal name
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
RDY/BSY#
Vcc
Vpp1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
LOW
LOW
LOW
LOW(1)
N.C.
HIGH
Signal name I/O
GND
CD1#
O
DQ11
I/O
DQ12
I/O
DQ13
I/O
DQ14
I/O
DQ15
I
CE2#
I
VS1
O
RFU
RFU
A17
I
A18
I
A19
I
A20
I
A21
I
Vcc
Vpp2
A22
I
A23
I
A24
I
A25
I
VS2
O
RST
I
Wait#
O
RFU
REG#
I
BVD2
O
BVD1
O
DQ8
I/O
DQ9
I/O
DQ10
O
CD2#
O
GND
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Reserved
Reserved
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
Extended Bus cycle
Reserved
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
Active
LOW
LOW
NC (2)
N.C.
N.C.
HIGH
LOW(3)
(3)
(3)
LOW
Notes:
1. RDY/BSY signal is an open drain type output, pull-up resistors are required on the host side.
2. VS1 is connected to GND.
3. Wait#, BVD1 and BVD2 are internally connected to Vcc by resistors for compatibility.
Mechanical
Interconnect area
1.0mm ± 0.05
(0.039”)
1.6mm ± 0.05
(0.063”)
3.0mm MIN
10.0mm MIN
(0.400”)
Substrate area
85.6mm ± 0.20
(3.370”)
1.0mm ± 0.05
(0.039”)
10.0mm MIN
(0.400”)
November 2000 Rev. 3 - ECO #13392
54.0mm ± 0.10
(2.126”)
3.3mm ± T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
3
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
Card Signal Description
Symbol
A0 - A25
Type
INPUT
DQ0 - DQ15
INPUT/OUTPUT
CE1#, CE2#
INPUT
OE#
INPUT
WE#
INPUT
RDY/BSY #
OUTPUT
CD1#, CD2#
OUTPUT
WP
OUTPUT
VPP1, VPP2
VCC
GND
REG #
N.C.
INPUT
RST
INPUT
WAIT #
OUTPUT
BVD1, BVD2
OUTPUT
VS1, VS2
OUTPUT
RFU
N.C.
Name and Function
ADDRESS INPUTS: A0 through A25 enable direct addressing of up
to 64MB of memory on the card. Signal A0 is not used in word access
mode. A25 is the most significant bit
DATA INPUT/OUTPUT: DQ0 THROUGH DQ15 constitute the
bi-directional databus. DQ15 is the MSB.
CARD ENABLE 1 AND 2: CE1# enables even byte accesses, CE2#
enables odd byte accesses. Multiplexing A0, CE1# and CE2# allows 8bit hosts to access all data on DQ0 - DQ7 (see truth table).
OUTPUT ENABLE: Active low signal gating read data from the
memory card.
WRITE ENABLE: Active low signal gating write data to the memory
card.
READY/BUSY OUTPUT: Indicates status of internally timed erase
or program algorithms. A high output indicates that the card is ready to
accept accesses. A low output indicates that one or more devices in the
memory card are busy with internally timed erase or write activities.
CARD DETECT 1 and 2: Provide card insertion detection. These
signals are internally connected to ground on the card. The host shall
monitor these signals to detect card insertion. Pulled up on host side.
WRITE PROTECT: Write protect reflects the status of the Write
Protect switch on the memory card. WP set to high = write protected,
providing internal hardware write lockout to the Flash array.
If card does not include optional write protect switch, this signal will be
pulled low internally indicating write protect = "off".
PROGRAMMING VOLTAGES: Not connected
CARD POW ER SUPPLY: Universal 3V to 5V Supply
CARD GROUND
ATTRIBUTE MEMORY SELECT: Active low signal, enables
access to attribute memory space, occupied by the Card Information
Structure (CIS) and Card Registers.
RESET: Active high signal for placing card in Power-on default state.
Reset can be used as a Power-Down control for the memory array.
WAIT: This signal is pulled high internally for compatibility. No wait
states are generated.
BATTERY VOLTAGE DETECT: These signals are pulled high to
maintain SRAM card compatibility.
VOLTAGE SENSE: Notifies the host socket of the card's VCC
requirements. VS1 grounded and VS2 is open to indicate a 3/5V card.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD: pin may be driven
or left floating.
Functional Truth Table
READ function
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
/CE2 /CE1
H
H
H
L
H
L
L
L
L
H
A0
X
L
H
X
X
/OE
X
L
L
L
L
/WE
X
H
H
H
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
Common Memory
Attribute Memory
/REG D15-D8
D7-D0
X
High-Z
High-Z
H
High-Z Even-Byte
H
High-Z
Odd-Byte
H
Odd-Byte Even-Byte
H
Odd-Byte
High-Z
/REG D15-D8
D7-D0
X
High-Z
High-Z
L
High-Z Even-Byte
L
High-Z Not Valid
L Not Valid Even-Byte
L Not Valid
High-Z
WRITE function
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
H
H
H
L
L
November 2000 Rev. 3 - ECO #13392
H
L
L
L
H
X
H
H
H
H
4
X
X
X
Even-Byte
X
Odd-Byte
Odd-Byte Even-Byte
Odd-Byte
X
X
L
L
L
L
X
X
X
X
X
X
Even-Byte
X
Even-Byte
X
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
Card Interface
The FLF10 series flash card complies with PC Card standard (PCMCIA, March 1997). While maintaining
PCMCIA compatibility, the FLF10 series card has integrated special features to extend functionality.
The card has built-in 2 control registers:
- Configuration Option Register (COR)
Address = 4000h
- Configuration and Status Register (CSR)
Address = 4002h
COR register: provides a soft reset function (bit D7) and additional page bits (bits D0 and D1) to extend
card capacity beyond 64MB.
SReset
As defined by PCMCIA, setting the SReset bit to 1, places the card in the reset state. During this state
all memory devices are placed in power down mode, minimizing power consumption. Returning this bit
to 0 leaves the reset cycle and places the card in the same condition as following a power up or hardware
reset. This bit must be cleared to 0, to access any device on the card.
Complete soft reset cycle must consist of a 2 step write sequence to the SReset bit:
1. Initialization: write 1 to SReset
- reset cycle begin
- memory devices enters Power-Down mode aborting all operations and clearing all registers.
2. Write 0 to SReset
- Reset cycle ends
- memory devices and registers enter power on default state
The card can also be placed in Power Down mode by activating the Reset signal (pin58) or by
controlling the bit D2 (PwrDwn) in the CSR register.
LevlRequest
Not supported
Configuration Index
Configuration Index bits (D0 - D5) are defined to provide address extension bits -page address, to extend
card capacity beyond 64MB.
Only bits D0 and D1 are supported:
- D1D0 set to 00bin (0H) selects
page 0
- D1D0 set to 01bin (1H) selects:
page 1
- D1D0 set to10bin (2H) selects: page 2
- D1D0 set to11bin (3H) selects: page 3 (No Memory Access)
D1D0 is set to the value of 00bin (0H) during any reset cycle (Power on Reset, Hardware
Reset, and SReset). Attempting to access page 3 will not result in the writing or reading of
data.
CSR register: provides a power control of the memory array. Only bit D2 is supported; all other bits are
“don’t care”
PwrDwn
Writing 1 to PwrDwn bit (D2) forces each memory device on the card into a reset/power down mode by
asserting all the devices RP# pins. Writing 0 to the bit returns the array to stand by mode.
November 2000 Rev. 3 - ECO #13392
5
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
The Card Information Structure (CIS) contains information about Register addressing and Memory
structure.
Cards with memory capacity up to 64MB do not support Configuration Index bits.
Notes:
1. Reading from undefined address location or unsupported bits will return random data.
2. Writing to undefined address location may result in card malfunctioning due to limited
address decoding.
3. See block diagram for more details about control registers.
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing
of the status register, and, when VPEN = VPENH, block erasure, program, and lock-bit configuration.
The Block Erase command requires appropriate command data and an address within the block to be erased.
The Byte/Word Program command requires the command and address of the location to be written. Set Block
Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits
command requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE#
is active. The address and data needed to execute a command are latched on the rising edge of WE# or the
first edge of CE0, CE1, or CE2 that disables the device. Standard microprocessor write timings are used.
For information regarding modes of operation, commands, and
programming details for the memory components, please consult the
Intel 28F128J3A data sheet.
November 2000 Rev. 3 - ECO #13392
6
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
Absolute Maximum Ratings (2)
Operating Temperature TA (ambient)
Commercial
Storage Temperature
Voltage on any pin relative to VSS
VCC supply Voltage relative to VSS
Note:
Stress greater than those listed under
“Absolute Maximum ratings” may cause
permanent damage to the device. This is a
stress rating only and functional operation at
these or any other conditions greater than
those indicated in the operational sections of
this specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
0°C to +60 °C
-10°C to +70 °C
-0.5V to VCC+0.5V
-0.5V to +7.0V
Recommended Supply Voltage
VCC
Tolerance
3.3V
± 0.3V
5.0V
± 0.5V
Note: The FLF10 Series Card will
function at either 3.3V or 5.0V
DC Characteristics (1)
Symbol
Parameter
ICCR
VCC Read Current
ICCW
VCC Program
Current
VCC Erase Current
ICCE
ICCD
VCC Power-down
Current
ICCS
(CMOS)
VCC Standby
Current
Density
(Mbytes)
32,64,96,128,
160,192
32,64,96,128,
160, 192
32,64,96,128,
160,192
32
64
96
128
160
192
32
64
96
128
160
192
Notes Typ(3)
2
2
Max
Units
Test Conditions
70
110
mA
70
120
mA
VCC = VCCmax
tcycle = 200ns
2 memory devices
70
140
mA
2 memory devices
100
200
300
400
500
600
0.1
0.2
0.3
0.4
0.5
0.6
200 µA
400
600
800
1000
1200
0.2
mA
0.4
0.6
0.8
1.0
1.2
VCC = VCCmax
Control Signals = VCC
Reset = VCC (active)
VCC = VCCmax
Control Signals = VCC
Reset = 0V (not active)
CMOS Test Conditions: VCC = 5V ± 5%, VIL = VSS ± 0.2V, VIH = VCC ± 0.2V
Notes:
1. All currents are RMS values unless otherwise specified. ICCR, ICCW and ICCE are based on Word wide
operations (2 memory devices activated).
2. Control Signals: CE1#, CE2#, OE#, WE#.
3. Typical: VCC = 5V or VCC = 3V, T = +25°C.
November 2000 Rev. 3 - ECO #13392
7
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
VCC = 3.3V or 5V
Symbol
Parameter
Notes
ILI
Input Leakage Current
ILO
Min
Max
Units
Test Conditions
1, 2
±20
µA
Output Leakage Current
1
±20
µA
VCC = VCCMAX
Vin =VCC or GND
VCC = VCCMAX
Vin =VCC or GND
VIL
Input Low Voltage
1
0.8
V
VIH
Input High Voltage
1
VOL
Output Low Voltage
1
VOH
Output High Voltage
1
VCC-0.4
VLKO
VCC Erase/Program
Lock Voltage
1
2.0
0
0.7xVCC VCC+0.5
V
0.4
V
IOL = 3.2mA
VCC
V
IOH = -2.0mA
V
Notes:
1. Values are the same for byte and word wide modes for all card densities.
2. Exception: Leakage current on control signals with internal pull up resistors (see block diag) will be < 500µA
when VIN=GND.
November 2000 Rev. 3 - ECO #13392
8
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
AC Characteristics
Read Timing Parameters
VCC = 3.3V or 5V
200ns
Parameter
Min
250ns
SYMBOL
(PCMCIA)
tC(R)
Max
Read Cycle Time
ta(A)
Address Access Time
200
250
ns
ta(CE)
Card Enable Access Time
200
250
ns
ta(OE)
Output Enable Access Time
90
100
ns
tsu(A)
Address Setup Time
20
30
ns
tsu(CE)
Card Enable Setup Time
0
0
ns
th(A)
Address Hold Time
20
20
ns
th(CE)
Card Enable Hold Time
20
20
ns
tv(A)
0
0
ns
tdis(CE)
Output Hold from Address
Change
Output Disable Time from CE#
90
100
ns
tdis(OE)
Output Disable Time from OE#
90
100
ns
ten(CE)
Output Enable Time from CE#
5
5
ns
ten(OE)
Output Enable Time from OE#
5
5
ns
trec(RST)
Power Down recovery to Output
Delay. VCC = 5V
200
Min
Max
Unit
250
500
ns
500
ns
Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications.
Read Timing Diagram
tc(R )
th(A )
ta(A )
A [25 ::0], /R E G
tv(A )
ta(C E )
/C E 1, /C E 2
tsu(C E )
NOTE 1
NOTE 1
tsu (A )
ta(O E )
th(C E )
tdis(C E )
/O E
tdis(O E )
ten(O E )
D [15::0]
November 2000 Rev. 3 - ECO #13392
D A TA V A LID
9
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
Write Timing Parameters
VCC = 3.3V or 5V
200ns
Parameter
Min
250ns
SYMBOL
(PCMCIA)
tCW
Max
Min
Max
Unit
Write Cycle Time
200
250
ns
tw(WE)
Write Pulse Width
120
150
ns
tsu(A)
Address Setup Time
20
30
ns
tsu(A-WEH)
Address Setup Time for WE#
140
180
ns
tsu(CE-WEH)
Card Enable Setup Time for WE#
140
180
ns
tsu(D-WEH)
Data Setup Time for WE#
60
80
ns
th(D)
Data Hold Time
30
30
ns
trec(WE)
Write Recover Time/Address hold
30
30
ns
tdis(WE)
Output Disable Time from WE#
90
100
ns
tdis(OE)
Output Disable Time from OE#
90
100
ns
ten(WE)
Output Enable Time from WE#
5
5
ns
ten(OE)
Output Enable Time from OE#
5
5
ns
tsu(OE-WE)
Output Enable Setup from WE#
10
10
ns
th(OE-WE)
Output Enable Hold from WE#
50
50
ns
tsu(CE)
Card Enable Setup Time from OE#
0
0
ns
th(CE)
Card Enable Hold Time
20
20
ns
trec(WEL)
Reset recovery to WE going low
1
1
µs
Note: AC timing diagrams and characteristics are guaranteed to meet or exceed PCMCIA 2.1 specifications.
Write Timing Diagram
tc(W)
A[25::0], /REG
tsu(A-WEH)
trec(WE)
tsu(CE-WEH)
th(CE)
tsu(CE)
/CE1, /CE2
NOTE 1
NOTE 1
/OE
th(OE-WE)
tw(WE)
tsu(A)
/WE
th(D)
tsu(OE-WE)
D[15::0](Din)
tsu(D-WEH)
NOTE 2
DATA INPUT
tdis(WE)
tdis(OE)
ten(OE)
ten(WE)
D[15::0](
Dout)
NOTE 2
November 2000 Rev. 3 - ECO #13392
10
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
Data Write and Erase Performance (1,3)
VCC = 5V ± 5%, TA = 0C to + 70C
SYM
Parameter
tWHQV1
Word/Byte Program time
tWHQV3
Byte Program Time (using
Byte program command)
Block Program Time (using
write to buffer command)
Block Erase Time
tWHQV4
tWHRH
Notes Min
2,4
Typ(1) Max
Units Test Conditions
6.3
µs
180
µs
2
0.8
sec
2
0.7
sec
Erase Suspend Latency
Time to Read
26
35
Effective time per Byte
(using Write Buffer)
Word Program Mode
µs
Notes:
1. Typical: Nominal voltages and TA = 25C.
2. Excludes system overhead.
3. Valid for all speed options.
4. To maximize system performance RDY/BSY# signal should be polled.
Waveforms for Reset Operation
Write Operation
WE#
Read Operation
Valid Output
trec(RST)
tWHQV
tWHRH
trec(WEL)
RST
tWHRL
P2
tw(RST)
RDY/BSY
SYMBOL
tw(RST)
P2
trec(RST)
Parameter
Min
Reset pulse High time
trec(WEL)
Reset Recovery to WE going Low
tWHRL
WE High to Rdy/Bsy going low
11
Unit
µs
35
RST Low to reset during
Erase/Program/Lock-bit
Reset Low to output delay
November 2000 Rev. 3 - ECO #13392
Max
100
ns
500
ns
µs
1
100
ns
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
CIS DATA FOR FLF10 32MB & 64 MB CARDS BASED ON INTEL 28F128J3A
Address
00H
Value
Description
c Address
Value
Description
TPL_LINK(05H)
01H
05H
03H
CISTPL_DEVICE
TPL_LINK
48H
02H
4AH
F6H
EDI
TPLMID_MANF: LSB
04H
51H
FLASH = 250ns (device writable)
4CH
01H
7EH
CARD SIZE: 32MB
4EH
00H
EDI
LSB:
TPLMID_MANF: MSB
06H
FEH
64MB
50H
00H
MSB:
08H
FFH
END OF DEVICE
52H
FFH
END OF TUPLE
0AH
1CH
CISTPL_DEVICE_OC
54H
1AH
CISTPL_CONF
0CH
04H
TPL_LINK
56H
06H
TPL_LINK
Number Not Assigned
Number Not Assigned
0EH
02H
3 VOLT OPERATION
58H
01H
TPCC_SZ
10H
51H
FLASH = 250ns (device writable)
5AH
00H
TPCC_LAST
12H
7EH
CARD SIZE:32MB
5CH
00H
TPCC_RADR
FEH
64MB
5EH
40H
TPCC_RADR
14H
16H
FFH
18H
END OF DEVICE
CISTPL_JEDEC_C
60H
62H
00H
FFH
TPCC_RMSK
END OF TUPLE
18H
1AH
03H
89H
TPL_LINK
Manufacturer ID -INTEL
64H
66H
1BH
03H
CISTPL_CFTABLE_ENTRY
TPL_LINK
1CH
18H
Device ID - 28F0128J3A
68H
00H
TPCE_INDEX
1EH
FFH
END OF DEVICE
6AH
00H
TPCE_FS (no selection)
20H
17H
CISTPL_DEVICE_A
6CH
FFH
END OF TUPLE
22H
03H
TPL_LINK
6EH
15H
CISTPL_VERS1
24H
42H
EEPROM - 200ns
70H
7FH
TPL_LINK
26H
01H
Device Size = 2KBytes
72H
04H
TPLLV1_MAJOR
28H
FFH
END OF TUPLE
74H
01H
TPLLV1_MINOR
2AH
1DH
CISTPL_DEVICE_OA
76H
37H
7
2CH
03H
TPL_LINK
78H
50H
P
2EH
02H
3 VOLT OPERATION
7AH
30H
0
30H
11H
ROM - 250ns
7CH
33H
3
32H
34H
FFH
1EH
7EH
80H
32H
46H
2
F
36H
07H
END OF DEVICE
CISTPL_DEVICEGEO
TPL_LINK
82H
4CH
L
38H
02H
DGTPL_BUS
84H
46H
F
3AH
12H
DGTPL_EBS
86H
31H
1
01H
DGTPL_RBS
88H
32H
2
3CH
3EH
01H
DGTPL_WBS
8AH
2DH
-
40H
01H
DGTPL_PART
8CH
2DH
-
42H
01H
FLASH DEVICE
8EH
2DH
-
NON-INTERLEAVED
90H
32H
2
44H
FFH
END OF TUPLE
92H
35H
5
46H
20H
CISTPL_MANFID
94H
20H
SPACE
November 2000 Rev. 3 - ECO #13392
12
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
CIS DATA FOR FLF10 32MB & 64 MB CARDS BASED ON INTEL 28F128J3A (CONT.)
Address
96H
98H
9AH
9CH
9EH
Value
Address
EAH
Value
Description
00H
43H
4FH
50H
59H
Description
END TEXT
C
O
P
Y
41H
A
ECH
54H
T
A0H
52H
R
A2H
49H
I
A4H
47H
G
A6H
48H
A8H
EEH
49H
I
F0H
4FH
O
F2H
4EH
N
F4H
20H
SPACE
F6H
00H
END TEXT
F8H
31H
1
H
FAH
39H
9
54H
T
FCH
39H
9
AAH
20H
SPACE
FEH
39H
9
ACH
57H
W
100H
00H
END TEXT
AEH
48H
H
102H
00H
NULL
B0H
49H
I
104H
FFH
END OF LIST
B2H
B4H
54H
45H
T
E
B6H
20H
SPACE
B8H
45H
E
BAH
4CH
L
BCH
45H
E
BEH
43H
C
C0H
54H
T
C2H
52H
R
C4H
4FH
O
C6H
4EH
N
C8H
49H
I
CAH
43H
C
CCH
20H
SPACE
CEH
44H
D
D0H
45H
E
D2H
53H
S
D4H
49H
I
D6H
47H
G
D8H
4EH
N
DAH
53H
S
DCH
20H
SPACE
DEH
43H
C
E0H
4FH
O
E2H
52H
R
E4H
50H
P
E6H
4FH
O
E8H
52H
R
November 2000 Rev. 3 - ECO #13392
13
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
CIS DATA FOR FLF10 96MB - 192MB CARDS BASED ON INTEL 28F128J3A
Address
Value
Description
Address
Value
Description
00H
01H
02H
03H
CISTPL_DEVICE
48H
02H
DGTPL_BUS
TPL_LINK
4AH
12H
DGTPL_EBS
04H
51H
FLASH = 250ns (device writable)
4CH
01H
DGTPL_RBS
06H
FEH
CARD SIZE: 64MB (1 page)
4EH
01H
DGTPL_WBS
st
08H
FFH
END OF DEVICE
50H
01H
DGTPL_PART
0AH
1CH
CISTPL_DEVICE_OC
52H
01H
FLASH DEVICE
FFH
END OF TUPLE
CISTPL_MANFID
0CH
04H
TPL_LINK
0EH
02H
3 VOLT OPERATION
54H
10H
51H
FLASH = 250ns (device writable)
56H
20H
12H
7EH
CARD SIZE:64MB (1 page)
58H
05H
14H
FFH
END OF DEVICE
5AH
F6H
EDI
TPLMID_MANF: LSB
16H
09H
CISTPL_EXTDEVICE
5CH
01H
EDI
TPLMID_MANF: MSB
18H
1AH
06H
0CH
TPL_LINK
Mem Paging Info:2bit/COR/64MB
5EH
60H
00H
00H
LSB:
MSB:
Number Not Assigned
Number Not Assigned
1CH
1EH
51H
07H
62H
64H
FFH
1AH
END OF TUPLE
CISTPL_CONF
20H
01H
1x64MB (for 96MB and 128MB)
66H
06H
TPL_LINK
02H
2x64MB (for 160MB and 192MB)
NON-INTERLEAVED
st
Flash = 250 ns
Device Size Extender
TPL_LINK(05H)
68H
01H
TPCC_SZ
6AH
00H
TPCC_LAST
7DH
+32MB (for 96MB and 160MB)
6CH
00H
TPCC_RADR
FEH
+64MB (for 128MB and 192 MB)
6EH
40H
TPCC_RADR
24H
FFH
END OF TUPLE
70H
03H
TPCC_RMSK
26H
18H
CISTPL_JEDEC_C
72H
FFH
END OF TUPLE
28H
03H
TPL_LINK
74H
15H
CISTPL_VERS1
2AH
89H
Manufacturer ID - INTEL
76H
7FH
TPL_LINK
2CH
18H
Device ID - 28F0128J3A
78H
04H
TPLLV1_MAJOR
2EH
FFH
END OF DEVICE
7AH
01H
TPLLV1_MINOR
30H
32H
17H
03H
CISTPL_DEVICE_A
TPL_LINK
7CH
7EH
37H
50H
7
P
34H
42H
EEPROM - 200ns
80H
30H
0
36H
01H
Device Size = 2Kbytes
82H
39H
9
38H
FFH
END OF TUPLE
84H
36H
6
22H
3AH
1DH
CISTPL_DEVICE_OA
86H
46H
F
3CH
03H
TPL_LINK
88H
4CH
L
3EH
02H
3 VOLT OPERATION
8AH
46H
F
40H
11H
ROM - 250ns
8CH
31H
1
42H
FFH
END OF DEVICE
8EH
32H
2
44H
1EH
CISTPL_DEVICEGEO
90H
2DH
-
46H
07H
TPL_LINK
92H
2DH
-
November 2000 Rev. 3 - ECO #13392
14
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
CIS DATA FOR FLF10 96MB - 192MB CARDS BASED ON INTEL 28F128J3A (CONT.)
Address
94H
96H
98H
9AH
9CH
Value
Description
2DH
32H
35H
20H
00H
2
5
SPACE
END TEXT
9EH
43H
A0H
Address
E8H
Value
Description
52H
R
EAH
50H
P
ECH
4FH
O
EEH
52H
R
F0H
41H
A
C
F2H
54H
T
4FH
O
F4H
49H
I
A2H
50H
P
F6H
4FH
O
A4H
59H
Y
F8H
4EH
N
A6H
52H
R
FAH
20H
SPACE
A8H
49H
I
FCH
00H
END TEXT
FEH
AAH
47H
G
ACH
48H
H
AEH
54H
T
B0H
B2H
20H
57H
SPACE
W
B4H
48H
H
B6H
49H
I
B8H
54H
T
BAH
45H
E
BCH
20H
SPACE
BEH
45H
E
C0H
4CH
L
C2H
45H
E
C4H
43H
C
C6H
54H
T
C8H
52H
R
CAH
4FH
O
CCH
4EH
N
CEH
49H
I
D0H
43H
C
D2H
20H
SPACE
D4H
44H
D
D6H
45H
E
D8H
53H
S
DAH
49H
I
DCH
47H
G
DEH
4EH
N
E0H
53H
S
E2H
20H
SPACE
E4H
43H
C
E6H
4FH
O
November 2000 Rev. 3 - ECO #13392
15
31H
1
100H
39H
9
102H
39H
9
104H
39H
9
106H
00H
END TEXT
108H
00H
NULL
10AH
FFH
END OF LIST
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
PRODUCT MARKING
WED 7P032FLF1200C15 C995 9915
EDI
Date code
Lot code / trace number
Part number
Company Name
Note:
Some products are currently marked with our pre-merger company name/acronym (EDI). During our
transition period, some products will also be marked with our new company name/acronym (WED).
Starting October 2000 all PCMCIA products will be marked only with the WED prefix.
PART NUMBERING
7 P 032 FLF12 00 C 15
Card access time
15
25
150ns
250ns
Temperature range
C Commercial 0°C to +70°C
I Industrial
-40°C to +85°C
Packaging option
00
Standard, type 1
Card family and version
- See Card Family and Version Info. for details (next page)
Card capacity
032
32MB
PC card
P
R
Standard PCMCIA
Ruggedized PCMCIA
Card technology
7
8
November 2000 Rev. 3 - ECO #13392
FLASH
SRAM
16
PC Card Products
PCMCIA Flash Memory Card
FLF10 Series
Ordering Information
7P XXX FLF YY SS T ZZ
where
XXX:
032
064
096
128
160
192
32MB
64MB
96MB
128MB
160MB
192MB
12
14
based on 28F128J3A
With Attribute Memory
based on 28F128J3A
With Attribute Memory and
Write Protect Switch (optional)
SS:
00
01
02
WEDC Logo
Blank Housing Type 1
Blank Housing T 1 (Recessed)
T:
C
Commercial
ZZ:
20
25
200ns
250ns
YY:
Date of Revision
22-Jul-99
31-May-00
01-Aug-00
06-Nov-00
REVISION HISTORY
Version
Description
-000
Initial Release
-001
Add Pg. 16
-002
Corrected Timing Errors, Pgs. 9 & 10
-003
Corrected CIS Errors, Pg. 14, and Added Memory
Chip Information, Pg. 6
White Electronic Designs Corporation
One Research Drive, Westborough, MA 01581, USA
tel:
(508) 366 5151
fax:
(508) 836 4850
www.whiteedc.com
November 2000 Rev. 3 - ECO #13392
17
PC Card Products