DATASHEET ICS91305I HIGH PERFORMANCE COMMUNICATION BUFFER Description Features The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. • • • • Zero input - output delay ICS91305I is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. • • • • Less than 200 ps Jitter between outputs The ICS91305I comes in an eight pin 150 mil SOIC package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. • 3.3V ±10% operation • Supports industrial temperature range -40°C to 85°C Frequency range 10 - 133 MHz (3.3V) 5V tolerant input REF High loop filter bandwidth ideal for Spread Spectrum applications Skew controlled outputs Skew less than 250 ps between outputs Available in 8 pin 150 mil SOIC & 173 mil TSSOP packages Block Diagram IDT® HIGH PERFORMANCE COMMUNICATION BUFFER 1 ICS91305I REV G 090612 ICS91305I HIGH PERFORMANCE COMMUNICATION BUFFER Pin Configuration Pin Descriptions IDT® HIGH PERFORMANCE COMMUNICATION BUFFER 2 ICS91305I REV G 090612 ICS91305I HIGH PERFORMANCE COMMUNICATION BUFFER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS91305I. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Electrical Characteristics at 3.3V DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 0.8 V Input Low Voltage VIL Input High Voltage VIH Input Low Current IIL VIN=0V 19 100.0 µA Input High Current IIH VIN=VDD 0.10 250.0 µA IOL = 12mA 0.25 0.4 V 2.0 V Output Low Voltage1 VOL Output High Voltage1 VOH IOH = -12mA Power Down Supply Current IDD REF = 0 MHz 0.3 100.0 µA Supply Current IDD Unloaded oututs at 66.66 MHz SEL inputs at VDD or GND 30.0 80.0 mA 2.4 2.9 V Notes: 1.Guaranteed by design and characterization. Not subject to 100% test. 2.All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V. 3.Duty cycle measured at 1.4V. 4.Skew measured at 1.4V on rising edges. Loading must be equal on outputs. IDT® HIGH PERFORMANCE COMMUNICATION BUFFER 3 ICS91305I REV G 090612 ICS91305I HIGH PERFORMANCE COMMUNICATION BUFFER Switching Characteristics PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Output period t1 With CL=30pF 100.00 (10) 7.5 (133) ns (MHz) Input period t1 With CL=30pF 100.00 (10) 7.5 (133) ns (MHz) Duty Cycle1 Dt1 Measured at 1.4V; CL=30pF Duty Cycle1 Dt2 Measured at VDD/2 Fout <66.6MHz Rise Time1 tr1 Fall Time1 40.0 50 60 % 45 50 55 % Measured between 0.8V and 2.0V: CL=30pF 1.2 1.5 ns tf1 Measured between 2.0V and 0.8V; CL=30pF 1.2 1.5 ns Delay, REF Rising Edge to CLKOUT Rising Edge1, 2 Dr1 Measured at 1.4V 0 ±350 ps Output to Output Skew1 Tskew All outputs equally loaded, CL=20pF 250 ps Device to Device Skew1 Tdsk-Tdsk Measured at VDD/2 on the CLKOUT pins of devices 700 ps Cycle to Cycle Jitter1 Tcyc-Tcyc Measured at 66.66 MHz, loaded outputs 200 ps PLL Lock Time1 tLOCK Stable power supply, valid clock presented on REF pin 1.0 ms Jitter; Absolute Jitter1 Tjabs @ 10,000 cycles CL = 30pF 70 200 ps Jitter; 1 - Sigma1 Tj1s @ 10,000 cycles CL = 30pF 14 60 ps 0 -200 Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. REF input has a threshold voltage of 1.4V 3. All parameters expected with loaded outputs IDT® HIGH PERFORMANCE COMMUNICATION BUFFER 4 ICS91305I REV G 090612 ICS91305I HIGH PERFORMANCE COMMUNICATION BUFFER Output to Output Skew The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT. Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. Timing diagrams with different loading configurations IDT® HIGH PERFORMANCE COMMUNICATION BUFFER 5 ICS91305I REV G 090612 ICS91305I HIGH PERFORMANCE COMMUNICATION BUFFER Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 8 Symbol E Min A A1 B C D E e H h L α H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce B SEATING PLANE L .10 (.004) IDT® HIGH PERFORMANCE COMMUNICATION BUFFER C 6 ICS91305I REV G 090612 ICS91305I HIGH PERFORMANCE COMMUNICATION BUFFER Package Outline and Package Dimensions (8-pin TSSOP, 4.4 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 8 Millimeters Symbol E1 E IN D EX AR EA 1 2 D A 2 Min A A1 A2 b C D E E1 e L α aaa Inches Max Min -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 2.90 3.10 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° 0.10 Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.114 0.122 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° 0.004 A A 1 c -C e b S E A TIN G P LA N E L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package 91305AMILF 91305AMILFT 91305AGILF 91305AGILFT 305AMILF 305AMILF 305IL 305IL Tubes Tape and Reel Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin TSSOP 8-pin TSSOP Temperature -40 to +85° -40 to +85° -40 to +85° -40 to +85° C C C C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT® HIGH PERFORMANCE COMMUNICATION BUFFER 7 ICS91305I REV G 090612 ICS91305I HIGH PERFORMANCE COMMUNICATION BUFFER Revision History Rev. Originator Date G D. Chan 09/06/12 Description of Change 1. Updated ordering information to inlclude “I” for industrial temp range in ordering scheme. 2. Re-created datasheet in latest template. IDT® HIGH PERFORMANCE COMMUNICATION BUFFER 8 ICS91305I REV G 090612 ICS91305I HIGH PERFORMANCE COMMUNICATION BUFFER SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp [email protected] Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA