NSC 9308

9308/DM9308 Dual 4-Bit Latch
General Description
The 9308 is a dual 4-bit D-type latch designed for general
purpose storage applications in digital systems. Each latch
contains both an active LOW Master Reset input an active
LOW Enable inputs. The 74116 is a pin for pin equivalent of
the 9308.
Connection Diagram
Logic Symbol
Dual-In-Line Package
TL/F/10208 – 2
VCC e Pin 24
GND e Pin 12
TL/F/10208 – 1
Order Number 9308DMQB, 9308FMQB or DM9308N
See NS Package Number J24A, N24A or W24C
Pin Names
C1995 National Semiconductor Corporation
TL/F/10208
Description
(
Parallel Latch Inputs
(
Parallel Latch Outputs
D0a – D3a
D0b – D3b
E0a, E1a, E0b, E1b
MRa, MRb
Q0a – Q3a
Q0b – Q3b
AND Enable Inputs (Active LOW)
Master Reset Inputs (Active LOW)
RRD-B30M105/Printed in U. S. A.
9308/DM9308 Dual 4-Bit Latch
June 1989
Absolute Maximum Ratings (Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
b 55§ C to a 125§ C
MIL
COM
0§ C to a 70§ C
Storage Temperature Range
b 65§ C to a 150§ C
Recommended Operating Conditions
Symbol
Military
Parameter
Commercial
Units
Min
Nom
Max
Min
Nom
Max
5
5.5
4.75
5
5.25
VCC
Supply Voltage
4.5
VIH
High Level Input
Voltage
2
VIL
Low Level Input
Voltage
IOH
2
V
V
0.8
0.8
V
High Level Output
Current
b 0.8
b 0.8
mA
IOL
Low Level Output
Current
16
16
mA
TA
Free Air Operating
Temperature
70
§C
ts (H)
Setup Time HIGH, Dn to En
6
10
th (H)
Hold Time HIGH, Dn to En
4
b 2.0
ns
ts (L)
Setup Time LOW, Dn to En
10
12
ns
th (L)
Hold Time LOW, Dn to En
4
8
ns
tw (L)
En Pulse Width LOW
18
18
ns
tw (L)
MR Pulse Width LOW
18
18
ns
trec
Recovery Time, MR to En
10
8
ns
b 55
125
0
ns
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC e Min, II e b18 mA
VOH
High Level Output
Voltage
VCC e Min, IOH e Max,
VIL e Max, VIH e Min
VOL
Low Level Output
Voltage
VCC e Min, IOL e Max
VIH e Min, VIL e Max
II
Input Current @ Max
Input Voltage
IIH
Min
Typ
(Note 1)
Max
Units
b 1.5
V
2.4
V
0.4
V
VCC e Max, VI e 5.5V
1
mA
High Level Input
Current
VCC e Max, VI e 2.4V
40
mA
IIL
Low Level Input
Current
VCC e Max, VI e 0.4V
b 1.6
mA
IOS
Short Circuit
Output Current
VCC e Max
(Note 2)
Supply Current
VCC e Max (Note 3)
ICC
MIL
b 20
b 70
COM
b 20
b 57
100
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all outputs open and all inputs grounded.
2
mA
mA
Functional Description
Truth Table
Data can be entered into the latch when both of the enable
inputs are LOW. As long as this logic condition exists, the
output of the latch will follow the input. If either of the enable
inputs goes HIGH, the data present in the latch at that time
is held in the latch and is no longer affected by data input.
The master reset overrides all other input conditions and
forces the outputs of all the latches LOW when a LOW signal is applied to the Master Reset input.
MR
E0
E1
D
Qn
Operation
H
H
H
L
L
L
L
L
H
L
H
X
L
H
Qnb1
Data Entry
Data Entry
Hold
H
H
L
H
H
X
L
H
X
X
X
X
Qnb1
Qnb1
L
Hold
Hold
Reset
Qnb1 e Previous Output State
Qn e Present Output State
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Logic Diagram
TL/F/10208 – 3
Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 5 for test waveforms and output load.)
9308
Symbol
CL e 15 pF
RL e 400X
Parameter
Min
Units
Max
tPLH
tPHL
Propagation Delay
En to Qn
30
22
ns
tPLH
tPHL
Propagation Delay
Dn to Qn
15
18
ns
tPHL
Propagation Delay
MR to Qn
22
ns
3
4
Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package (J)
Order Number 9308DMQB
NS Package Number J24A
24-Lead Molded Dual-In-Line Package (N)
Order Number DM9308N
NS Package Number N24A
5
9308/DM9308 Dual 4-Bit Latch
Physical Dimensions inches (millimeters) (Continued)
24-Lead Ceramic Flat Package (W)
Order Number 9308FMQB
NS Package Number W24C
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