STMICROELECTRONICS 93CS46

ST93CS46
ST93CS47
1K (64 x 16) SERIAL MICROWIRE EEPROM
NOT FOR NEW DESIGN
1 MILLION ERASE/WRITE CYCLES, with
40 YEARS DATA RETENTION
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE SUPPLY VOLTAGE
– 3V to 5.5V for the ST93CS46
– 2.5V to 5.5V for the ST93CS47
USER DEFINED WRITE PROTECTED AREA
PAGE WRITE MODE (4 WORDS)
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ST93CS46 and ST93CS47 are replaced by
the M93S46
8
8
1
1
PSDIP8 (B)
0.4mm Frame
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST93CS46 and ST93CS47 are 1K bit Electrically Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. The memory
is accessed through a serial input D and output Q.
The 1K bit memory is organized as 64 x 16 bit
words.The memory is accessed by a set of instructions which include Read, Write, Page Write, Write
All and instructions used to set the memory protection. A Read instruction loads the address of the
first word to be read into an internal address
pointer.
Table 1. Signal Names
S
Chip Select Input
D
Serial Data Input
Q
Serial Data Output
C
Serial Clock
PRE
Protect Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
June 1997
This is information on a product still in production bu t not recommended for new de signs.
VCC
D
C
S
Q
ST93CS46
ST93CS47
PRE
W
VSS
AI00884B
1/16
ST93CS46, ST93CS47
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
ST93CS46
ST93CS47
ST93CS46
ST93CS47
S
C
D
Q
1
2
3
4
8
7
6
5
VCC
PRE
W
VSS
S
C
D
Q
AI00885B
1
2
3
4
8
7
6
5
VCC
PRE
W
VSS
AI00886C
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature
–40 to 85
°C
TSTG
Storage Temperature
–65 to 150
°C
TLEAD
Lead Temperature, Soldering
215
260
°C
TA
(SO8 package)
(PSDIP8 package)
VIO
Input or Output Voltages (Q = VOH or Hi-Z)
VCC
Supply Voltage
VESD
Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)
(3)
(2)
40 sec
10 sec
–0.3 to VCC +0.5
V
–0.3 to 6.5
V
3000
V
500
V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
DESCRIPTION (cont’d)
The data is then clocked out serially. The address
pointer is automatically incremented after the data
is output and, if the Chip Select input (S) is held
High, the ST93CS46/47 can output a sequential
stream of data words. In this way, the memory can
be read as a data stream of 16 to 1024 bits, or
continuously as the address counter automatically
rolls over to 00 when the highest address is
reached. Within the time required by a programming cycle (tW), up to 4 words may be written with
the help of the Page Write instruction; the whole
memory may also be erased, or set to a predetermined pattern, by using the Write All instruction.
Within the memory, an user defined area may be
protected against further Write instructions. The
size of this area is defined by the content of a
2/16
Protect Register, located outside of the memory
array. As a final protection step, data may be permanently protected by programming a One Time
Programing bit (OTP bit) which locks the Protect
Register content.
Programming is internally self-timed (the external
clock signal on C input may be disconnected or left
running after the start of a Write cycle) and does
not require an erase cycle prior to the Write instruction. The Write instruction writes 16 bits at one time
into one of the 64 words, the Page Write instruction
writes up to 4 words of 16 bits to sequential locations, assuming in both cases that all addresses
are outside the Write Protected area.
After the start of the programming cycle, a
Ready/Busy signal is available on the Data output
(Q) when the Chip Select (S) input pin is driven
High.
ST93CS46, ST93CS47
Figure 3. AC Testing Input Output Waveforms
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
≤ 20ns (10% to 90%)
Input Pulse Voltages
0.4V to 2.4V
Input and Output Timing
Reference Voltages
0.8 and 2V
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Table 3. Capacitance (1)
(TA = 25 °C, f = 1 MHz )
Symbol
C IN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
5
pF
VOUT = 0V
5
pF
Note: 1. Sampled only, not 100% tested.
Table 4. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS46 and
VCC = 2.5V to 5.5V for ST93CS47)
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±2.5
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC,
Q in Hi-Z
±2.5
µA
ICC
Supply Current (TTL Inputs)
S = VIH, f = 1 MHz
3
mA
Supply Current (CMOS Inputs)
S = VIH, f = 1 MHz
2
mA
Supply Current (Standby)
S = VSS, C = VSS
50
µA
Input Low Voltage (ST93CS46,47)
4.5V ≤ VCC ≤ 5.5V
–0.1
0.8
V
Input Low Voltage (ST93CS46)
3V ≤ VCC ≤ 5.5V
–0.1
0.2 VCC
V
Input Low Voltage (ST93CS47)
2.5V ≤ VCC ≤ 5.5V
–0.1
0.2 VCC
V
Input High Voltage (ST93CS46,47)
4.5V ≤ VCC ≤ 5.5V
2
VCC + 1
V
Input High Voltage (ST93CS46)
3V ≤ VCC ≤ 5.5V
0.8 VCC
VCC + 1
V
Input High Voltage (ST93CS47)
2.5V ≤ VCC ≤ 5.5V
0.8 VCC
VCC + 1
V
IOL = 2.1mA
0.4
V
IOL = 10 µA
0.2
V
ICC1
VIL
VIH
VOL
VOH
Output Low Voltage
Output High Voltage
IOH = –400µA
2.4
V
IOH = –10µA
VCC – 0.2
V
3/16
ST93CS46, ST93CS47
Table 5. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS46 and
VCC = 2.5V to 5.5V for ST93CS47)
Symbol
Alt
Parameter
Test Condition
Min
tPRVCH
tPRES
Protect Enable Valid to Clock High
50
ns
tWVCH
tPES
Write Enable Valid to Clock High
50
ns
tSHCH
tCSS
Chip Select High to Clock High
50
ns
tDVCH
tDIS
Input Valid to Clock High
100
ns
tCHDX
tDIH
Clock High to Input Transition
100
ns
tCHQL
tPD0
Clock High to Output Low
500
ns
tCHQV
tPD1
Clock High to Output Valid
500
ns
tCLPRX
tPREH
Clock Low to Protect Enable Transition
tSLWX
tPEH
Chip Select Low to Write Enable Transition
tCLSL
tCSH
Clock Low to Chip Select Transition
tSLSH
tCS
Chip Select Low to Chip Select High
tSHQV
tSV
Chip Select High to Output Valid
500
ns
tSLQZ
tDF
Chip Select Low to Output Hi-Z
300
ns
tCHCL
tSKH
Clock High to Clock Low
Note 2
250
ns
tCLCH
tSKL
Clock Low to Clock High
Note 2
250
ns
tW
tWP
Erase/Write Cycle time
fC
fSK
Clock Frequency
Note 1
Max
0
ns
250
ns
0
ns
250
ns
0
10
ms
1
MHz
Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.
Figure 4. Synchronous Timing, Start and Op-Code Input
PRE
tPRVCH
W
tWVCH
tCHCL
C
tSHCH
tCLCH
S
tDVCH
D
START
tCHDX
OP CODE
OP CODE
OP CODE INPUT
START
AI00887
4/16
Unit
ST93CS46, ST93CS47
Figure 5. Synchronous Timing, Read or Write
C
tCLSL
S
tDVCH
tCHDX
tSLSH
A0
An
D
tCHQV
tSLQZ
tCHQL
Hi-Z
Q15/Q7
Q
ADDRESS INPUT
Q0
DATA OUTPUT
AI00820C
PRE
tCLPRX
W
tSLWX
C
tCLSL
S
tSLSH
tDVCH
D
tCHDX
An
A0/D0
tSHQV
tSLQZ
Hi-Z
BUSY
Q
READY
tW
ADDRESS/DATA INPUT
WRITE CYCLE
AI00888B
5/16
ST93CS46, ST93CS47
POWER-ON DATA PROTECTION
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit resets all internal programming
circuitry and sets the device in the Write Disable
mode. When VCC reaches its functional value, the
device is properlyreset (in the Write Disable mode)
and is ready to decode and execute an incoming
instruction. A stable VCC must be applied before
any logic signal.
INSTRUCTIONS
The ST93CS46/47 has eleven instructions, as
shown in Table 6. Each instruction is preceded by
the rising edge of the signal applied on the Chip
Select (S) input (assuming that the Clock C is low),
followed by a ’1’ read on D input during the rising
edge of the clock C. The op-codes of the instructions are made up of the 2 following bits. Some
instructions use only these first two bits, others use
also the first two bits of the address field to define
the op-code. The address field is six bits long
(A5-A0).
The ST93CS46/47 is fabricated in CMOS technology and is therefore able to run from zero Hz (static
input signals) up to the maximum ratings (specified
in Table 5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
is received, the instruction and address are decoded and the data from the memory is transferred
into an output shiftregister. A dummy ’0’ bit is output
first followed by the 16 bit word with the MSB first.
Table 6. Instruction Set
Instruction
Description
W
Pin (1)
PRE
Pin
Op
Code
READ
Read Data from Memory
X
’0’
10
A5-A0
Q15-Q0
WRITE
Write Data to Memory
’1’
’0’
01
A5-A0
D15-D0
Write is executed if
the address is not
inside the Protected
area
PAWRITE
Page Write to Memory
’1’
’0’
11
A5-A0
D15-D0
Write is executed if
all the addresses
are not inside the
Protected area
Write All Memory
’1’
’0’
00
01XXXX
D15-D0
Write all data if the
Protect Register is
cleared
WEN
Write Enable
’1’
’0’
00
11XXXX
WDS
Write Disable
X
’0’
00
00XXXX
PRREAD
Protect Register Read
X
’1’
10
XXXXXX
Q8-Q0
Data Output =
Protect Register
content + Protect
Flag bit
PRWRITE
Protect Register Write
’1’
’1’
01
A5-A0
Data above
specified address
A5-A0 are protected
PRCLEAR
Protect Register Clear
’1’
’1’
11
111111
Protect Flag is also
cleared (cleared
Flag = 1)
PREN
Protect Register Enable
’1’
’1’
00
11XXXX
PRDS
Protect Register Disable
’1’
’1’
00
000000
WRALL
Note: 1. X = don’t care bit.
6/16
Address
(1)
Data
Additional
Information
OTP bit is set
permanently
ST93CS46, ST93CS47
Output data changes are triggered by the Low to
High transition of the Clock (C). The ST93CS46/47
will automatically increment the address and will
clock out the next word as long as the Chip Select
input (S) is held High. In this case the dummy ’0’ bit
is NOT output between words and a continuous
stream of data can be read.
Write Enable and Write Disable
The Write Enable instruction (WEN) authorizes the
following Write instructions to be executed, the
Write Disable instruction (WDS) disables the execution of the following Erase/Write instructions.
When power is first applied, the ST93CS46/47
enters the Disable mode. When the Write Enable
instruction (WEN) is executed, Write instructions
remain enabled until a Write Disable instruction
(WDS) is executed or if the Power-on reset circuit
becomes active due to a reduced VCC. To protect
the memory contents from accidental corruption, it
is advisable to issue the WDS instruction after
every write cycle.
The READ instruction is not affected by the WEN
or WDS instructions.
Write
The Write instruction (WRITE) is followed by the
address and the word to be written. The Write
Enable signal (W) must be held high during the
WRITE instruction. Data input D is sampled on the
Low to High transition of the clock. After the last
data bit has been sampled, Chip Select (S) must
be brought Low before the next rising edge of the
clock (C), in order to start the self-timed programming cycle, providing that the address is NOT in the
protected area. If the ST93CS46/47 is still performing the programming cycle, the Busy signal (Q
= 0) will be returned if the Chip Select input (S) is
driven high, and the ST93CS46/47 will ignore any
data on the bus. When the write cycle is completed,
the Ready signal (Q = 1) will indicate (if S is driven
high) that the ST93CS46/47 is ready to receive a
new instruction.
Page Write
A Page Write instruction (PAWRITE) contains the
first address to be written followed by up to 4 data
words. The Write Enable signal (W) must be held
High duringthe Write instruction. Input address and
data are read on the Low to High transition of the
clock. After the receipt of each data word, bits
A1-A0 of the internal address register are incremented, the high order bits A5-A2 remaining unchanged. Users must take care by software to
ensure that the last word address has the same
four upper order address bits as the initial address
transmitted to avoid address roll-over.
After the LSB of the last data word, Chip Select (S)
must be brought Low before the next rising edge of
the Clock (C). The falling edge of Chip Select (S)
initiates the internal, self-timed write cycle. The
Page Write operation will not be performed if any
of the 4 words is addressing the protected area. If
the ST93CS46/47 is still performing the programming cycle, the Busy signal (Q = 0) will be returned
if the Chip Select input (S) is driven high, and the
ST93CS46/47 will ignore any data on the bus.
When the write cycle is completed, the Ready
signal (Q = 1) will indicate (if S is driven high) that
the ST93CS46/47is ready to receive a new instruction.
Write All
The Write All instruction (WRALL) is valid only after
the Protect Register has been cleared by executing
a PRCLEAR (Protect Register Clear) instruction.
The Write All instruction simultaneously writes the
whole memory with the same data word included
in the instruction. The Write Enable signal (W) must
be held High before and during the Write instruction. Input address and data are read on the Low
to High transition of the clock. If the ST93CS46/47
is still performing the programming cycle, the Busy
signal (Q = 0) will be returned if the Chip Select
input (S) is driven high, and the ST93CS46/47 will
ignore any data on the bus. When the write cycle
is completed, the Ready signal (Q = 1) will indicate
(if S is driven high) that the ST93CS46/47 is ready
to receive a new instruction.
MEMORY WRITE PROTECTION AND PROTECT
REGISTER
The ST93CS46/47 offers a Protect Register containing the bottom address of the memory area
which has to be protected against write instructions. In addition to this Protect Register, two flag
bits are used to indicate the Protect Register status:
the Protect Flag enabling/disabling the protection
of theProtect Register and the OTP bit which, when
set, disables access to the Protect Register and
thus prevents any further modifications of this Protect Register value. The content of the Protect
Register is defined when using the PRWRITE instruction, it may be read when using the PRREAD
instruction. A specific instruction PREN (Protect
Register Enable) allows the user to execute the
protect instructions PRCLEAR, PRWRITE and
PRDS; this PREN instruction being used together
with the signals applied on the input pins PRE
(Protect Register Enable pin) and W (Write Enable).
7/16
ST93CS46, ST93CS47
Figure 6. READ, WRITE, WEN, WDS Sequences
READ
PRE
S
D
1 1 0 An
A0
Q
Qn
ADDR
Q0
DATA OUT
OP
CODE
WRITE
PRE
W
S
CHECK
STATUS
D
1 0 1 An
A0 Dn
D0
Q
ADDR
BUSY
DATA IN
READY
OP
CODE
WRITE
ENABLE
PRE
WRITE
DISABLE
PRE
W
S
S
D
D
1 0 0 1 1 Xn X0
1 0 0 0 0 Xn X0
OP
CODE
OP
CODE
AI00889D
8/16
ST93CS46, ST93CS47
Figure 7. PAWRITE, WRALL Sequences
PAGE
WRITE
PRE
W
S
CHECK
STATUS
D
1 1 1 An
A0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
WRITE
ALL
PRE
W
S
CHECK
STATUS
D
1 0 0 0 1 Xn X0 Dn
D0
Q
ADDR
DATA IN
BUSY
READY
OP
CODE
AI00890C
9/16
ST93CS46, ST93CS47
MEMORY WRITE PROTECTION (cont’d)
Accessing the Protect Register is done by executing the following sequence:
– WEN: execute the Write Enable instruction,
– PREN: execute the PREN instruction,
– PRWRITE, PRCLEAR or PRDS: the protection
then may be defined, in terms of size of the
protected area (PRWRITE, PRCLEAR) and
may be set permanently (PRDS instruction).
Protect Register Read
The Protect Register Read instruction (PRREAD)
outputs on the Data Output Q the content of the
Protect Register, followed by the Protect Flag bit.
The Protect Register Enable pin (PRE) must be
driven High before and during the instruction. As in
the Read instruction a dummy ’0’ bit is output first.
Since it is not possible to distinguish if the Protect
Register is cleared (all 1’s) or if it is written with all
1’s, user must check the Protect Flag status (and
not the Protect Register content) to ascertain the
setting of the memory protection.
Protect Register Enable
The Protect Register Enable instruction (PREN) is
used to authorize the use of further PRCLEAR,
PRWRITE and PRDS instructions. The PREN
insruction does not modify the Protect Flag bit
value.
Note: A Write Enable (WEN) instruction must be
executed before the Protect Enable instruction.
Both the Protect Enable (PRE) and Write Enable
(W) input pins must be held High during the instruction execution.
Protect Register Clear
The Protect Register Clear instruction (PRCLEAR)
clears the address stored in the Protect Register to
all 1’s, and thus enables the execution of WRITE
and WRALL instructions. The Protect Register
Clear execution clears the Protect Flag to ’1’. Both
the Protect Enable (PRE) and Write Enable (W)
input pins must be driven High during the instruction execution.
Note: A PREN instruction must immediately precede the PRCLEAR instruction.
Protect Register Write
The Protect Register Write instruction (PRWRITE)
is used to write into the Protect Register the address of the first word to be protected. After the
PRWRITE instruction execution, all memory loca-
10/16
tions equal to and above the specified address, are
protected from writing. The Protect Flag bit is set to
’0’, it can be read with Protect Register Read
instruction. Both the Protect Enable (PRE) and
Write Enable (W) input pins must be driven High
during the instruction execution.
Note: A PREN instruction must immediately precede the PRWRITE instruction, but it is not necessary to execute first a PRCLEAR.
Protect Register Disable
The Protect Register Disable instruction sets the
One Time Programmable bit (OTP bit). The Protect
Register Disable instruction (PRDS) is a ONE TIME
ONLY instruction which latches the Protect Register content, this content is therefore unalterable in
the future. Both the Protect Enable (PRE) and Write
Enable (W) input pins must be driven High during
the instruction execution. The OTP bit cannot be
directly read, it can be checked by reading the
content of the Protect Register (PRREAD instruction), then by writing this same value into the Protect Register (PRWRITE instruction): when the
OTP bit is set, the Ready/Busy status cannot appear on the Data output (Q); when the OTP bit is
not set, the Busy status appear on the Data output
(Q).
A PREN instruction must immediately precede the
PRDS instruction.
READY/BUSY Status
When the ST93CS46/47 is performing the write
cycle, the Busy signal (Q = 0) is returned if S is
driven high, and the ST93CS46/47 will ignore any
data on the bus. When the write cycle is completed,
the Ready signal (Q = 1) will indicate, if S is driven
high, that the ST93CS46/47 is ready to receive a
new instruction. Once the ST93CS46/47 is Ready,
the Data Output Q is set to ’1’ until a new Start bit
is decoded or the Chip Select is brought Low.
COMMON I/O OPERATION
The Data Output (Q) and Data Input (D) signals can
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memory with this connection, mostly to prevent
a short circuit between the last entered address bit
(A0) and the first data bit output by Q. The reader
should refer to the SGS-THOMSON application
note ”MICROWIRE EEPROM Common I/O Operation”.
ST93CS46, ST93CS47
Figure 8. PRREAD, PRWRITE, PREN Sequences
Protect
Register
READ
PRE
S
D
1 1 0 Xn
X0
Q
An
ADDR
OP
CODE
Protect
Register
WRITE
A0 F
F = Protect Flag
DATA
OUT
PRE
W
S
CHECK
STATUS
D
1 0 1 An
A0
Q
ADDR
BUSY
READY
OP
CODE
Protect
Register
ENABLE
PRE
W
S
D
1 0 0 1 1 Xn X0
OP
CODE
AI00891D
11/16
ST93CS46, ST93CS47
Figure 9. PRCLEAR, PRDS Sequences
Protect
Register
CLEAR
PRE
W
S
CHECK
STATUS
D
1 11
111
Q
ADDR
BUSY
READY
OP
CODE
Protect
Register
DISABLE
PRE
W
S
CHECK
STATUS
D
1 00
000
Q
ADDR
BUSY
READY
OP
CODE
AI00892C
12/16
ST93CS46, ST93CS47
ORDERING INFORMATION SCHEME
Example:
ST93CS46
3V to 5.5V
47
2.5V to 5.5V
1
013TR
Temp. Range
Package
Operating Voltage
46
M
B
PSDIP8
0.4 mm Frame
1
0 to 70 °C
6
–40 to 85 °C
M
SO8
150mil Width
(1)
–40 to 125 °C
3
Option
013TR Tape & Reel
Packing
Note: 1. Temperature range on request only.
Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the SGS-THOMSON Sales Office nearest to you.
13/16
ST93CS46, ST93CS47
PSDIP8 - 8 pin Plastic Skinny DIP, 0.4mm lead frame
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
4.80
0.189
A1
0.70
–
0.028
–
A2
3.10
3.60
0.122
0.142
B
0.38
0.58
0.015
0.023
B1
1.15
1.65
0.045
0.065
C
0.38
0.52
0.015
0.020
D
9.20
9.90
0.362
0.390
–
–
–
–
6.30
7.10
0.248
0.280
–
–
–
–
8.40
–
0.331
–
E
7.62
E1
e1
2.54
eA
eB
0.300
0.100
9.20
L
3.00
N
8
0.362
3.80
0.118
0.10
0.004
PSDIP8
A2
A1
B
A
L
e1
eA
eB
B1
D
C
N
E1
E
1
PSDIP-a
Drawing is not to scale
0.150
8
CP
14/16
Max
ST93CS46, ST93CS47
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
Symb
Typ
inches
Min
Max
A
1.35
A1
Min
Max
1.75
0.053
0.069
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
1.27
CP
Typ
0.050
8
0.10
0.004
SO8
h x 45°
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Drawing is not to scale
15/16
ST93CS46, ST93CS47
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
 1997 SGS-THOMSON Microelectronics - All Rights Reserved
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