NSC 93L28DMQB

93L28
Dual 8-Bit Shift Register
General Description
Features
The 93L28 is a high speed serial storage element providing
16 bits of storage in the form of two 8-bit registers. The
multifunctional capability of this device is provided by several features: 1) additional gating is provided at the input to
both shift registers so that the input is easily multiplexed
between two sources; 2) the clock of each register may be
provided separately or together; 3) both the true and complementary outputs are provided from each 8-bit register,
and both registers may be master cleared from a common
input.
Y
Connection Diagram
Logic Symbol
Y
Y
Y
2-input multiplexer provided at data input of each
register
Gated clock input circuitry
Both true and complementary outputs provided from
last bit of each register
Asynchronous master reset common to both registers
Dual-In-Line Package
TL/F/10200 – 1
Order Number 93L28DMQB or 93L28FMQB
See NS Package Number J16A or W16A
TL/F/10200 – 2
VCC e Pin 16
GND e Pin 8
Pin
Names
S
D0, D1
CP
MR
Q7
Q7
C1995 National Semiconductor Corporation
TL/F/10200
Description
Data Select Input
Data Inputs
Clock Pulse Input (Active HIGH)
Common (Pin 9)
Separate (Pins 7 and 10)
Master Reset Input (Active LOW)
Last Stage Output
Complementary Output
RRD-B30M105/Printed in U. S. A.
93L28 Dual 8-Bit Shift Register
June 1989
Absolute Maximum Ratings (Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
b 55§ C to a 125§ C
MIL
b 65§ C to a 150§ C
Storage Temperature Range
Recommended Operating Conditions
Symbol
93L28 (MIL)
Parameter
Units
Min
Nom
Max
4.5
5
5.5
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
TA
Free Air Operating Temperature
ts(H)
ts(L)
Setup Time HIGH or LOW
Dn to CP
30
30
ns
th(H)
th(L)
Hold Time HIGH or LOW
Dn to CP
0
0
ns
tw(H)
tw(L)
Clock Pulse Width
HIGH or LOW
55
55
ns
tw(L)
MR Pulse Width with CP HIGH
60
ns
tw(L)
MR Pulse Width with CP LOW
70
ns
2
b 55
2
V
V
0.7
V
b 400
mA
4.8
mA
125
§C
Electrical Characteristics over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
VI
Input Clamp Voltage
VCC e Min, II e b10 mA
VOH
High Level Output Voltage
VCC e Min, IOH e Max,
VIL e Max, VIH e Min
VOL
Low Level Output Voltage
VCC e Min, IOL e Max,
VIH e Min, VIL e Max
II
Input Current @ Max
Input Voltage
VCC e Max, VI e 5.5V
IIH
HIGH Level
Input Current
VCC e Max, VI e 2.4V
IIL
LOW Level
Input Current
VCC e Max, VI e 0.3V
Min
Typ
(Note 1)
Short Circuit
Output Current
VCC e Max
(Note 2)
ICC
Supply Current
VCC e Max
Units
b 1.5
V
2.4
V
0.3
V
1
mA
MR, Dx
20
CP (7, 10)
30
S
40
CP Com
60
MR, Dx
b 400
CP (7, 10)
b 600
S
b 800
CP Com
IOS
Max
mA
mA
b 1200
b 2.5
b 25
mA
25.3
mA
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
VCC e a 5.0V, TA e a 25§ C (See Section 1 for test waveforms and output load)
Symbol
CL e 15 pF
Parameter
Min
Units
Max
fmax
Maximum Shift Right Frequency
5.0
tPLH
tPHL
Propagation Delay
CP to Q7 or Q7
45
80
ns
tPHL
Propagation Delay MR to Q7
110
ns
3
MHz
Functional Description
Each 8-bit shift register has a 2-input multiplexer in front of
the serial data input. The two data inputs D0 and D1 are
controlled by the data select input (S) following the Boolean
expression:
Serial data in: SD e SD0 a SD1
The two 8-bit shift registers have a common clock input (pin
9) and separate clock inputs (pins 10 and 7). The clocking
of each register is controlled by the OR function of the separate and the common clock input. Each register is composed of eight clocked RS master/slave flip-flops and a
number of gates. The clock OR gate drives the eight clock
inputs of the flip-flops in parallel. When the two clock inputs
(the separate and the common) to the OR gate are LOW,
the slave latches are steady, but data can enter the master
latches via the R and S input. During the first LOW-to-HIGH
transition of either, or both simultaneously, of the two clock
inputs, the data inputs (R and S) are inhibited so that a later
change in input data will not affect the master; then the now
trapped information in the master is transferred to the slave.
When the transfer is complete, both the master and the
slave are steady as long as either or both clock inputs remain HIGH. During the HIGH-to-LOW transition of the last
remaining HIGH clock input, the transfer path from master
to slave is inhibited first, leaving the slave steady in its present state. The data inputs (R and S) are enabled so that new
data can enter the master. Either of the clock inputs can be
used as clock inhibit inputs by applying a logic HIGH signal.
An asynchronous master reset is provided which, when activated by a LOW logic level, will clear all 16 stages independently of any other input signal.
Shift Select Table
Inputs
Output
S
D0
D1
Q7 (tn a 8)
L
L
H
H
L
H
X
X
X
X
L
H
L
H
L
H
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
n a 8 e Indicates state after eight clock pulse
Logic Diagram
TL/F/10200 – 3
4
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 93L28DMQB
NS Package Number J16A
5
93L28 Dual 8-Bit Shift Register
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 93L28FMQB
NS Package Number W16A
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