54165/DM74165 8-Bit Parallel-to-Serial Converter General Description The ’165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable. Connection Diagram Logic Symbol Dual-In-Line-Package TL/F/9782 – 2 VCC e Pin 16 GND e Pin 8 TL/F/9782 – 1 Order Number 54165DMQB, 54165FMQB or DM74165N See NS Package Number J16A, N16E or W16A Pin Names CP1, CP2 DS PL P0–P7 Q7 Q7 C1995 National Semiconductor Corporation TL/F/9782 Description Clock Pulse Inputs (Active Rising Edge) Serial Data Input Asynchronous Parallel Load Input (Active LOW) Parallel Data Inputs Serial Output from Last Stage Complementary Output RRD-B30M115/Printed in U. S. A. 54165/DM74165 8-Bit Parallel-to-Serial Converter August 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C 54 DM74 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol 54165 Parameter DM74165 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 V 0.8 0.8 V b 0.8 b 0.8 mA 16 mA 70 §C VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current TA Free Air Operating Temperature ts(H) ts(L) Setup Time HIGH or LOW Pn to PL 10 10 10 10 ns th(H) th(L) Hold Time HIGH or LOW Pn to PL 10 10 0 0 ns ts(H) ts(L) Setup Time HIGH or LOW DS to CPn 20 20 20 20 ns th(H) th(L) Hold Time HIGH or LOW DS to CPn 0 0 0 0 ns ts(H) Setup Time HIGH CP1 to CP2 or CP2 to CP1 30 30 ns tw(H) CPn Pulse Width HIGH 25 25 ns tw(L) PL Pulse Width LOW 15 15 ns trec Recovery Time, PL to CPn 45 45 ns 2 2 V 16 b 55 125 0 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max, VIL e Max VOL Low Level Output Voltage VCC e Min, VIH e Min II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max, VI e 2.4V IIL IOS ICC Low Level Input Current VCC e Max, VI e 0.4V Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max, PL e ß Pn e K, CP1, CP2 e 4.5V 2 Min Typ (Note 1) 2.4 3.4 Max b 1.5 0.2 Units V V 0.4 V 1 mA PL 80 Inputs 40 PL b 3.2 Inputs b 1.6 54 b 20 b 55 DM74 b 18 b 55 63 mA mA mA mA Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for waveforms and load configurations) Symbol CL e 15 pF RL e 400X Parameter Min Units Max fmax Maximum Clock Frequency 20 MHz tPLH tPHL Propagation Delay PL to Q7 or Q7 31 40 ns tPLH tPHL Propagation Delay CP1 to Q7 or Q7 24 31 ns tPLH tPHL Propagation Delay P7 to Q7 17 36 ns tPLH tPHL Propagation Delay P7 to Q7 27 27 ns Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Functional Description by applying a HIGH signal. To avoid double clocking, however, the inhibit signal should only go HIGH while the clock is HIGH. Otherwise, the rising inhibit signal will cause the same response as a rising clock edge. The flip-flops are edge-triggered for serial operations. The serial input data can change at any time, provided only that the recommended setup and hold times are observed, with respect to the rising edge of the clock. The ’165 contains eight clocked master/slave RS flip-flops connected as a shift register with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL signal is LOW. The parallel data can change while PL is LOW provided that the recommended setup and hold times are observed. For clocked operation, PL must be HIGH. The two clock inputs perform identically; one can be used as a clock inhibit Truth Table CP PL L H H H H Contents Response 1 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 X L H L L X L L L H P0 DS Q0 DS Q0 P1 Q0 Q1 Q0 Q1 P2 Q1 Q2 Q1 Q2 P3 Q2 Q3 Q2 Q3 P4 Q3 Q4 Q3 Q4 P5 Q4 Q5 Q4 Q5 P6 Q5 Q6 Q5 Q6 P7 Q6 Q7 Q6 Q7 Parallel Entry Right Shift No Change Right Shift No Change H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e Positive Rising Edge Logic Diagram TL/F/9782 – 3 3 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54165DMQB NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74165N NS Package Number N16E 5 54165/DM74165 8-Bit Parallel-to-Serial Converter Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54165FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.