MICROCHIP 93LC46-P

M
93LC46/56/66
1K/2K/4K 2.0V Microwire® Serial EEPROM
FEATURES
BLOCK DIAGRAM
VCC
• Single supply with programming operation down
to 2.0V (Commercial only)
• Low power CMOS technology
- 1 mA active current typical
- 5 µA standby current (typical) at 3.0V
• ORG pin selectable memory configuration
- 128 x 8 or 64 x 16-bit organization (93LC46)
- 256 x 8 or 128 x 16-bit organization(93LC56)
- 512 x 8 or 256 x 16-bit organization(93LC66)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles guaranteed on
93LC56 and 93LC66
• 1,000,000 E/W cycles guaranteed on 93LC46
• Data retention > 200 years
• 8-pin PDIP/SOIC and 14-pin SOIC package
(SOIC in JEDEC and EIAJ standards)
• Temperature ranges supported
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
VSS
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
COUNTER
OUTPUT
BUFFER
DATA REGISTER
DO
DI
MODE
DECODE
LOGIC
CS
CLOCK
GENERATOR
CLK
DESCRIPTION
The Microchip Technology Inc. 93LC46/56/66 are 1K,
2K, and 4K low-voltage serial Electrically Erasable
PROMs. The device memory is configured as x8 or x16
bits, depending on the ORG pin setup. Advanced
CMOS technology makes these devices ideal for
low-power, nonvolatile memory applications. The
93LC46/56/66 is available in standard 8-pin DIP and 8/
14-pin surface mount SOIC packages. The 93LC46X/
56X/66X are only offered in an “SN” package.
PACKAGE TYPES
SOIC
DIP
DI
3
DO
4
7
NU
CS
1
CLK
2
6
ORG
DI
3
5
VSS
DO
4
 1997 Microchip Technology Inc.
8
7
VCC
NU
NU
1
VCC
2
6
ORG
CS
3
5
VSS
CLK
4
1
14
NC
CS
2
13
Vcc
CLK
3
12
NU
11
NC
ORG
93LC56
93LC66
2
VCC
SOIC
93LC46X
93LC56X
93LC66X
CLK
8
93LC46
93LC56
93LC66
1
93LC46
93LC56
93LC66
CS
SOIC
NC
8
ORG
NC
4
7
VSS
DI
5
10
6
DO
DO
6
9
VSS
5
DI
NC
7
8
NC
DS11168L-page 1
93LC46/56/66
1.0
1.1
ELECTRICAL
CHARACTERISTICS
PIN function Table
Name
CS
CLK
DI
DO
VSS
ORG
NU
NC
VCC
Maximum Ratings*
Vcc ...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to Vcc +1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied................. -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins................................................4 kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1
DC AND AC ELECTRICAL CHARACTERISTICS
Parameter
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Commercial (C): Vcc = +2.0V to +6.0V (C): Tamb = 0˚C to +70˚C
Industrial (I):
Vcc = +2.5V to +6.0V (I): Tamb = -40˚C to +85˚C
Symbol
Min.
Max.
Units
Conditions
VIH1
VIH2
VIL1
VIL2
VOL1
VOL2
VOH1
VOH2
ILI
ILO
CIN, COUT
2.0
0.7 Vcc
-0.3
-0.3
—
—
2.4
Vcc-0.2
-10
-10
—
Vcc +1
Vcc +1
0.8
0.2 Vcc
0.4
0.2
—
—
10
10
7
V
V
V
V
V
V
V
V
µA
µA
pF
ICC read
—
ICC write
ICCS
—
—
FCLK
—
TCKH
TCKL
TCSS
TCSH
TCSL
TDIS
TDIH
TPD
TCZ
TSV
TWC
TEC
TWL
250
250
50
0
250
100
100
—
—
—
—
—
—
1
500
3
100
30
2
1
—
—
—
—
—
—
—
400
100
500
10
15
30
mA
µA
mA
µA
µA
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
—
—
1M
10M
—
—
cycles
Operating current
Standby current
Clock frequency
Clock high time
Clock low time
Chip select setup time
Chip select hold time
Chip select low time
Data input setup time
Data input hold time
Data output delay time
Data output disable time
Status valid time
Program cycle time
Endurance
93LC46
93LC56/66
Note 1:
2:
3:
4:
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Not Utilized
No Connect
Power Supply
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
IOL = 2.1 mA; Vcc = 4.5V
IOL =100 µA; Vcc = Vcc Min.
IOH = -400 µA; Vcc = 4.5V
IOH = -100 µA; Vcc = Vcc Min.
VIN = 0.1V to Vcc
VOUT = 0.1V to Vcc
VIN/VOUT = 0 V (Notes 1 & 3)
Tamb = +25°C, FCLK = 1 MHz
FCLK = 2 MHz; Vcc = 6.0V
FCLK = 1 MHz; Vcc = 3.0V
FCLK = 2 MHz; Vcc = 6.0V (Note 3)
CLK = CS = 0V; Vcc = 6.0V
CLK = CS = 0V; Vcc = 3.0V
Vcc ≥ 4.5V
Vcc < 4.5V
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
CL = 100 pF
CL = 100 pF (Note 3)
CL = 100 pF
ERASE/WRITE mode (Note 2)
ERAL mode
WRAL mode
25°C, Vcc = 5.0V, Block Mode (Note 4)
This parameter is tested at Tamb = 25˚C and FCLK = 1 MHz.
Typical program cycle time is 4 ms per word.
This parameter is periodically sampled and not 100% tested.
This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
DS11168L-page 2
 1997 Microchip Technology Inc.
93LC46/56/66
2.0
PIN DESCRIPTION
2.3
2.1
Chip Select (CS)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
A high level selects the device. A low level deselects the
device and forces it into standby mode. However, a programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the programming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal control logic is held in a RESET status.
2.2
Serial Clock (CLK)
The Serial Clock (CLK) is used to synchronize the communication between a master device and the 93LCXX.
Opcodes, addresses, and data bits are clocked in on
the positive edge of CLK. Data bits are also clocked out
on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing the opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
2.4
Data In (DI)
Data Out (DO)
Data Out (DO) is used in the READ mode to output data
synchronously with the CLK input (TPD after the positive edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation has
been initiated.
The status signal is not available on DO, if CS is held
low or high during the entire WRITE or ERASE cycle. In
all other cases DO is in the HIGH-Z mode. If status is
checked after the ERASE/WRITE cycle, a pull-up
resistor on DO is required to read the READY signal.
2.5
Organization (ORG)
When ORG is tied to VSS, the (x8) memory organization is selected. When ORG is connected to Vcc or
floated, the (x16) memory organization is selected.
ORG can only be floated for clock speeds of 1 MHz or
less for the (X16) memory organization. For clock
speeds greater than 1 MHz, ORG must be tied to Vcc
or VSS.
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified number of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcodes, addresses,
and data bits before an instruction is executed
(Table 2-1 to Table 2-6). CLK and DI then become don't
care inputs waiting for a new START condition to be
detected.
Note:
CS must go low between consecutive
instructions.
 1997 Microchip Technology Inc.
DS11168L-page 3
93LC46/56/66
TABLE 2-1
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-2
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-3
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-4
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-5
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
TABLE 2-6
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
DS11168L-page 4
INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
11
00
00
00
10
01
00
A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X
0 0 X X X X X
1 1 X X X X X
A6 A5 A4 A3 A2 A1 A0
A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X
—
—
—
—
—
D7 - D0
D7 - D0
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
10
10
10
10
18
18
18
INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
11
00
00
00
10
01
00
A5 A4 A3 A2 A1 A0
1 0 X X X X
0 0 X X X X
1 1 X X X X
A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0
0 1 X X X X
—
—
—
—
—
D15 - D0
D15 - D0
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
9
9
9
9
25
25
25
INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
11
00
00
00
10
01
00
X A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X X
0 0 X X X X X X X
1 1 X X X X X X X
X A7 A6 A5 A4 A3 A2 A1 A0
X A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X X
—
—
—
—
—
D7 - D0
D7 - D0
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
12
12
12
12
20
20
20
INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
11
00
00
00
10
01
00
X A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X
0 0 X X X X X X
1 1 X X X X X X
X A6 A5 A4 A3 A2 A1 A0
X A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X
—
—
—
—
—
D15 - D0
D15 - D0
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
11
11
11
11
27
27
27
INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
11
00
00
00
10
01
00
A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X X
0 0 X X X X X X X
1 1 X X X X X X X
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X X
—
—
—
—
—
D7 - D0
D7 - D0
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
12
12
12
12
20
20
20
INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)
SB
Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
10
00
11
00
01
00
00
A7 A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X
A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X
A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X
0 0 X X X X X X
—
—
—
—
D15 - D0
D15 - D0
—
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
27
11
11
11
27
27
11
 1997 Microchip Technology Inc.
93LC46/56/66
3.0
FUNCTIONAL DESCRIPTION
When it is connected to ground, the (x8) organization is
selected. When the ORG pin is connected to Vcc, the
(x16) organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a HIGH-Z state, except when reading data from the
device or when checking the READY/BUSY status during a programming operation. The READY/BUSY
status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates
the device is ready. The DO will enter the HIGH-Z state
on the falling edge of the CS.
3.1
START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
3.2
Data In (DI) and Data Out (DO)
It is possible to connect the Data In (DI) and Data Out
(DO) pins together. However, with this configuration, if
A0 is a logic-high level, it is possible for a “bus conflict”
to occur during the “dummy zero” that precedes the
READ operation. Under such a condition the voltage
level seen at DO is undefined and will depend upon the
relative impedances of Data Out, and the signal source
driving A0. The higher the current sourcing capability of
A0, the higher the voltage at the DO pin.
3.3
Data Protection
During power-up, all programming modes of operation
are inhibited until Vcc has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 1.4V at nominal conditions.
The ERASE/WRITE Disable (EWDS) and ERASE/
WRITE Enable (EWEN) commands give additional protection against accidentally programming during normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
An instruction following a START condition will only be
executed if the required amount of opcodes,
addresses, and data bits for any particular instruction is
clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new START condition is
detected.
FIGURE 3-1:
SYNCHRONOUS DATA TIMING
V IH
CS
TCSS
V IL
TCKH
TCKL
TCSH
V IH
CLK
V IL
TDIS
TDIH
V IH
DI
V IL
TPD
DO
(READ)
TPD
TCZ
V OH
TCZ
V OL
DO V OH
(PROGRAM)
V OL
TSV
 1997 Microchip Technology Inc.
STATUS VALID
DS11168L-page 5
93LC46/56/66
3.4
ERASE
3.5
The ERASE instruction forces all data bits of the specified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The ERAL instruction is
guaranteed at Vcc = +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is complete.
The ERASE cycle takes 4 ms per word (Typical).
The ERAL cycle takes 15 ms maximum (8 ms typical).
FIGURE 3-2:
ERASE TIMING
TCSL
CS
CHECK STATUS
STANDBY
CLK
1
DI
1
1
An
An-1
An-2
•••
A0
TCZ
TSV
DO
TRI-STATE
READY
BUSY
TRI-STATE
TWC
FIGURE 3-3:
ERAL TIMING
TCSL
CS
CHECK STATUS
STANDBY
CLK
1
DI
0
0
1
0
T CZ
TSV
DO
TRI-STATE
TRI-STATE
BUSY
READY
T EC
Guarantee at Vcc = +4.5V to +6.0V.
DS11168L-page 6
 1997 Microchip Technology Inc.
93LC46/56/66
3.6
ERASE/WRITE Disable and Enable
(EWEN, EWDS)
3.7
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (x8 organization) or 16-bit
(x16 organization) output string. The output data bits
will toggle on the rising edge of the CLK and are stable
after the specified time delay (TPD.). Sequential read is
possible when CS is held high. The memory data will
automatically cycle to the next register and output
sequentially.
The 93LC46/56/66 powers up in the ERASE/WRITE
Disable (EWDS) state. All programming modes must
be preceded by an ERASE/WRITE Enable (EWEN)
instruction. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To
protect against accidental data disturb, the EWDS
instruction can be used to disable all ERASE/WRITE
functions and should follow all programming operations. Execution of a READ instruction is independent
of both the EWDS and EWEN instructions.
FIGURE 3-4:
READ
EWDS TIMING
TCSL
CS
CLK
DI
FIGURE 3-5:
1
0
0
0
0
•••
X
X
EWEN TIMING
T CSL
CS
CLK
DI
FIGURE 3-6:
1
0
0
1
1
•••
X
X
READ TIMING
TCSL
CS
CLK
DI
DO
1
1
0

TRI-STATE
TRI-STATE™
• An
•••
A0
0
Dx
•••
D0
Dx*
•••
D0
Dx*
•••
D0
TRI-STATE
registeredof
trademark
National Semiconductor Incorporated.
Tri-State isisa atrademark
National of
Semiconductor.
 1997 Microchip Technology Inc.
DS11168L-page 7
93LC46/56/66
3.8
WRITE
3.9
The WRITE instruction is followed by 8 bits (or by 16
bits) of data which are written into the specified
address. After the last data bit is put on the DI pin, CS
must be brought low before the next rising edge of the
CLK clock. This falling edge of CS initiates the selftimed auto-erase and programming cycle.
Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the self clocking mode. The WRAL command does
include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL
instruction, but the chip must be in the EWEN status.
The WRAL instruction is guaranteed at VCC = +4.5V to
+6.0V.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is complete.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruction.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
The WRITE cycle takes 4 ms per word (Typical).
The WRAL cycle takes 30 ms maximum (16 ms typical).
FIGURE 3-7:
WRITE TIMING
TCSL
CS
STANDBY
CLK
DI
1
0
1
•An
•••
A0
Dx
•••
D0
BUSY
TRI-STATE
DO
READY
TRI_STATE
TWC
FIGURE 3-8:
WRAL TIMING
T CSL
CS
STANDBY
CLK
DI
DO
1
0
0
0
1
X
•••
X
Dx
•••
D0
TRI-STATE
BUSY
READY
TRI-STATE
T WL
Guarantee at Vcc = +4.5V to +6.0V.
DS11168L-page 8
 1997 Microchip Technology Inc.
93LC46/56/66
NOTES:
 1997 Microchip Technology Inc.
DS11168L-page 9
93LC46/56/66
NOTES:
DS11168L-page 10
 1997 Microchip Technology Inc.
93LC46/56/66
93LC46/56/66 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office..
93LC46/56/66
—
/P
P = Plastic DIP (300 mil Body), 8-lead
Package:
SL = Plastic SOIC (107 mil Body), 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body), 8-lead
Temperature
Range:
Blank = 0˚C to +70˚C
I = –40˚C to +85˚C
93LC46
93LC46T
1K Microwire Serial EERPOM, Tape and Reel
93LC46X
1K Microwire Serial EEPROM in alternate
pinouts (SN package only)
93LC46XT
1K Microwire Serial EEPROM in alternate
pinouts, Tape and Reel (SN package only)
93LC56
Device:
1K Microwire Serial EEPROM
2K Microwire Serial EEPROM
93LC56T
2K Microwire Serial EERPOM, Tape and Reel
93LC56X
2K Microwire Serial EEPROM in alternate
pinouts (SN package only)
93LC56XT
2K Microwire Serial EEPROM in alternate
pinouts, Tape and Reel (SN package only)
93LC66
4K Microwire Serial EEPROM
93LC66T
4K Microwire Serial EERPOM, Tape and Reel
93LC66X
4K Microwire Serial EEPROM in alternate
pinouts (SN package only)
93LC66XT
4K Microwire Serial EEPROM in alternate
pinouts, Tape and Reel (SN package only)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
 1997 Microchip Technology Inc.
DS11168L-page 11
WORLDWIDE SALES & SERVICE
AMERICAS
ASIA/PACIFIC
EUROPE
Corporate Office
Hong Kong
United Kingdom
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602-786-7200 Fax: 602-786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
Microchip Asia Pacific
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44-1628-851077 Fax: 44-1628-850259
Atlanta
India
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Microchip Technology India
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Boston
Korea
Germany
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Müchen, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Shanghai
Arizona Microchip Technology SRL
Centro Direzionale Colleone
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, PRC 200335
Tel: 86-21-6275-5700
Fax: 86 21-6275-5060
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972-991-7177 Fax: 972-991-8588
Singapore
Microchip Technology Taiwan
Singapore Branch
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Taiwan, R.O.C
Los Angeles
France
Italy
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2-717-7175 Fax: 886-2-545-0139
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 714-263-1888 Fax: 714-263-1338
New York
5/8/97
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
M
All rights reserved. © 1997, Microchip Technology Incorporated, USA. 6/97
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or
warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other
intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks
of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS11168L-page 12
Preliminary
 1997 Microchip Technology Inc.