MICROCHIP 93LC76

93LC76/86
8K/16K 2.5V Microwire Serial EEPROM
FEATURES
PACKAGE TYPES
DIP Package
2
3
4
8
VCC
7
6
5
PE
ORG
93LC76/86
1
8
VSS
SOIC Package
CS
CLK
DI
DO
1
2
3
4
7
6
5
VCC
PE
ORG
VSS
BLOCK DIAGRAM
VCC VSS
DESCRIPTION
The Microchip Technology Inc. 93LC76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
non-volatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93LC76/86 is available in standard 8-pin DIP and
8-pin surface mount SOIC packages.
CS
CLK
DI
DO
93LC76/86
• Single supply with programming operation down
to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 5 µA standby current (typical) at 3.0V
• ORG pin selectable memory configuration
1024 x 8 or 512 x 16 bit organization (93LC76)
2048 x 8 or 1024 x 16 bit organization (93LC86)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC package
• Temperature ranges available
- Commercial (C)
0°C to +70°C
- Industrial (I)
-40°C to +85°C
Memory
Array
Address
Decoder
Address
Counter
Data
Register
Output
Buffer
DO
DI
PE
CS
CLK
Mode
Decode
Logic
Clock
Generator
Microwire is a registered trademark of National Semiconductor Incorporated.
 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21131C-page 1
93LC76/86
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
AC Waveform:
VLO = 2.0V
VCC ...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to Vcc +1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied................. -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins................................................4 kV
(Note 1)
(Note 2)
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V
PIN FUNCTION TABLE
Name
CS
CLK
DI
DO
VSS
ORG
PE
VCC
VHI = Vcc - 0.2V
VHI = 4.0V for
Timing Measurement Reference Level
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability
TABLE 1-1:
AC Test Conditions
1.2
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Program Enable
Power Supply
TABLE 1-2:
DC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = +2.5V to +6.0V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I):
Tamb = -40˚C to +85˚C
Parameter
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
Symbol
VIH1
VIH2
VIL1
VIL2
VOL1
VOL2
VOH1
VOH2
ILI
ILO
CINT
ICC write
ICC read
Min.
Max.
Units
2.0
0.7 VCC
-0.3
-0.3
—
—
2.4
VCC-0.2
-10
-10
—
VCC +1
VCC +1
0.8
0.2 VCC
0.4
0.2
—
—
10
10
7
V
V
V
V
V
V
V
V
µA
µA
pF
3
mA
1
mA
500
µA
µA
—
100
Standby current
ICCS
30
µA
Note:
This parameter is periodically sampled and not 100% tested.
DS21131C-page 2
—
—
Preliminary
Conditions
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
IOL = 2.1 mA; VCC = 4.5V
IOL =100 µA; VCC = VCC Min.
IOH = -400 µA; VCC = 4.5V
IOH = -100 µA; VCC = VCC Min.
VIN = 0.1V to VCC
VOUT = 0.1V to VCC
(Note Note:)
Tamb = +25˚C, FCLK = 1 MHz
VCC = 5.5V
FCLK = 3 MHz; VCC = 5.5V
FCLK = 1 MHz; VCC = 3.0V
CLK = CS = 0V; VCC = 5.5V
CLK = CS = 0V; VCC = 3.0V
 1996 Microchip Technology Inc.
93LC76/86
TABLE 1-3:
AC CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
VCC = +2.5V to +6.0V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I):
Tamb = -40˚C to +85˚C
Parameter
Symbol
Min.
Max.
Units
Conditions
3
2
—
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5V
2.5V
4.5V
2.5V
4.5V
2.5V
4.5V
2.5V
Clock frequency
FCLK
—
Clock high time
TCKH
Clock low time
TCKL
Chip select setup time
TCSS
Chip select hold time
Chip select low time
Data input setup time
TCSH
TCSL
TDIS
200
300
100
200
50
100
0
250
50
100
Data input hold time
TDIH
Data output delay time
TPD
50
100
—
Data output disable time
TCZ
—
Status valid time
TSV
—
Program cycle time
TWC
TEC
TWL
—
—
—
—
10M
Endurance
—
—
—
—
—
—
100
250
100
500
ns
ns
ns
ns
ns
ns
200
300
5
15
30
—
ns
ns
ms
ms
ms
cycles
≤ VCC ≤ 6.0V
≤ VCC < 4.5V
≤ VCC ≤ 6.0V
≤ VCC < 4.5V
≥ VCC ≤ 6.0V
≤ VCC < 4.5V
≤ VCC ≤ 6.0V, Relative to CLK
≤ VCC < 4.5V, Relative to CLK
Relative to CLK
4.5V ≤ VCC ≤ 6.0V, Relative to CLK
2.5V ≤ VCC <4.5V, Relative to CLK
4.5V ≤ VCC ≤ 6.0V, Relative to CLK
2.5V ≤ VCC < 4.5V, Relative to CLK
4.5V ≤ VCC ≤ 6.0V, CL = 100 pF
2.5V ≤ VCC < 4.5V, CL = 100 pF
4.5V ≤ VCC ≤ 6.0V
2.5V ≤ VCC < 4.5V (Note 1)
4.5V ≥ VCC ≤ 6.0V, CL = 100 pF
2.5V ≤ VCC <4.5V, CL = 100 pF
ERASE/WRITE mode
ERAL mode
WRAL mode
25°C, Vcc = 5.0V, Block Mode
(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be found on our BBS or website.
 1996 Microchip Technology Inc.
Preliminary
DS21131C-page 3
93LC76/86
TABLE 1-4:
Instruction
INSTRUCTION SET FOR 93LC76: ORG=1 (1X16 ORGANIZATION)
SB
Opcode
1
1
1
1
1
1
1
10
00
11
00
01
00
00
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-5:
Instruction
SB
Opcode
1
1
1
1
1
1
1
10
00
11
00
01
00
00
TABLE 1-6:
X A8 A7 A6 A5 A4 A3
1 1 X X X X X
X A8 A7 A6 A5 A4 A3
1 0 X X X X X
X A8 A7 A6 A5 A4 A3
0 1 X X X X X
0 0 X X X X X
A2
X
A2
X
A2
X
X
A1
X
A1
X
A1
X
X
A0
—
X
—
A0
—
X
—
A0 D15 - D0
X D15 - D0
X
—
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK
Cycles
29
13
13
13
29
29
13
Address
X A9 A8 A7 A6 A5 A4
1 1 X X X X X
X A9 A8 A7 A6 A5 A4
1 0 X X X X X
X A9 A8 A7 A6 A5 A4
0 1 X X X X X
0 0 X X X X X
A3
X
A3
X
A3
X
X
A2
X
A2
X
A2
X
X
A1 A0
X
A1 A0
X
A1 A0
X
X
Data In
Data Out
—
—
—
—
D7 - D0
D7 - D0
—
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK
Cycles
22
14
14
14
22
22
14
INSTRUCTION SET FOR 93LC86: ORG=1 (X16 ORGANIZATION)
SB
Opcode
1
1
1
1
1
1
1
10
00
11
00
01
00
00
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
TABLE 1-7:
Instruction
Data In
INSTRUCTION SET FOR 93LC76: ORG=0 (X8 ORGANIZATIONI
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
Instruction
Address
Address
A9
1
A9
1
A9
0
0
A8
1
A8
0
A8
1
0
A7
X
A7
X
A7
X
X
A6
X
A6
X
A6
X
X
A5
X
A5
X
A5
X
X
A4
X
A4
X
A4
X
X
Data In
A3
X
A3
X
A3
X
X
A2
X
A2
X
A2
X
X
A1
X
A1
X
A1
X
X
A0
—
X
—
A0
—
X
—
A0 D15 - D0
X D15 - D0
X
—
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK
Cycles
29
13
13
13
29
29
13
INSTRUCTION SET FOR 93LC86: ORG=0 (X8 ORGANIZATION)
SB
Opcode
1
1
1
1
1
1
1
10
00
11
00
01
00
00
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
DS21131C-page 4
Address
A10 A9 A8 A7 A6 A5 A4
1
1 X X X X X
A10 A9 A8 A7 A6 A5 A4
1
0 X X X X X
A10 A9 A8 A7 A6 A5 A4
0
1 X X X X X
0
0 X X X X X
A3
X
A3
X
A3
X
X
Preliminary
A2
X
A2
X
A2
X
X
Data In
Data Out
Req. CLK
Cycles
A1 A0
—
X
—
A1 A0
—
X
—
A1 A0 D7 - D0
X
D7 - D0
X
—
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
22
14
14
14
22
22
14
 1996 Microchip Technology Inc.
93LC76/86
2.0
PRINCIPLES OF OPERATION
When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the
x8 organization is selected. Instructions, addresses
and write data are clocked into the DI pin on the rising
edge of the clock (CLK). The DO pin is normally held in
a high-Z state except when reading data from the
device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an Erase/Write operation by
polling the DO pin; DO low indicates that programming
is still in progress, while DO high indicates the device is
ready. The DO will enter the high impedance state on
the falling edge of the CS.
2.1
2.3
The 93LC76/86 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction.
Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed
or VCC is removed from the device. To protect against
accidental data disturb, the EWDS instruction can be
used to disable all Erase/Write functions and should follow all programming operations. Execution of a READ
instruction is independent of both the EWEN and
EWDS instructions.
2.4
START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction are clocked
in.
Erase/Write Enable and Disable
(EWEN, EWDS)
Data Protection
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V.
The EWEN and EWDS commands give additional protection against accidentally programming during normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction can
be executed.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero” that
precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0, the
higher the voltage at the Data Out pin.
 1996 Microchip Technology Inc.
Preliminary
DS21131C-page 5
93LC76/86
3.0
DEVICE OPERATION
3.1
READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable after
the specified time delay (TPD). Sequential read is possible when CS is held high and clock transitions continue. The memory address pointer will automatically
increment and output data sequentially.
3.2
ERASE
The ERASE instruction forces all data bits of the specified address to the logical “1” state. The self-timed programming cycle is initiated on the rising edge of CLK as
the last address bit (A0) is clocked in. At this point, the
CLK, CS, and DI inputs become don’t cares.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO pin
to enter the high impedance state. DO at logical “0” indicates that programming is still in progress. DO at logical
“1” indicates that the register at the specified address
has been erased and the device is ready for another
instruction.
The ERASE cycle takes 3 ms per word (Typical).
3.3
WRITE
The WRITE instruction is followed by 16 bits (or by 8
bits) of data to be written into the specified address.
The self-timed programming cycle is initiated on the rising edge of CLK as the last data bit (D0) is clocked in.
At this point, the CLK, CS, and DI inputs become don’t
cares.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO pin
to enter the high impedance state. DO at logical “0” indicates that programming is still in progress. DO at logical
“1” indicates that the register at the specified address
has been written and the device is ready for another
instruction.
the least significant 8 or 9 address bits are don’t care
bits, depending on selection of x16 or x8 mode. Clocking of the CLK pin is not necessary after the device has
entered the self clocking mode. The ERAL instruction is
guaranteed at Vcc = +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO pin
to enter the high impedance state. DO at logical “0” indicates that programming is still in progress. DO at logical
“1” indicates that the entire device has been erased and
is ready for another instruction.
The ERAL cycle takes 15 ms maximum (8 ms typical).
3.5
Write All (WRAL)
The WRAL instruction will write the entire memory array
with the data specified in the command. The WRAL
cycle is completely self-timed and commences on the
rising edge of the last address bit (A0). Note that the
least significant 8 or 9 address bits are don’t cares,
depending on selection of x16 or x8 mode. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The WRAL command
does include an automatic ERAL cycle for the device.
Therefore, the WRAL instruction does not require an
ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is guaranteed at Vcc = +4.5V
to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if the CS is high. The READY/BUSY status will
be displayed on the DO pin until the next start bit is
received as long as CS is high. Bringing the CS low will
place the device in standby mode and cause the DO pin
to enter the high impedance state. DO at logical “0” indicates that programming is still in progress. DO at logical
“1” indicates that the entire device has been written and
is ready for another instruction.
The WRAL cycle takes 30 ms maximum (16 ms typical).
The WRITE cycle takes 3 ms per word (Typical).
3.4
Erase All (ERAL)
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identical
to the ERASE cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
on the rising edge of the last address bit (A0). Note that
DS21131C-page 6
Preliminary
 1996 Microchip Technology Inc.
93LC76/86
FIGURE 3-1:
SYNCHRONOUS DATA TIMING
VIH
CS
TCSS
VIL
TCKH
TCKL
TCSH
VIH
CLK
VIL
TDIH
TDIS
VIH
DI
VIL
DO
(Read)
TPD
VOH
VOL
TCZ
TPD
TCZ
TSV
VOH
DO
(Program) VOL
STATUS VALID
The memory automatically cycles to the next register.
FIGURE 3-2:
READ
TCSL
CS
CLK
1
DI
1
0
...
AN
A0
HIGH IMPEDANCE
DO
FIGURE 3-3:
0
DN
...
D0
DN
...
D0
EWEN
TCSL
CS
CLK
DI
1
0
0
1
1
...
X
X
ORG=VCC, 8 X’s
ORG=VSS, 9 X’s
FIGURE 3-4:
EWDS
TCSL
CS
CLK
DI
1
0
0
0
0
X
...
X
ORG=VCC, 8 X’s
ORG=VSS, 9 X’S
 1996 Microchip Technology Inc.
Preliminary
DS21131C-page 7
93LC76/86
FIGURE 3-5:
WRITE
CS
STANDBY
CLK
DI
1
0
1
...
AN
...
DN
A0
D0
TCZ
HIGH IMPEDANCE
DO
READY
BUSY
TWC
FIGURE 3-6:
WRAL
STANDBY
CS
CLK
1
DI
0
0
0
1
X
...
X
DN
...
D0
TCZ
HIGH IMPEDANCE
DO
ORG=VCC, 8 X’s
ORG=VSS, 9 X’s
FIGURE 3-7:
BUSY
READY
TWL
Guarantee at Vcc = +4.5V to +6.0V.
ERASE
CS
STANDBY
CLK
DI
1
1
1
AN
...
...
A0
TCZ
DO
HIGH IMPEDANCE
BUSY
READY
TWC
DS21131C-page 8
Preliminary
 1996 Microchip Technology Inc.
93LC76/86
FIGURE 3-8:
ERAL
CS
STANDBY
CLK
DI
1
0
0
1
0
X
...
X
TCZ
HIGH IMPEDANCE
BUSY
DO
ORG=VCC, 8 X’s
ORG=VSS, 9 X’s
PIN DESCRIPTIONS
4.1
Chip Select (CS)
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated will be
completed, regardless of the CS input signal. If CS is
brought LOW during a program cycle, the device will go
into standby mode as soon as the programming cycle
is completed.
CS must be LOW for 250 ns minimum (TCSL) between
consecutive instructions. If CS is LOW, the internal control logic is held in a RESET status.
4.2
TEC
Guaranteed at VCC = +4.5V to +6.0V.
4.0
Serial Clock (CLK)
The Serial Clock is used to synchronize the communication between a master device and the 93LC76/86.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be continued
anytime with respect to clock HIGH time (TCKH) and
clock LOW time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
READY
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions of
CLK) must be provided. These clock cycles are
required to clock in all opcode, address, and data bits
before an instruction is executed (see Table 1-4 through
Table 1-7 for more details). CLK and DI then become
don't care inputs waiting for a new start condition to be
detected.
Note:
4.3
CS must go LOW between consecutive
instructions, except when performing a
sequential read (Refer to Section 3.1 for
more detail on sequential reads).
Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
4.4
Data Out (DO)
Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY status information is available when CS is high. It will be
displayed until the next start bit occurs as long as CS
stays high.
4.5
Organization (ORG)
When ORG is connected to VCC, the x16 memory organization is selected. When ORG is tied to VSS, the x8
memory organization is selected. There is an internal
pull-up resistor on the ORG pin that will select x16 organization when left unconnected.
4.6
Program Enable (PE)
This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is floated
or tied to VCC, the device can be programmed. If the PE
pin is tied to VSS, programming will be inhibited. There
is an internal pull-up on this device that enables programming if this pin is left floating.
 1996 Microchip Technology Inc.
Preliminary
DS21131C-page 9
93LC76/86
NOTES:
DS21131C-page 10
Preliminary
 1996 Microchip Technology Inc.
93LC76/86
93LC76/86 Product Identification System
To order or obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales
office.
93LC76/86
–
/P
Package:
Temperature
Range:
Device:
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
Blank = 0°C to +70°C
I = -40°C to +85°C
93LC76/86
93LC76T/86T
Microwire Serial EEPROM
Microwire Serial EEPROM (Tape and Reel)
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
DS21131C-page 11
Preliminary
 1996 Microchip Technology Inc.
WORLDWIDE SALES & SERVICE
AMERICAS
ASIA/PACIFIC
EUROPE
Corporate Office
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508 480-9990 Fax: 508 480-8575
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972 991-7177 Fax: 972 991-8588
Dayton
Microchip Technology Inc.
Suite 150
Two Prestige Place
Miamisburg, OH 45342
Tel: 513 291-1654 Fax: 513 291-9175
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 714 263-1888 Fax: 714 263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279 Fax: 905 405-6253
Hong Kong
Microchip Technology
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431
India
Microchip Technology
No. 6, Legacy, Convent Road
Bangalore 560 025 India
Tel: 91 80 526 3148 Fax: 91 80 559 9840
Korea
Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
Shanghai
Microchip Technology
Unit 406 of Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, Peoples Republic of China
Tel: 86 21 6275 5700
Fax: 011 86 21 6275 5060
Singapore
Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
Taiwan, R.O.C
Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139
United Kingdom
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 1628 850303 Fax: 44 1628 850178
France
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: 39 39 6899939 Fax: 39 39 689 9883
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: 81 45 471 6166 Fax: 81 45 471 6122
11/7/96
All rights reserved.  1996, Microchip Technology Incorporated, USA. 11/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21131C-page 12
Preliminary
 1996 Microchip Technology Inc.