ICS95V857 Integrated Circuit Systems, Inc. 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD VDD CLK_INT CLK_INC VDD AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND Product Description/Features: • Low skew, low jitter PLL clock driver • 1 to 10 differential clock distribution (SSTL_2) • Feedback pins for input to output synchronization • PD# for power management • Spread Spectrum-tolerant inputs • Auto PD when input signal removed Specifications: • Meets PC3200 Class A+ specification for DDR-I 400 support • Covers all DDRI speed grades 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS95V857 Pin Configuration Recommended Application: • DDR Memory Modules / Zero Delay Board Fan Out • Provides complete DDR registered DIMM solution with ICSSSTVF16857, ICSSSTVF16859 or ICSSSTV32852 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD FB_OUTC FB_OUTT GND CLKC8 CLKT8 VDD CLKT9 CLKC9 GND 48-Pin TSSOP/TVSOP Switching Characteristics: • CYCLE - CYCLE jitter: <50ps • OUTPUT - OUTPUT skew: <40ps • Period jitter: ±30ps 6.10 mm Body, 0.50 mm Pitch = TSSOP 4.40 mm Body, 0.40 mm Pitch = TVSOP Block Diagram FB_OUTT FB_OUTC CLKT0 CLKC0 Functionality CLKT1 CLKC1 INPUTS OUTPUTS PLL State AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC GND H L H L H L H Bypassed/off GND H H L H L H L Bypassed/off 2.5V (nom) L L H Z Z Z Z off 2.5V (nom) L H L Z Z Z Z off 2.5V (nom) H L H L H L H on 2.5V (nom) H H L H L H L on Z Z Z Z off 2.5V (nom) X (1) <20MHz) Control PD# Logic CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 FB_INT FB_INC CLK_INC CLK_INT CLKT5 CLKC5 PLL CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 0674U—01/27/09 ICS95V857 Pin Configuration 1 2 3 4 5 6 A B C D E F G H J K 56-Ball BGA Top View 1 CLKT0 CLKC1 GND CLKT2 VDD CLK_INT VDD AGND CLKC3 CLKT4 2 CLKC0 CLKT1 GND CLKC2 VDD CLK_INC AVDD GND CLKT3 CLKC4 3 GND VDD NC NC NB NB NC NC VDD GND 4 GND VDD NC NC NB NB NC NC VDD GND 5 6 CLKC5 CLKT5 CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INC FB_INT FB_OUTC VDD GND FB_OUTT CLKT8 CLKC8 CLKC9 CLKT9 CLKC1 CLKT1 VDD CLKT0 CLKC0 CLKC5 CLKT5 VDD CLKT6 CLKC6 A B C D E F G H J K 40 GND CLKC2 CLKT2 VDD CLK_INT CLK_INC VDD AVDD AGND GND 31 30 1 ICS95V857 10 21 20 CLKC3 CLKT3 VDD CLKT4 CLKC4 CLKC9 CLKT9 VDD CLKT8 CLKC8 11 40-Pin MLF 0674U—01/27/09 2 CLKC7 CLKT7 VDD PD# FB_INT FB_INC VDD VDD FB_OUTC FB_OUTT ICS95V857 Pin Descriptions PIN NAME TYPE DESCRIPTION VDD PWR Power supply, 2.5V GND PWR Ground AVDD PWR Analog power supply, 2.5V AGND PWR A n a l o g gr o u n d CLKT(9:0) OUT "Tr ue" Clock of differential pair outputs CLKC(9:0) OUT "Complementar y" clocks of differential pair outputs CLK_INC IN "Complementar y" reference clock input CLK_INT IN "True" reference clock input FB_OUTC OUT "Complementar y" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC FB_OUTT OUT "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT FB_INT IN "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error FB_INC IN "Complementar y" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error PD# IN Power Down. LVCMOS input This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels. The ICS95V857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT, FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD). When input (PD#) is low while power is applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INC, CLK_INT). The PLL to the ICS95V857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT, FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The ICS95V857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI. The ICS95V857 is characterized for operation from 0°C to 85°C, and will meet JEDEC Standard 82-1 and 82-1A Class A+ for registered DDR clock drivers. 0674U—01/27/09 3 ICS95V857 Absolute Maximum Ratings Supply Voltage (VDD & AVDD) . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V GND –0.5 V to VDD + 0.5 V 0°C to +85°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5V ± 0.2V PARAMETER Input High Current Input Low Current Operating Supply Current Output High Current SYMBOL I IH IIL I DD2.5 I DDPD I OH Output Low Current I OL VDD = 2.3V, VOUT = 1.2V I OZ VDD=2.7V, Vout=VDD or GND ±10 mA VIK VDDQ = 2.3V Iin = -18mA -1.2 V High Impedance Output Current Input Clamp Voltage High-level output voltage VOH Low-level output voltage VOL Input Capacitance1 Output Capacitance1 1 CIN COUT CONDITIONS VI = VDD or GND VI = VDD or GND CL = 0pf @ 200MHz CL = 0pf VDD = 2.3V, VOUT = 1V VDD = min to max, I OH = -1 mA VDDQ = 2.3V, I OH = -12 mA VDD = min to max I OL=1 mA VDDQ = 2.3V I OH=12 mA VI = GND or VDD VOUT = GND or VDD MIN 5 TYP MAX -18 -32 UNITS µA µA mA µA mA 148 5 170 100 26 35 mA VDDQ - 0.1 V 1.7 V 3 3 Guaranteed by design at 220MHz, not 100% tested in production. 0674U—01/27/09 4 0.1 V 0.6 V pF pF ICS95V857 Recommended Operating Condition (see note1) TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Supply Voltage SYMBOL V DD, AVDD VDD + 0.6 UNITS V V V V V -0.3 VDD + 0.3 V 0.36 0.7 VDD + 0.6 VDD + 0.6 V V VOX VDD/2 - 0.15 VDD/2 + 0.15 V VIX VDD/2 - 0.2 VDD/2 + 0.2 V IOH -6.4 mA Low level output current IOL 5.5 mA Operating free-air temperature TA 85 °C Low level input voltage VIL High level input voltage VIH DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current CONDITIONS CLKT, CLKC, FB_INC PD# CLKT, CLKC, FB_INC PD# VIN VID DC - CLKT, FB_INT AC - CLKT, FB_INT MIN 2.3 -0.3 V DD/2 + 0.18 1.7 0 Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VT is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing. 0674U—01/27/09 5 TYP 2.5 0.4 MAX 2.7 V DD/2 - 0.18 0.7 2.1 VDD/2 ICS95V857 Timing Requirements TA = 0 - 85°C; Supply Voltage A VDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization freqop freqApp o 2.5V+0.2V @ 25 C 2.5V+0.2V @ 25oC dtin UNITS 45 233 MHz 95 220 MHz 40 60 % 15 µs TSTAB Switching Characteristics (see note 3) PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate SYMBOL CONDITION MIN TYP MAX UNITS tPLH1 CLK_IN to any output 3.5 ns tPLL1 CLK_IN to any output 3.5 ns tEN tdis PD# to any output PD# to any output 100MHz to 200MHz 100MHz to 200MHz 3 3 ns ns ps ps V/ns V/ns ps ps ps Tjit (per) t(jit_hper) tsl(i) tsl(o) Tcyc -Tcyc -30 -75 1 1 -50 -50 100MHz to 200MHz Cycle to Cycle Jitter1 Static Phase Offset 0 t(static phase offset)4 Output to Output Skew Tskew Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, where the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. 0674U—01/27/09 6 30 75 4 2 50 50 40 ICS95V857 Parameter Measurement Information VDD V(CLKC) R = 60Ω R = 60Ω VDD/2 V(CLKC) ICS95V857 GND Figure 1. IBIS Model Output Load VDD/2 C = 14 pF -V DD/2 ICS95V857 R = 10Ω Z = 60Ω SCOPE Z = 50Ω R = 50Ω V(TT) R = 10Ω Z = 60Ω Z = 50Ω R = 50Ω V(TT) C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n+1) Figure 3. Cycle-to-Cycle Jitter 0674U—01/27/09 7 ICS95V857 Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t( ) n n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset YX# YX YX, FB_OUTC YX, FB_OUTT t(SK_O) Figure 5. Output Skew YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter 0674U—01/27/09 8 t ( ) n+1 ICS95V857 Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT t (hper_n+1) t (hper_n) 1 fo t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7. Half-Period Jitter 80% 80% VID , VOD Clock Inputs and Outputs 20% 20% Rise tsl Fall tsl Figure 8. Input and Output Slew Rates 0674U—01/27/09 9 ICS95V857 In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0° 8° 0° 8° aaa -0.10 -.004 c N L E1 INDEX AREA E 1 2 D A A2 VARIATIONS A1 N -Ce 48 SEATING PLANE b D mm. MIN MAX 12.40 12.60 Reference Doc.: JEDEC Publication 95, M O-153 10-0039 aaa C 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information XXXX y G (LF) T Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Example: 95V857AGLFT 0674U—01/27/09 10 D (inch) MIN .488 MAX .496 ICS95V857 c N L E1 INDEX AREA E 1 2 α D In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 6.40 BASIC 0.252 BASIC E E1 4.30 4.50 .169 .177 0.40 BASIC 0.016 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0° 8° 0° 8° aaa -0.08 -.003 A A2 VARIATIONS A1 N -C- e SEATING PLANE b aaa C 48 D mm. MIN 9.60 D (inch) MAX 9.80 Reference Do c.: JEDEC P ublicatio n 95, M O-153 10-0037 4.40 mm. Body, 0.40 mm. pitch TSSOP (173 mil) (16 mil) Ordering Information XXXX y L (LF) T Designation for tape and reel packaging Lead Free (Optional) Package Type L = TSSOP (TVSOP) Revision Designator (will not correlate with datasheet revision) Device Type Example: 95V857ALLFT 0674U—01/27/09 11 MIN .378 MAX .386 ICS95V857 (Ref.) Seating Plane (N D -1)x e (Ref.) A1 Index Area ND & NE Even A3 N L N 1 Anvil Singulation 1 2 Top View (NE -1)x e (Ref.) E2 2 Sawn Singulation b (Ref.) A D are Even 2 E2 or E (Typ.) e 2 If N & N D E e ND & NE Odd D2 2 Thermal Base D2 0.08 C C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE ALL DIMENSIONS IN MILLIMETERS N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. 40 10 10 6.00 x 6.00 2.75 / 3.05 2.75 / 3.05 0.30 / 0.50 SYMBOL A A1 A3 b e MIN. MAX. 0.80 1.00 0 0.05 0.25 Reference 0.18 0.30 0.50 BASIC Source Reference: MLF2™SE 10-0053 Ordering Information XXXX y K (LF) T Designation for tape and reel packaging Lead Free (Optional) Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type Example: 95V857AKLFT 0674U—01/27/09 12 ICS95V857 C Seating Plane A1 Numeric Designations for Horizontal Grid b REF T 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q & S not used) D d TYP D1 - e - TYP TOP VIEW E c REF h TYP - e - TYP E1 0.12 C ALL DIMENSIONS IN MILLIMETERS D E 7.00 Bsc 4.50 Bsc T Min/Max 0.86/1.00 e 0.65 Bsc ----- BALL GRID ----HORIZ VERT 6 Max. TOTAL 10 60 d Min/Max 0.35/0.45 h Min/Max 0.15/0.21 D1 E1 5.85 Bsc 3.25 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC Publication 95, MO-205*, MO-225** 10-0055 Ordering Information XXXX y H (LF) T Designation for tape and reel packaging Lead Free (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Example: 95V857AHLFT 0674U—01/27/09 13 REF. DIMENSIONS b c 0.575 0.625 **