DATASHEET Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 9DB1200C Description Features/Benefits DB1200 Rev 2.0 Intel Yellow Cover Device • 3 selectable SMBus addresses for easy system expansion • Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread • Supports undriven differential outputs in Power Down Mode for power management. General Description The ICS9DB1200 is an Intel DB1200 Differential Buffer Specification device. This buffer provides 12 differential clocks at frequencies ranging from 100MHz to 400 MHz. The ICS9DB1200 is driven by a differential output from a CK410B+ or CK509B main clock generator. Key Specifications • • • • • • Output Features • • • • • 12 - 0.7V current-mode differential output pairs. Supports zero delay buffer mode and fanout mode. Bandwidth programming available. 100-400 MHz operation in PLL mode 33-400 MHz operation in Bypass mode Output cycle-cycle jitter < 50ps. Output to output skew: 50ps Phase jitter: PCIe Gen2 < 3.1ps rms Phase jitter: QPI < 0.5ps rms 64-pin TSSOP Package Available in RoHS compliant packaging Functional Block Diagram 12 OE_(11:0)# SPREAD COMPATIBLE PLL SRC_IN SRC_IN# M U X 12 DIF(11:0)) FS(2:0) HIGH_BW# BYPASS#/PLL VTTPWRGD#/PD CONTROL LOGIC ADR_SEL SMBDAT SMBCLK IREF IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 1 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 9DB1200C VDD DIF_IN DIF_IN# GND OE0# DIF_0 DIF_0# VDD GND OE1# DIF_1 DIF_1# OE2# DIF_2 DIF_2# GND VDD OE3# DIF_3 DIF_3# OE4# DIF_4 DIF_4# VDD GND OE5# DIF_5 DIF_5# **ADR_SEL HIGH_BW# FS2 SMBCLK VDDA AGND IREF FS0 OE11# DIF_11 DIF_11# VDD GND OE10# DIF_10 DIF_10# OE9# DIF_9 DIF_9# GND VDD OE8# DIF_8 DIF_8# OE7# DIF_7 DIF_7# VDD GND OE6# DIF_6 DIF_6# VTTPWRGD#/PD BYPASS#/PLL FS1 SMBDAT 64-TSSOP ** Indicates 120K ohm Pulldown Frequency Select Table FSL2 FSL1 FSL0 B0b2 B0b1 B0b0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Input MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 Hi-Z SMBus Address Selection (Pin 29) ADR_SEL Voltage SMBus Adr (Wr/Rd) Low <0.8V DC/DD Mid 1.2<Vin<1.8V D6/D7 High Vin > 2.0V D4/D5 DIF_x; MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 Hi-Z Power Groups Pin Number VDD GND 1 4 8, 17, 24, 41, 9, 16, 25, 40, 48, 57 49, 56 N/A 63 Description DIF_IN/DIF_IN# DIF(11:0) IREF Analog VDD & GND 64 63 for PLL core Note: Please treat pin 1 as an analog VDD. 1. FSL(2:0) are 3.3V tolerant low-threshold inputs. Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 2 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Pin Description PIN # PIN NAME TYPE DESCRIPTION PWR IN IN PWR Power supply, nominal 3.3V 0.7 V Differential TRUE input 0.7 V Differential Complementary Input Ground pin. Active low input for enabling DIF pair 0. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. Active low input for enabling DIF pair 1. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 2. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Ground pin. Power supply, nominal 3.3V Active low input for enabling DIF pair 3. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 4 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. Active low input for enabling DIF pair 5. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output This tri-level input selects one of 3 SMBus addresses. See the SMBus Address Select Table for the addresses. 3.3V input for selecting PLL Band Width 0 = High, 1= Low Frequency select pin. Clock pin of SMBUS circuitry, 5V tolerant 1 2 3 4 VDD DIF_IN DIF_IN# GND 5 OE0# 6 7 8 9 DIF_0 DIF_0# VDD GND 10 OE1# 11 12 DIF_1 DIF_1# 13 OE2# 14 15 16 17 DIF_2 DIF_2# GND VDD 18 OE3# 19 20 DIF_3 DIF_3# 21 OE4# 22 23 24 25 DIF_4 DIF_4# VDD GND 26 OE5# 27 28 DIF_5 DIF_5# 29 **ADR_SEL IN 30 HIGH_BW# IN 31 32 FS2 SMBCLK IN IN IN OUT OUT PWR PWR IN OUT OUT IN OUT OUT PWR PWR IN OUT OUT IN OUT OUT PWR PWR IN OUT OUT IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 3 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Pin Description PIN # PIN NAME TYPE 33 34 SMBDAT FS1 I/O IN 35 BYPASS#/PLL IN 36 VTTPWRGD#/PD IN 37 38 DIF_6# DIF_6 39 OE6# 40 41 42 43 GND VDD DIF_7# DIF_7 44 OE7# 45 46 DIF_8# DIF_8 47 OE8# 48 49 50 51 VDD GND DIF_9# DIF_9 52 OE9# 53 54 DIF_10# DIF_10 55 OE10# 56 57 58 59 GND VDD DIF_11# DIF_11 60 OE11# IN 61 FS0 IN 62 IREF OUT 63 64 AGND VDDA PWR PWR OUT OUT IN PWR PWR OUT OUT IN OUT OUT IN PWR PWR OUT OUT IN OUT OUT IN PWR PWR OUT OUT DESCRIPTION Data pin of SMBUS circuitry, 5V tolerant 3.3V Frequency select latched input pin. Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode VTTPWRGD# is an active low input used to sample latched inputs and allow the device to Power Up. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks and PLLs are stopped. 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 6. 1 = tri-state outputs, 0 = enable outputs Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 7. 1 = tri-state outputs, 0 = enable outputs 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 8. 1 = tri-state outputs, 0 = enable outputs Power supply, nominal 3.3V Ground pin. 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 9. 1 = tri-state outputs, 0 = enable outputs 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 10. 1 = tri-state outputs, 0 = enable outputs Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 11. 1 = tri-state outputs, 0 = enable outputs 3.3V Frequency select latched input pin. This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Analog Ground pin for Core PLL 3.3V power for the PLL core. IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 4 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Absolute Max Symbol VDDA VDD VIL VIH Parameter 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Ts Tambient Tcase Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model ESD prot Min Max 4.6 4.6 GND-0.5 VDD+0.5V -65 0 150 70 115 2000 Units V V V V ° C °C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 3.3 V +/-5% 2 V DD + 0.3 V 1 Input Low Voltage Input High Current VIL I IH 3.3 V +/-5% V IN = V DD VIN = 0 V; Inputs with no pull-up resistors GND - 0.3 -5 0.8 5 V uA 1 1 -5 uA 1 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 uA 1 Operating Supply Current IDD3.3OP Full Active, CL = Full load; 375 mA 1 Powerdown Current IDD3.3PD FiPLL FiBYPASS Lpin CIN COUT all differential pairs tri-stated PLL Mode Bypass Mode 24 400 400 7 5 6 2 2 4 1.4 mA MHz MHz nH pF pF dB dB MHz MHz 1 1 1 1 1 1 1 1 1 1 1.8 ms 1,2 30 33 kHz 1 4 12 cycles 1,3 300 us 1,3 5 5 ns ns 1 1 IIL1 Input Low Current Input Frequency Pin Inductance Capacitance PLL Jitter Peaking jPEAK PLL Bandwidth BW Clk Stabilization TSTAB Modulation Frequency f MOD OE# Latency tLATOE# Tdrive_PD t DRVPD Tfall Trise tF tR Logic Inputs Output pin capacitance Peaking when HIGH_BW#=0 Peaking when HIGH_BW#=1 PLL Bandwidth when HIGH_BW#=0 PLL Bandwidth when HIGH_BW#=1 From V DD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Triangular Modulation DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD de-assertion Fall time of OE# Rise time of OE# TYP 100 33 1.5 2 0.7 1.5 1.5 3 1 MAX UNITS NOTES 1 Guaranteed by design and characterization, not 100% tested in production. See timing diagrams for timing requirements. 3 Time from deassertion until outputs are >200 mV 2 IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 5 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Electrical Characteristics - Clock Input Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Input High Voltage DIF_IN Input Low Voltage DIF_IN Input Common Mode Voltage - DIF_IN CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) VIHDIF VILDIF MIN TYP MAX UNITS NOTES 600 800 1150 mV 1 VSS - 300 0 300 mV 1 VCOM Common Mode Input Voltage 300 1000 mV 1 Input Amplitude - DIF_IN VSWING Peak to Peak value 300 1450 mV 1 Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2 Input Leakage Current I IN -5 5 uA 1 Input Duty Cycle dtin VIN = VDD , VIN = GND Measurement from differential wavefrom 45 55 % 1 Input Jitter - Cycle to Cycle J DIFIn 0 125 ps 1 Differential Measurement 1 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing min centered around differential zero 2 Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, RREF=475Ω PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. 660 1 MAX VLow Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Rise Time Fall Time Rise Time Variation Fall Time Variation Vovs Vuds Vcross(abs) d-Vcross ppm tr tf d-tr d-tf Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V 175 175 Duty Cycle dt3 Measurement from differential wavefrom 45 Ω 850 -150 IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 6 1 1,3 150 1150 -300 250 1,3 550 140 0 700 700 125 125 mV mV ppm ps ps ps ps 1 1 1 1 1,2 1 1 1 1 55 % 1 ps ps ps ps ps 1 1 1 1,5 1,5 Bypass Mode, VT = 50% 2.5 4.5 PLL Mode VT = 50% -250 250 VT = 50% 50 Skew, Output to Output PLL mode 50 tjcyc-cyc Jitter, Cycle to cycle 50 BYPASS mode as additive jitter 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK509B accuracy requirements. The 9DB1200 itself does not contribute to ppm error. 3 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 4 Applies to Bypass Mode Only 5 Measured from differential waveform Skew, Input to Output UNITS NOTES mV Voltage Low tpdBYP tpdPLL tsk3 TYP mV 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Electrical Characteristics - Phase Jitter PARAMETER MAX UNITS 35 86 ps 1,2,3 1.1 3 ps rms 1,2 2.3 3.1 ps rms 1,2 0.25 0.5 ps rms Notes on Phase Jitter: 1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production. 2 Device driven by 932S421BGLF or equivalent 3 BER of 1E-9 4 Measured at 133MHz using CSI_133_MHZ_6_4BG_12UI template in Intel supplied Clock Jitter Tool. 2,4 tjphase CONDITIONS PCIe Gen 1 REFCLK phase jitter (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz ) PCIe Gen 2 REFCLK phase jitter (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=12 ns) Lo-band content (10kHz to 1.5MHz) PCIe Gen 2 REFCLK phase jitter (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=12 ns) Hi-band content (1.5MHz to Nyquist) QPI specs REFCLK phase jitter IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 7 MIN NOTES TYP. Jitter, Phase SYMBOL 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM DIF Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs HCSL Output Buffer Rt Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' HCSL Output Buffer Rs Rt Rt L3' IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 8 PCI Express Add-in Board REF_CLK Input L3 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 9 PCIe Device REF_CLK Input 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM General SMBus serial interface information for the 9DB1200C How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address DC(h) WRite WR Controller (host) will send start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address DC(h) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address DD(h) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK P X Byte ACK stoP bit Byte N + X - 1 N P Not acknowledge stoP bit Note: Addresses show assumes pin 29 is low. IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 10 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM SMBus Table: Frequency Select Register Byte 0 Pin # Name HIGH_BW# Bit 7 BYPASS#/PLL Bypass Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 FS2 Bit 2 FS1 Bit 1 FS0 Bit 0 Control Function High or Low BW (non-PLL Mode) or PLL Mode Reserved Reserved Reserved Frequency Select 2 Frequency Select 1 Frequency Select 0 SMBus Table: Output Control Register Byte 1 Pin # Name 43,42 DIF_7 Bit 7 38,37 DIF_6 Bit 6 27,28 DIF_5 Bit 5 22,23 DIF_4 Bit 4 19,20 DIF_3 Bit 3 14,15 DIF_2 Bit 2 11,12 DIF_1 Bit 1 6,7 DIF_0 Bit 0 Control Function Output Control (Disable = Output Control (Disable = Output Control (Disable = Output Control (Disable = Output Control (Disable = Output Control (Disable = Output Control (Disable = Output Control (Disable = SMBus Table: Output Control Register Byte 2 Pin # Name Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 58,59 DIF_11 Bit 3 53,54 DIF_10 Bit 2 50,51 DIF_9 Bit 1 45,46 DIF_8 Bit 0 Control Function Reserved Reserved Reserved Reserved Output Control (Disable = Output Control (Disable = Output Control (Disable = Output Control (Disable = SMBus Table: Output Enable Readback Byte 3 Pin # Name 43,42 OE7# Bit 7 38,37 OE6# Bit 6 27,28 OE5# Bit 5 OE4# 22,23 Bit 4 19,20 OE3# Bit 3 14,15 OE2# Bit 2 11,12 OE1# Bit 1 6,7 OE0# Bit 0 Control Function OE# Pin Readback OE# Pin Readback OE# Pin Readback OE# Pin Readback OE# Pin Readback OE# Pin Readback OE# Pin Readback OE# Pin Readback IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 11 Type RW RW RW RW RW RW RW RW 0 1 High BW Low BW Bypass PLL Reserved Reserved Reserved See FS Table Hi-Z) Hi-Z) Hi-Z) Hi-Z) Hi-Z) Hi-Z) Hi-Z) Hi-Z) Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 0 Hi-Z) Hi-Z) Hi-Z) Hi-Z) PWD Latch Latch X X X Latch Latch Latch 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 Type RW RW RW RW RW RW RW RW 1 Reserved Reserved Reserved Reserved Disable Enable Disable Enable Disable Enable Disable Enable PWD 0 0 0 0 1 1 1 1 Type R R R R R R R R 0 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled PWD X X X X X X X X 1 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM SMBus Table: Output Enable Readback Pin # Name Byte 4 Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 58,59 OE11# Bit 3 53,54 OE10# Bit 2 50,51 OE9# Bit 1 45,46 OE8# Bit 0 Control Function Reserved Reserved Reserved Reserved Output Control (Disable = Output Control (Disable = Output Control (Disable = Output Control (Disable = Hi-Z) Hi-Z) Hi-Z) Hi-Z) Type R R R R R R R R 0 1 Reserved Reserved Reserved Reserved Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled PWD 0 0 0 0 X X X X Note: For an output to be enabled, BOTH the Output Enable Bit and the OE# pin must be enabled. This means that the Output Enable Bit must be '1' and the corresponding OE# pin must be '0'. SMBus Table: Vendor & Revision ID Register Byte 5 Pin # Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 SMBus Table: DEVICE ID Byte 6 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Byte Count Register Byte 7 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Type R R R R R R R R 0 - 1 - PWD X X X X 0 0 0 1 Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 Type RW RW RW RW RW RW RW RW 0 1 PWD 1 1 0 0 0 0 0 0 Control Function Type RW RW RW RW RW RW RW RW Control Function REVISION ID VENDOR ID Writing to this register configures how many bytes will be read back. IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 12 Device ID is C0 Hex 0 - 1 - PWD 0 0 0 0 0 1 1 1 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM c N SYMBOL L E1 INDEX AREA A A1 A2 b c D E E1 e L N α aaa E 1 2 a D VARIATIONS A A2 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° 8° -0.10 -.004 N A1 64 D mm. MIN 16.90 D (inch) MAX 17.10 MIN .665 MAX .673 -Ce Reference Doc.: JEDEC Publication 95, MO-153 SEATING PLANE b 10-0039 aaa C Ordering Information Part / Order Number 9DB1200CGLF 9DB1200CGLFT Shipping Packaging Tubes Tape and Reel Package 64-pin TSSOP 64-pin TSSOP Temperature 0 to +70°C 0 to +70°C “LF” after the package code denotes the Pb-Free configuration, RoHS compliant. IDT® Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM 13 1414F—06/30/10 9DB1200C Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM Revision History Rev. A B C D E F Issue Date Description 1. Updated SMBus Serial Interface Information. 12/18/2007 2. Release to Final. 4/7/2008 Added Input Clock Parameters 1. Updated Phase Jitter Numbers 2. Added PLL BW and jitter peaking specs 3. Added input to output delay specs 8/28/2008 5. Updated stabilization time to 1.8ms from 1.0ms 1. Corrected pin number references in SMBus Bytes 1 and 3 9/15/2009 2. Added typical values to phase jitter table. 11/4/2009 Changed CLK Stabilization spec from 1.0 to 1.8 ms 7/1/2010 Corrected power groups table for input clock, Page # 10 6 Various 5 2 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 14