IDT 9FG1901HKLFT

DATASHEET
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Description
Features/Benefits
The 9FG1901H follows the Intel DB1900G Differential Buffer
Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock.
A differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H
can provide outputs up to 400MHz.
•
•
Key Specifications
•
•
•
•
•
•
•
•
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(18:17) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
VDDA controlled power down mode
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew across all outputs in 1:1 mode < 150ps
Functional Block Diagram
OE_17_18#
OE(16:5)#,
OE_01234#
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
STOP
LOGIC
17
DIF(18:17)
13
CLK_IN
CLK_IN#
DIF(16:0)
HIGH_BW#
FS_A_410
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
1
DIF_14
DIF_14#
OE15#
DIF_15
DIF_15#
OE16#
DIF_16
DIF_16#
VDD
GND
DIF_17
DIF_17#
DIF_18
DIF_18#
OE17_18#
CLK_IN
SMB_A2_PLLBYP#
Pin Configuration
CLK_IN#
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
IREF
1
GNDA
2
VDDA/PD#
3
HIGH_BW#
4
FS_A_410
5
DIF_0
6
DIF_0#
7
DIF_1
8
DIF_1#
9
54 OE14#
53 DIF_13#
52 DIF_13
51 OE13#
50 DIF_12#
49 DIF_12
48 OE12#
47 VDD
46 GND
9FG1901
GND 10
45 DIF_11#
44 DIF_11
43 OE11#
VDD 11
DIF_2 12
42 DIF_10#
41 DIF_10
40 OE10#
DIF_2# 13
DIF_3 14
DIF_3# 15
39 DIF_9#
38 DIF_9
37 OE9#
DIF_4 16
DIF_4# 17
OE_01234# 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SMB_A1
SMB_A0
DIF_8#
DIF_8
OE8#
DIF_7#
DIF_7
OE7#
GND
VDD
DIF_6#
DIF_6
OE6#
DIF_5#
DIF_5
OE5#
SMBDAT
SMBCLK
72-pin MLF
Power Groups
Functionality at Power Up (PLL Mode)
1
FS_A_410
1
0
CLK_IN
(CPU FSB)
MHz
100 <= CLK_IN < 200
200<= CLK_IN <= 400
Pin Number
VDD
GND
3
2
11,27,47,63 10,28,46,64
DIF(18:0)
MHz
CLK_IN
CLK_IN
Description
Main PLL, Analog
DIF clocks
1. FS_A_410 is a low-threshold input. Please see the VIL_FS
and VIH_FS specifications in the Input/Supply/Common Output
Parameters Table for correct values.
Power Down Functionality
INPUTS
OUTPUTS
PLL State
VDDA/PD# CLK_IN/CLK_IN# DIF DIF#
Running
3.3V (NOM)
Running
ON
Hi-Z
GND
X
OFF
Functionality Note
It is recommended that Byte 2, bit 6 be toggled from 1 to 0
and back to 1, the first time VDDA is applied. This ensures
proper initialization of the device.
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
2
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Pin Description
PIN #
PIN NAME
PIN TYPE
1
IREF
OUT
2
GNDA
PWR
3
VDDA/PD#
PWR
4
HIGH_BW#
IN
5
FS_A_410
IN
6
7
8
9
10
11
12
13
14
15
16
17
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
18
OE_01234#
IN
19
20
SMBCLK
SMBDAT
IN
I/O
21
OE5#
IN
22
23
DIF_5
DIF_5#
24
OE6#
25
26
27
28
DIF_6
DIF_6#
VDD
GND
29
OE7#
30
31
DIF_7
DIF_7#
32
OE8#
33
34
35
36
DIF_8
DIF_8#
SMB_A0
SMB_A1
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
IN
DESCRIPTION
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core that also functions as Power Down. Collapsing
this power supply places the device in Power Down mode.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
3.3V tolerant low threshold input for CPU frequency selection. This pin
requires CK410 FSA. Refer to input electrical characteristics for Vil_FS and
Vih_FS threshold values.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
SMBus address bit 0 (LSB)
SMBus address bit 1
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
3
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Pin Description (continued)
PIN #
PIN NAME
PIN TYPE
37
OE9#
IN
38
39
DIF_9
DIF_9#
OUT
OUT
40
OE10#
IN
41
42
DIF_10
DIF_10#
43
OE11#
44
45
46
47
DIF_11
DIF_11#
GND
VDD
48
OE12#
49
50
DIF_12
DIF_12#
51
OE13#
52
53
DIF_13
DIF_13#
54
OE14#
55
56
DIF_14
DIF_14#
57
OE15#
58
59
DIF_15
DIF_15#
60
OE16#
61
62
63
64
65
66
67
68
DIF_16
DIF_16#
VDD
GND
DIF_17
DIF_17#
DIF_18
DIF_18#
69
OE17_18#
IN
70
71
CLK_IN
CLK_IN#
IN
IN
72
SMB_A2_PLLBYP#
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
DESCRIPTION
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 13.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 14.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 15.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 16.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pairs 17 and 18.
1 = tri-state outputs, 0 = enable outputs
True Input for differential reference clock.
Complement Input for differential reference clock.
SMBus address bit 2. When Low, the part operates as a fanout buffer with the
PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with
the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
4
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
9FG1901 Programmable Gear Ratios
FS_A_410
Bit 3
Bit 2
Bit 1
Bit 0
SMBus
Byte 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input Output Gear Ratio
(m)
(n)
(n/m)
Input (CPU FSB) and Output
Frequencies (MHz)
200.0
3
5
12
2
5
8
3
4
6
1
5
4
3
2
3
1
1
2
5
1
3
5
2
3
5
1
6
5
4
3
5
2
0.333
0.400
0.417
0.500
0.600
0.625
0.667
0.750
0.833
1.000
1.200
1.250
1.333
1.500
1.667
2.000
266.7
320.0
333.3
400.0
66.7
88.9
106.7
111.1 133.3
80.0 106.7
128.0
133.3 160.0
83.3 111.1
133.3
138.9 166.7
100.0 133.3
160.0
166.7 200.0
120.0 160.0
192.0
200.0 240.0
125.0 166.7
200.0
208.3 250.0
133.3 177.8
213.3
222.2 266.7
150.0 200.0
240.0
250.0 300.0
166.7 222.2
266.7
277.8 333.3
200.0 266.7
320.0
333.3 400.0
240.0 320.0
384.0
400.0
NA
250.0 333.3
400.0
NA
NA
266.7 355.6
NA
NA
NA
300.0 400.0
NA
NA
NA
333.3
NA
NA
NA
NA
400.0
NA
NA
NA
NA
CLK IN (CPU FSB) Frequency (MHz)
100 133.33
160
166.67
1 0 0 0 0
3
1
0.333
1 0 0 0 1
5
2
0.400
NA
53.3
64.0
66.7
1 0 0 1 0
12
5
0.417
NA
55.6
66.7
69.4
1 0 0 1 1
2
1
0.500
50.0
66.7
80.0
83.3
1 0 1 0 0
5
3
0.600
60.0
80.0
96.0
100.0
1 0 1 0 1
8
5
0.625
62.5
83.3
100.0
104.2
1 0 1 1 0
3
2
0.667
66.7
88.9
106.7
111.1
1 0 1 1 1
5
4
0.800
80.0 106.7
128.0
133.3
1 1 0 0 0
6
5
0.833
NA
111.1
133.3
138.9
1
1
1.000
100.0 133.3
160.0
166.7
1 1 0 0 1
1 1 0 1 0
5
6
1.200
120.0 160.0
192.0
200.0
1 1 0 1 1
4
5
1.250
125.0 166.7
200.0
208.3
1 1 1 0 0
3
4
1.333
133.3 177.8
213.3
222.2
1 1 1 0 1
2
3
1.500
150.0 200.0
1 1 1 1 0
3
5
1.667
166.7 222.2
266.7
277.8
1 1 1 1 1
1
2
2.000
200.0 266.7
320.0
333.3
Note: Lines in BOLD are Power-up defaults for FS_A_410 = 0 and 1 respectively.
Shaded areas are shown for reference only and device operation is not guaranteed
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
5
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
9FG1901 SMBus Address Mapping
when using CK410B+, 9FG1201, and 9DB401/801
PLL BYPASS MODE
SMB_A2_PLLBYP# = 0
SMB_A(2:0) = 000
SMB Adr: D0
9FG1901
(DB1900G)
SMB_A(2:0) = 001
SMB Adr: D2
9FG1901
(DB1900G)
SMB_A(2:0) = 010
SMB Adr: D4
9FG1901
(DB1900G)
SMB_A(2:0) = 011
SMB Adr: D6
9FG1901
(DB1900G)
SMB_A(2:0) = 100
SMB Adr: D8
9FG1901
(DB1900G)
PLL ZDB MODE
SMB_A2_PLLBYP# = 1
SMB_A(2:0) = 101
SMB Adr: DA
9FG1901
(DB1900G)
SMB_A(2:0) = 110
SMB Adr: DC
9FG1901
(DB1900G)
SMB_A(2:0) = 111
SMB Adr: DE
9FG1901
(DB1900G)
SMB_A(2:0) = 000
SMB Adr: D0
9FG1201/2
(DB1200G)
OR
SMB_A(2:0) = 001
SMB Adr: D2
9FG1201/2
(DB1200G)
OR
OR
SMB Adr: D2
9324201
(CK410B+)
OR
SMB Adr: DC
9DB401/801
(DB400/800)
SMB_A(2:0) = 010
SMB Adr: D4
9FG1201/2
(DB1200G)
OR
SMB_A(2:0) = 011
SMB Adr: D6
9FG1201/2
(DB1200G)
OR
SMB_A(2:0) = 100
SMB Adr: D8
9FG1201/2
(DB1200G)
OR
SMB_A(2:0) = 101
SMB Adr: DA
9FG1201/2
(DB1200G)
OR
SMB_A(2:0) = 110
SMB Adr: DC
9FG1201/2
(DB1200G)
OR
SMB_A(2:0) = 111
SMB Adr: DE
9FG1201/2
(DB1200G)
OR
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
6
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
General SMBus serial interface information for the 9FG1901H
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D0 (h)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D0(h)*
WR
WRite
Controller (host) will send start bit.
Controller (host) sends the write address D0 (h)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D1 (h)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address D0(h)*
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D1(h)*
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
* Note: See SMBus Address Mapping (page 6), for programming SMBus Read/Write Address
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
7
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
SMBusTable: FSB Frequency Select Register
Byte 0
Pin #
Name
Control Function
DIF(16:0)
GRSEL_17
Group of 17 gear ratio select
Bit 7
DIF(18:17)
GRSEL_2
Group of 2 gear ratio select
Bit 6
Reserved
Bit 5
FS_A_410
Latched
Input
Bit 4
FSBG_3
FSB Gear Ratio FS_3
Bit 3
FSBG_2
FSB Gear Ratio FS_2
Bit 2
FSBG_1
FSB Gear Ratio FS_1
Bit 1
FSBG_0
FSB Gear Ratio FS_0
Bit 0
SMBusTable: Output Control Register
Byte 1
Pin #
Name
DIF_7
Bit 7
DIF_6
Bit 6
DIF_5
Bit 5
DIF_4
Bit 4
DIF_3
Bit 3
DIF_2
Bit 2
DIF_1
Bit 1
DIF_0
Bit 0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
0
RW Gear Ratio
RW Gear Ratio
RW
See ICS9FG1901
RW
RW Programmable Gear Ratios
Table
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SMBusTable: Output and PLL BW Control Register
Byte 2
Pin #
Name
Control Function
Type
0
see note
PLL_BW# adjust
RW
High BW
Bit 7
see note
BYPASS# test mode / PLL
RW
Bypass
Bit 6
DIF_13
Output Control
RW
Hi-Z
Bit 5
DIF_12
Output Control
RW
Hi-Z
Bit 4
DIF_11
Output Control
RW
Hi-Z
Bit 3
DIF_10
Output Control
RW
Hi-Z
Bit 2
DIF_9
Output Control
RW
Hi-Z
Bit 1
DIF_8
Output Control
RW
Hi-Z
Bit 0
Note: Bit 7 is wired OR to the HIGH_BW# input, any 0 selects High BW
Note: Bit 6 is wired OR to the SMB_A2_PLLBYP# input, any 0 selects Fanout Bypass mode
SMBusTable: Output Enable Readback Register
Byte 3
Pin #
Name
Control Function
Readback
OE9#
Input
Bit 7
Readback - OE8# Input
Bit 6
Readback - OE7# Input
Bit 5
Readback - OE6# Input
Bit 4
Readback - OE5# Input
Bit 3
Readback - OE_01234# Input
Bit 2
8
Readback - HIGH_BW# In
Bit 1
72
Readback - SMB_A2_PLLBYP# In
Bit 0
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1
1:1
1:1
Type
R
R
R
R
R
R
R
R
PWD
1
1
X
Latch
x
0
x
1
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
1
Low BW
PLL
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
1
PWD
X
X
X
X
X
X
X
X
0
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Readback
1386A - 02/02/10
8
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
SMBusTable: Output Enable Readback Register
Byte 4
Pin #
Name
Control Function
Readback - OE17_18# Input
69
Bit 7
60
Readback - OE16# Input
Bit 6
57
Readback - OE15# Input
Bit 5
Readback - OE14# Input
54
Bit 4
51
Readback - OE13# Input
Bit 3
48
Readback - OE12# Input
Bit 2
43
Readback - OE11# Input
Bit 1
40
Readback - OE10# Input
Bit 0
Type
R
R
R
R
R
R
R
R
0
SMBusTable: Vendor & Revision ID Register
Byte 5
Pin #
Name
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
-
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Type
RW
RW
RW
Writing to this register configures
RW
how many bytes will be read
RW
back.
RW
RW
RW
0
-
SMBusTable: DEVICE ID
Byte 6
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SMBusTable: Byte Count Register
Byte 7
Pin #
Name
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
REVISION ID
VENDOR ID
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Control Function
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1
PWD
X
X
X
X
X
X
X
X
1
-
PWD
X
X
X
X
0
0
0
1
1
PWD
1
0
0
1
0
0
0
1
1
-
PWD
0
0
0
0
0
1
1
1
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1386A - 02/02/10
9
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
SMBusTable: Control Pin Readback Register
Byte 8
Pin #
Name
Control Function
5
Readback - FS_A_410
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
DIF_18
Output Control
Bit 4
DIF_17
Output Control
Bit 3
DIF_16
Output Control
Bit 2
DIF_15
Output Control
Bit 1
DIF_14
Output Control
Bit 0
SMBusTable: 1:1 PLL Operating Set Point Register
Byte 9
Pin #
Name
Control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Frequency Select C
Bit 2
Frequency Select B
Bit 1
FS_A_410
Bit 0
Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
R
0
1
RW
RW
RW
RW
RW
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Enable
Enable
Enable
Enable
Enable
Type
0
1
Readback
PWD
X
X
X
1
1
1
1
1
PWD
0
0
0
0
0
RW
x
See ICS9FG1901H 1:1 PLL
RW
1
Programming Table
RW
Latch
9FG1901H 1:1 PLL Programming
Byte 9,
bit 2
FSC
Byte 9,
bit 1
FSB
Byte 9,
bit 0
FS_A_410
1
0
1
0
0
1
0
1
1
0
1
0
0
0
0
1
0
0
1
1
1
0
1
CLK_IN
1:1 DIF
(CPU FSB)
Outputs
MHz
MHz
100.00
100.00
133.33
133.33
166.67
166.67
200.00
200.00
266.67
266.67
333.33
333.33
400.00
400.00
Reserved
Notes
3
3
1
3
3
3
2
Notes:FS_A_410 = 1
1. Powerup Default for FS_A_410 = 1
2. Powerup Default for FS_A_410 = 0
3. Setting the exact FSB frequency after Power is required to meet phase jitter specs.
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
10
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
VDD_A
VDD_In
GND - 0.5
GND - 0.5
VDD + 0.5V
VDD + 0.5V
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
Ts
Tambient
Tcase
ESD prot
-65
0
150
70
115
Human Body Model
MIN
TYP
MAX
2000
UNITS Notes
V
V
°
C
°C
°C
V
1
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage
VIH
3.3 V +/-5%, Except CLK_IN
2
VDD + 0.3
V
1
Input Low Voltage
Input High Current
VIL
IIH
VSS - 0.3
-5
0.8
5
V
uA
1
Input Low Current
IIL1
3.3 V +/-5%, Except CLK_IN
VIN = VDD
VIN = 0 V; Inputs with no pullup resistors
Low Threshold InputHigh Voltage
VIH_FS
Low Threshold InputLow Voltage
Operating Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
VIL_FS
IDD3.3OP
IDD3.3PD
Fi
Lpin
CIN
COUT
TSTAB
Modulation Frequency
Tdrive_PD#
Tfall_Pd#
Trise_Pd#
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
VMAX
VOL
3.3 V +/-5%, Applies to
FS_A_410 pin
3.3 V +/-5%, Applies to
FS_A_410 pin
all outputs driven
all differential pairs tri-stated
VDD = 3.3 V
Logic Inputs
Output pin capacitance
From VDD Power-Up or deassertion of PD# to 1st clock
Triangular Modulation
DIF output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
Maximum input voltage
@ IPULLUP
IPULLUP
TRI2C
TFI2C
TYP
MAX
-5
uA
0.7
VDD + 0.3
V
1
VSS - 0.3
0.35
V
1
600
36
400
7
6
5
mA
mA
MHz
nH
pF
pF
1
1
3
1
1
1
1.8
ms
1
33
kHz
1
300
us
1
5
5
5.5
0.4
ns
ns
V
V
1
2
1
1
mA
1
1000
ns
1
300
ns
1
100
30
4
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
UNITS Notes
1386A - 02/02/10
11
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
CONDITIONS
MIN
Zo1
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on
single ended signal using
oscilloscope math function.
Measurement on single ended
signal using absolute value.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Vovs
Vuds
Crossing Voltage (abs)
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
Duty Cycle
dt3
tJCYC-CYC
Jitter, Cycle to cycle
tJBYP
Measurement from differential
wavefrom
PLL mode,
from differential wavefrom
Bypass mode as additive jitter
MAX
UNITS NOTES
Ω
850
1
1,3
mV
-150
150
1150
1,3
mV
1
1
550
mV
1
140
mV
1
-300
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
175
300
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
700
700
125
125
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
45
55
%
1
50
ps
1,4,5
50
ps
1,4
-300
250
Variation of crossing over all
edges
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
Notes:
1.Guaranteed by design and characterization, not 100% tested in production.
2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that the input frequency meets CK410B accuracy requirements
3.IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
4. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
5. Measured from differential cross-point to differential cross-point
6. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
12
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
CLK_IN, DIF[x:0]
tSPO_PLL
CLK_IN, DIF[x:0]
tPD_BYP
CLK_IN, DIF [x:0]
∆tSPO_PLL
CLK_IN, DIF [x:0]
∆tPD_BYP
DIF[18:17]
tSKEW_G2
DIF[16:0]
tSKEW_G17
DIF[18:0]
tSKEW_A19
DIF[18:0]
DIF[18:0]
tJPH
tSSTERROR
Description
Input-to-Output Skew in PLL mode (1:1 only),
nominal value @ 25°C, 3.3V
Input-to-Output Skew in Bypass mode (1:1 only),
nominal value @ 25°C, 3.3V
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating ranges)
Input-to-Output Skew Variation in Bypass mode
(over specified voltage / temperature operating ranges)
Output-to-Output Skew Group of 2
(Common to Bypass and PLL mode)
Output-to-Output Skew Group of 17
(Common to Bypass and PLL mode)
Output-to-Output Skew across all 19 outputs (Common to
Bypass and PLL mode - all outputs at same gear)
Differential Phase Jitter (RMS Value)
Differential Spread Spectrum Tracking Error (peak to peak)
Min
Typ
Max
Units
PLL Jitter Peaking
jpeak-hibw
(HIGH_BW# = 0)
PLL Jitter Peaking
jpeak-lobw
PLL Bandwidth
PLL Bandwidth
pllHIBW
pllLOBW
Notes
1,2,4,5,8,
12
1,2,3,5,
12
1,2,4,5,6,
10,12
1,2,3,4,5,
6,10,12
-500
270
500
ps
2.5
3.8
4.5
ns
270
|500|
ps
467
|500|
ps
10
50
ps
1,2,12
70
100
ps
1,2,12
70
150
ps
1,2,3,12
5
40
10
80
ps
ps
1,4,7,12
1,4,9,12
0
2.2
2.5
dB
11,12
(HIGH_BW# = 1)
0
1.4
2
dB
11,12
(HIGH_BW# = 0)
(HIGH_BW# = 1)
2
0.7
3.7
1.2
4
1.4
MHz
MHz
12,13
12,13
NOTES on Skew and Differential Jitter Parameters:
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2. Measured from differential cross-point to differential cross-point
3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4. This parameter is deterministic for a given device
5. Measured with scope averaging on to find mean value.
6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
7. This parameter is measured at the outputs of two separate 9FG1901H devices driven by a single CK410B+. The 9FG1901H must be set to high bandwidth.
Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target ranges of
consideration are agents with BW of 1-22MHz and 11-33MHz.
8. t is the period of the input clock
9. Differential spread spectrum tracking error is the difference in spread spectrum tracking betw een tw o 9FG1901H devices This parameter is measured at the
outputs of tw o separate 9FG1901H devices driven by a single CK410B+ in Spread Spectrum mode. The 9FG1901H must set to high bandw idth. The spread
spectrum characterisitics are : maximum of 0.5%, 30 to 33KHz modulation frequency, linear profile.
10. This parameter is an absolute value. It is not a double-sided figure.
11. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
12. Guaranteed by design and characterization, not 100% tested in production.
13. Measured at 3 db dow n or half pow er point.
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
13
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Electrical Characteristics - Phase Jitter
PARAMETER
SYMBOL
tjphPCIe1
Jitter, Phase
tjphFBD1_3.2G
tjphFBD1_4.8G
CONDITIONS
PCIe Gen 1 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54,
Td=10 ns, Ftrk=1.5 MHz )
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
MIN
TYP.
MAX UNITS
NOTES
42/41
86
ps
1,2,3,5
2.8/2.7
3
ps
(RMS)
1,2
2.4/2.1
2.5
ps
(RMS)
1,2
Notes on Phase Jitter:
See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.
2
Device driven by 932S421BGLF or equivalent
3
-12
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1
4
Hi-Bandwidth Number/Low Bandwidth Number with Spread On. Spread Off gives lower numbers.
5
Byte 9 must be properly set to meet these parameters.
1
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
14
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, route as non-coupled 50ohm trace
0.5 max
L2 length, route as non-coupled 50ohm trace
0.2 max
L3 length, route as non-coupled 50ohm trace
0.2 max
Rs
33
Rt
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
L4 length, route as coupled stripline 100ohm differential trace
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
L4 length, route as coupled stripline 100ohm differential trace
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
HCSL Output Buffer
Rt
L3'
PCI Express
Down Device
REF_CLK Input
L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
HCSL Output Buffer
Rt
L3'
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
PCI Express
Add-in Board
REF_CLK Input
L3
1386A - 02/02/10
15
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
Vp-p
Vcm
R1
R2
R3
R4
Note
0.45v
0.22v
1.08
33
150
100
100
0.58
0.28
0.6
33
78.7
137
100
0.80
0.40
0.6
33
78.7
none
100
ICS874003i-02 input compatible
0.60
0.3
1.2
33
174
140
100
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R1a
L4
R4
L4'
L2'
L1'
R1b
R2a
HCSL Output Buffer
R2b
L3'
Down Device
REF_CLK Input
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
8.2K 5%
R6a, R6b
1K 5%
Cc
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
R6a
R6b
Cc
L4
L4'
Cc
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
PCIe Device
REF_CLK Input
1386A - 02/02/10
16
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
(Ref. )
Seating Plane
(N D - 1)x e
(Ref. )
A1
Index Area
ND & NE
Even
A3
N
L
N
e (Typ.)
2 If N D & N
E
are Even
1
Anvil
Singulation
1
2
E2
OR
E
Top View
(Ref. )
2
Sawn
Singulation
b
(Ref.)
A
D
(N E - 1)x e
E2
e
Thermal
Base
D2
2
ND & NE
Odd
D2
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
C
0.08
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS
SYMBOL
N
ND
NE
DIMENSIONS (mm)
72L
72
18
18
SYMBOL
A
A1
A3
b
e
D x E BASIC
D2 MIN. / MAX.
E2 MIN. / MAX.
L MIN. / MAX.
MIN.
MAX.
0.8
1.0
0
0.05
0.25 Reference
0.18
0.3
0.50 BASIC
10.00 x 10.00
5.75
6.15
5.75
6.15
0.3
0.5
Ordering Information
Part / Order Number Shipping Packaging
9FG1901HKLF
Tubes
9FG1901HKLFT
Tape and Reel
Package
72-pin MLF
72-pin MLF
Temperature
0 to +70° C
0 to +70° C
“LF” suffix to the part numbers are the Pb-Free configuration and are RoHS compliant.
“H” is the device revision designator (will not correlate to the datasheet revision).
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
17
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Revision History
Rev.
0.1
0.2
A
Issue Date Description
9/8/2008 Initial Release
1. Updated Skews, Phase Jitter, SMBus Address Graphic
1/22/2009 2. Removed output divider table.
3. Re-ordered SMBus and electrical tables for consistency.
2/2/2010
Released to final.
Page #
Various
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Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
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+65 6 887 5505
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Prime House
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+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
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18