ALLEGRO A3949

Data Sheet
29319.47C
A3949
DMOS Full-Bridge Motor Driver
A3949SLB SOIC
Scale 1:1
N/C
1
16 N/C
MODE
2
15 VREG
PHASE
3
14 VCP
GND
4
13 GND
SLEEP
5
12 CP2
ENABLE
6
11
OUTA
7
10 OUTB
SENSE
8
9
CP1
VBB
A3949SLP TSSOP
Scale 1:1
N/C
1
16 N/C
MODE
2
15 VREG
PHASE
3
14 VCP
GND
4
13 GND
SLEEP
5
12 CP2
ENABLE
6
11 CP1
OUTA
7
10 OUTB
SENSE
8
9 VBB
Designed for PWM (pulse width modulated) control of dc motors, the
A3949 is capable of peak output currents to ±2.8 A and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM
control signals. Internal synchronous rectification control circuitry is
provided to reduce power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with hysteresis,
undervoltage monitoring of VBB and VCP , and crossover current protection.
The A3949 is supplied in a choice of two power packages, a 16-pin
plastic SOIC with a copper batwing tab (part number suffix LB), and
a low profile (1.1mm) 16-pin TSSOP (suffix LP) with exposed power
tab. Both packages are available in a lead-free version (100% matte tin
leadframe).
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage
VBB...............................................................36 V
VBB (Peak < 2 µs) ........................................38 V
Output Current, IOUT (Repetitive)1 ....................±2.8 A
Sense Voltage, VSENSE .........................................0.5 V
Logic Input Voltage, VIN ..................... –0.3 V to 7 V
Package Power Dissipation, PD
A3949SLB2 ......................................... 52ºC / W
A3949SLP3 .......................................... 34ºC / W
Operating Temperature Range
Ambient Temperature, TA.............–20°C to +85°C
Junction Temperature, TJ..................+150°C Max.
Storage Temperature, TS ..........–55°C to +150°C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set of
conditions, DO NOT exceed the specified IOUT or TJ.
2
Measured on a typical two-sided PCB with 2 in.2 copper
ground plane.
3
Measured on a JEDEC-standard "High-K" 4-layer PCB.
FEATURES
Single supply operation
Very small outline package
Low RDS(ON) outputs
Sleep function
Internal UVLO
Crossover current protection
Thermal shutdown protection
Use the following complete part numbers when ordering:
1
Part Number
Package
Description
A3949SLB
16-pin, SOIC
Copper batwing tab
A3949SLB-T
16-pin, SOIC
Copper batwing tab; Lead-free
A3949SLP
16-pin, TSSOP
Exposed thermal pad
A3949SLP-T
16-pin, TSSOP
Exposed thermal pad; Lead-free
Data Sheet
29319.47C
A3949
DMOS Full-Bridge Motor Driver
Functional Block Diagram
.22 µF
25 V
0.1 µF
VREG
CP1
Low Side
Gate Supply
CP2
VCP
Charge
Pump
OSC
0.1 µF
Load
Supply
VBB
MODE
0.1 µF
100 µF
PHASE
OUTA
Control
Logic
OUTB
ENABLE
SENSE
DMOS Full Bridge
SLEEP
GND
GND
Control Logic Table
PHASE ENABLE MODE
SLEEP
OUTA
OUTB
Function
1
1
X
1
H
L
Forward
0
1
X
1
L
H
Reverse
X
0
1
1
L
L
Brake (slow decay)
1
0
0
1
L
H
Fast decay SR*
0
0
0
1
H
L
Fast decay SR*
X
X
X
0
Hi-Z
Hi-Z
Sleep mode
* To prevent reversal of current during fast decay SR (synchronous rectification), the outputs
go to the high impedance state as the current approaches zero.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Data Sheet
29319.47C
A3949
DMOS Full-Bridge Motor Driver
ELECTRICAL CHARACTERISTICS at TA = 25°C, VBB = 8 V to 36 V (unless otherwise noted)
Characteristics
Min.
Typ.
Max.
Units
Source driver, IOUT = –2.8 A, TJ= 25°C
–
.4
.48
Ω
Source driver, IOUT = –2.8 A, TJ= 125°C
–
.68
–
Ω
Sink driver, IOUT = 2.8 A, TJ= 25°C
–
.3
.43
Ω
Sink driver, IOUT = –2.8 A, TJ= 125°C
–
.576
–
Ω
Source diode, IF = –2.8 A
–
1.1
1.3
V
Sink diode, IF = 2.8 A
–
1
1.3
V
fPWM < 50 kHz
–
6
8.5
mA
Charge pump turned on; outputs disabled
–
3
4.5
mA
Sleep mode
–
–
10
µA
VIN(1)
2.0
–
–
V
VIN(0)
–
–
0.8
V
Logic Input Voltage
SLEEP
VIN(1)
2.7
–
–
V
VIN(0)
–
–
0.8
V
Logic Input Current
PHASE, MODE pins
IIN(1)
VIN = 2.0 V
–
< 1.0
20
µA
IIN(0)
VIN = 0.8 V
–
< –2.0
–20
µA
Logic Input Current
ENABLE pin
IIN(1)
VIN = 2.0 V
–
40
100
µA
IIN(0)
VIN = 0.8 V
–
16
40
µA
Logic Input Current
SLEEP pin
IIN(1)
VIN = 2.7 V
–
27
50
µA
IIN(0)
VIN = 0.8 V
–
<1
10
µA
From PWM change to source or sink turn on
–
600
–
ns
From PWM change to source or sink turn off
–
100
–
ns
–
500
–
ns
–
6
–
V
–
250
–
mV
TJ
–
170
–
°C
∆TJ
–
15
–
°C
Output-On Resistance
Body Diode Forward Voltage
Motor Supply Current
Logic Input Voltage
PHASE, ENABLE, MODE
Propagation Delay Times
Crossover Delay
Symbol
RDSON
VF
IBB
tpd
Test Conditions
tCOD
Protection Circuitry
UVLO Enable Threshold
VBB rising
UVLO Hysteresis
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3
Data Sheet
29319.47C
A3949
DMOS Full-Bridge Motor Driver
PWM Control Timing Diagram
SLEEP
ENABLE
PHASE
MODE
VBB
OUTA
0V
VBB
OUTB
0V
IOUT
0A
A
1
2
3
4
5
6
7
8
9
VBB
VBB
6
7
OUTB
OUTA
1
OUTA
OUTB
5
9
3
2
8
4
A
Charge pump and VREG power-up delay (approximately 200 us)
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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Data Sheet
29319.47C
A3949
DMOS Full-Bridge Motor Driver
Functional Description
VREG. This supply voltage is used to operate the sinkside DMOS outputs. VREG is internally monitored and in
the case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22 µF
capacitor to ground.
Charge Pump. The charge pump is used to generate a
supply above VBB to drive the source-side DMOS gates. A
0.1 uF ceramic monolithic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1 uF
ceramic monolithic capacitor should be connected between
VCP and VBB to act as a reservoir to run the high side
DMOS devices. The VCP voltage is internally monitored,
and in the case of a fault condition, the outputs of the device
are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of
the device are disabled until the fault condition is removed.
At power-up, the UVLO circuit disables the drivers.
Sleep Mode. Control input SLEEP is used to minimize
power consumption when the A3949 is not in use. This
disables much of the internal circuitry, including the low-side
gate supply and the charge pump. A logic low on this pin
puts the device into Sleep mode. A logic high allows normal
operation. After coming out of Sleep mode, the user should
wait 1 ms before applying PWM signals, to allow the charge
pump to stabilize.
Braking. The braking function is implemented by driving the device in slow decay mode via the MODE pin, and
applying an enable chop command. Because it is possible to
drive current in both directions through the DMOS switches,
this configuration effectively shorts out the motor-generated
BEMF, as long as the enable chop mode is asserted on the
ENABLE pin. The maximum current can be approximated
by VBEMF / RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case
braking situations of high speed and high inertial loads.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5
Data Sheet
29319.47C
A3949
DMOS Full-Bridge Motor Driver
Terminal List Table
Name
Description
Number
TSSOP-16
SOIC-16
Not used
1
1
MODE
Logic input
2
2
PHASE
Logic input for direction control
3
3
Ground
4*
4*
SLEEP
Logic input
5
5
ENABLE
Logic input
6
6
Output A for full bridge
7
7
Power return
8
8
Load supply voltage
9
9
OUTB
Output B for full bridge
10
10
CP1
Charge pump capacitor
11
11
CP2
Charge pump capacitor
12
12
GND
Ground
13*
13*
VCP
Reservoir capacitor
14
14
Low side gate supply decoupler
15
15
Not used
16
16
N/C
GND
OUTA
SENSE
VBB
VREG
N/C
*For the TSSOP package, connect pins 4 and 13 to the exposed thermal pad via the PCB
layout. In the SOIC package, the pins are internally connected.
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
Data Sheet
29319.47C
A3949
DMOS Full-Bridge Motor Driver
A3949SLB 16-Pin Batwing SOIC
.406 10.31
.398 10.11
8”
0”
16
.011 0.28
.009 0.23
.299 7.59
.291 7.39
.040 1.02
.020 0.51
.414 10.52
.398 10.11
1
2
.020 0.51
.014 0.36
.104 2.64
.096 2.44
.050 1.27
BSC
.026 0.66
REF
.012 0.30
.004 0.10
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
Leads 4 and 13 are connected inside the device package.
A3949SLP 16-Pin TSSOP
5.1
4.9
0.201
0.193
8”
0”
16
0.20 0.008
0.09 0.004
4.5 0.177
4.3 0.169
A
6.6 0.260
6.2 0.244
3 0.118
BSC
1 0.039
REF
1
2
3 0.118
BSC
.75
.45
0.030
0.018
.25 0.010
BSC
Seating Plane
Gauge Plane
.30
.19
0.012
0.007
.65 .026
BSC
1.20 0.047
MAX
.15 0.006
.00 0.000
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
A Exposed thermal pad (bottom surface)
No internal connection of leads for thermal dissipation.
NOTES:
1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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Data Sheet
29319.47C
A3949
DMOS Full-Bridge Motor Driver
The products described here are manufactured under one or
more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical components in life-support devices or systems without express written
approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other
rights of third parties which may result from its use.
Copyright©2003, 2004 AllegroMicrosystems, Inc.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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