ETC A42MX36

v5.0
40MX and 42MX FPGA Families
Fe a t ur es
High C apaci t y
•
•
•
•
•
• Commercial, Military Temperature and MIL-STD-883
Ceramic Packages
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
• QML Certification
• Ceramic Devices Available to DSCC SMD
E ase of Int egr at io n
• Mixed Voltage Operation (5.0V or 3.3V I/O)
High P er f or m ance
•
•
•
•
•
• Synthesis-Friendly Architecture to Support ASIC Design
Methodologies
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
• Up to 100% Resource Utilization and 100% Pin Fixing
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
HiR el Feat ur es
• Low Power Consumption
• Commercial, Industrial, and Military Temperature Plastic
Packages
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
• 5.0V and 3.3V Programmable PCI-Compliant I/O
Pr od uc t P r o f i l e
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
3,000
N/A
6,000
N/A
14,000
N/A
24,000
N/A
36,000
N/A
54,000
2,560
—
295
—
9.5 ns
—
547
—
9.5 ns
348
336
N/A
5.6 ns
624
608
N/A
6.1 ns
954
912
24
6.1 ns
1,230
1,184
24
6.3 ns
N/A
—
147
1
57
No
No
N/A
—
273
1
69
No
No
N/A
348
516
2
104
No
No
N/A
624
928
2
140
No
No
N/A
954
1,410
2
176
Yes
Yes
10
1,230
1,822
6
202
Yes
Yes
44, 68
100
80
—
—
—
44, 68, 84
100
80
—
—
—
84
100, 160
100
176
—
—
84
100, 160, 208
100
176
—
—
84
160, 208
—
176
—
—
—
208, 240
—
—
208, 256
272
Capacity
System Gates
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
Clock-to-Out
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
User I/O (Maximum)
PCI
Boundary Scan Test (BST)
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
F eb r u a r y 2 0 0 1
© 2001 Actel Corporation
1
40MX and 42MX FPGA Families
G en er al D e sc r i p t i on
MHz on-chip operation and 6.1 ns clock-to-output
performance with capacities spanning from 36,000 to 54,000
system gates. MX devices comply 100 percent to the
electrical and timing specifications detailed in the PCI
specification. However, as with all programmable logic
devices, the performance of the final product depends upon
the user's design and optimization techniques.
Actel’s 40MX and 42MX families provide a
high-performance, single-chip solution for shortening the
system design and development cycle, offering a
cost-effective alternative to ASICs. The 40MX and 42MX
devices are excellent choices for integrating logic that is
currently implemented in multiple PALs, CPLDs, and
FPGAs. Example applications include high-speed
controllers and address decoding, peripheral bus interfaces,
DSP, and co-processor functions.
The MX24 and MX36 devices also include system-level
features such as IEEE Standard 1149.1 (JTAG) Boudary
Scan Testing, dual-port SRAM, and fast wide-decode
modules. The A42MX36 device offers dual-port SRAM for
implementing fast FIFOs, LIFOs, and temporary data
storage. The large number of storage elements can
efficiently address applications requiring wide datapath
manipulation and can perform transformation functions
such as those required for telecommunications, networking,
and DSP.
The MX device architecture is based on Actel’s patented
antifuse technology implemented in a 0.45µ triple-metal
CMOS process. With capacities ranging from 3,000 to 54,000
system gates, the synthesis-friendly MX devices provide
performance up to 250 MHz, are live on power-up, and
require up to five times lower stand-by power consumption
than any other FPGA device. Actel’s MX FPGAs provide up
to 202 user I/Os and are available in a wide variety of
packages and speed grades.
All products in the 40MX and 42MX families are available
100 percent tested over the military temperature range. In
addition, the largest member of the family, the A42MX36, is
available in both CQ208 and CQ256 ceramic packages
screened to MIL-STD-883 levels. For easy prototyping and
conversion from plastic to ceramic, the CQ208 and PQ208
devices are pin compatible.
Actel’s 42MX devices also feature MultiPlex I/Os, which
support mixed voltage systems, enable programmable PCI,
deliver high-performance operation at both 5.0V and 3.3V,
and provide a low-power mode.
The MX PCI-Compliant devices are fully compliant with the
PCI Local Bus Specification (version 2.1). They deliver 200
O r d e r i n g I nf o r m a t i o n
A42MX16
–
PQ
100
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Package Type
PL = Plastic Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
BG = Ball Grid Array
CQ = Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
A40MX02=
A40MX04=
A42MX09=
A42MX16=
A42MX24=
A42MX36=
2
3,000 System Gates
6,000 System Gates
14,000 System Gates
24,000 System Gates
36,000 System Gates
54,000 System Gates
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pr od uc t P l a n
Speed Grade1
Application
Std
–1
–2
–3
–F2
C
I
M
B
44-Pin Plastic Leaded Chip Carrier (PLCC)
✔
✔
✔
✔
✔
✔
✔
✔
—
68-Pin Plastic Leaded Chip Carrier (PLCC)
✔
✔
✔
✔
✔
✔
✔
✔
—
100-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
80-Pin Very Thin Plastic Quad Flat Pack (VQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
44-Pin Plastic Leaded Chip Carrier (PLCC)
✔
✔
✔
✔
✔
✔
✔
✔
—
68-Pin Plastic Leaded Chip Carrier (PLCC)
✔
✔
✔
✔
✔
✔
✔
✔
—
84-Pin Plastic Leaded Chip Carrier (PLCC)
✔
✔
✔
✔
✔
✔
✔
✔
—
100-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
80-Pin Very Thin Plastic Quad Flat Pack (VQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
84-Pin Plastic Leaded Chip Carrier (PLCC)
✔
✔
✔
✔
✔
✔
✔
✔
—
100-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
160-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
176-Pin Thin Plastic Quad Flat Pack (TQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
100-Pin Very Thin Plastic Quad Flat Pack (VQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
84-Pin Plastic Leaded Chip Carrier (PLCC)
✔
✔
✔
✔
✔
✔
✔
✔
—
100-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
160-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
208-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
176-Pin Thin Plastic Quad Flat Pack (TQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
100-Pin Very Thin Plastic Quad Flat Pack (VQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
84-Pin Plastic Leaded Chip Carrier (PLCC)
✔
✔
✔
✔
✔
✔
✔
✔
—
160-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
208-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
176-Pin Thin Plastic Quad Flat Pack (TQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
208-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
240-Pin Plastic Quad Flat Pack (PQFP)
✔
✔
✔
✔
✔
✔
✔
✔
—
272-Pin Plastic Ball Grid Array (PBGA)
✔
✔
✔
✔
✔
✔
✔
✔
—
—
3
✔
✔3
—
✔3
✔3
faster
faster
faster
slower
than
than
than
than
A40MX02 Device
A40MX04 Device
A42MX09 Device
A42MX16 Device
A42MX24 Device
A42MX36 Device
208-Pin Ceramic Quad Flat Pack (CQFP)
✔
✔
256-Pin Ceramic Quad Flat Pack (CQFP)
✔
✔
Contact your Actel sales representative for product availability.
Applications: C = Commercial
Availability: ✔ = Available
Standard I = Industrial
P = Planned
Standard M = Military
— = Not Planned
Standard
Standard
v5.0
✔
✔
—
—
—
—
✔
✔
*Speed Grade: –1 = Approx.
–2 = Approx.
–3 = Approx.
–F = Approx.
† Only Std, –1, –2 Speed Grade
• Only Std, –1 Speed Grade
15%
25%
35%
40%
3
40MX and 42MX FPGA Families
D ev el o pm e n t T oo l S up po r t
enabling 100 percent real-time observation and analysis of a
device's internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer II, an
easy-to-use integrated verification and logic analysis tool
that can sample data at 100 MHz (asynchronous) or 66 MHz
(synchronous). Silicon Explorer II attaches to a PC’s
standard COM port, turning the PC into a fully functional
18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several hours
per cycle to only a few seconds.
The MX devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Series tools. The Actel DeskTOP series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place-and-route tools.
Designer Series, Actel’s suite of FPGA development point
tools for PCs and Workstations, includes the ACTgen Macro
Builder, timing-driven place-and-route and analysis tools,
and device programming software.
In addition, the MX devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
Pl a s t i c D e vi c e Re so u r ce s
User I/Os
PLCC
44-Pin
PLCC
68-Pin
PLCC
84-Pin
A40MX02
34
57
—
57
—
—
—
57
—
—
—
A40MX04
34
57
69
69
—
—
—
69
—
—
—
A42MX09
—
—
72
83
101
—
—
—
83
104
—
A42MX16
—
—
72
83
125
140
—
—
83
140
—
A42MX24
—
—
72
—
125
176
—
—
—
150
—
A42MX36
—
—
—
—
—
176
202
—
—
—
202
Device
PQFP
PQFP
PQFP
PQFP
100-Pin 160-Pin 208-Pin 240-Pin
VQFP
80-Pin
VQFP
TQFP
PBGA
100-Pin 176-Pin 272-Pin
Package Definitions (Contact your Actel sales representative for product availability.)
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,
PBGA = Plastic Ball Grid Array
C er a m i c De v i ce R es ou r c es
User I/Os
Device
A42MX36
CQFP
CQFP
208-Pin 256-Pin
176
202
Package Definitions (Contact your Actel sales representative for product availability.)
CQFP = Ceramic Quad Flat Pack
4
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Po w e r R eq ui r em e nt s
M X Ar ch i t e ct u r a l O ve r vi ew
40MX
The 40MX and 42MX devices are composed of fine-grained
building blocks that enable fast, efficient logic designs. All
devices within these families are composed of logic
modules, I/O modules, routing resources, and clock
networks, which are the building blocks for designing fast
logic designs. In addition, the A42MX36 device contains
embedded dual-port SRAM and wide decode modules. The
dual-port SRAM modules are optimized for high-speed
datapath functions such as FIFOs, LIFOs, and scratchpad
memory. The “Product Profile” on page 1 lists the specific
logic resources contained within each device.
The 40MX FPGAs will operate in 5.0V-only systems or
3.3V-only systems.
VCC
Input
Output
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
42MX
The 42MX FPGAs will operate in 5.0V-only systems,
3.3V-only systems, or mixed 5.0V/3.3V systems.
VCCA
VCCI
Input
Output
5.0V
5.0V
5.0V
5.0V
3.3V
3.3V
3.3V
3.3V
5.0V
3.3V
3.3V, 5.0V
3.3V
M i xe d Vo l t a ge P ow e r U p an d P o w er
D ow n
When powering up the device in the mixed voltage mode
(VCCA = 5.0V and VCCI = 3.3V), VCCA must be greater than or
equal to VCCI throughout the power-up sequence. If VCCI is
0.5V greater than VCCA when both are above 1.5V, then the
I/Os’ input protection junction on the I/Os will be forward
biased, causing them to draw large amounts of current.
When VCCA and VCCI are in the 1.5V to 2.0V region and VCCI
is greater than VCCA, all I/Os would momentarily behave as
outputs that are in a logical high state, and ICC rises to high
levels. For power down, any sequence with VCCA and VCCI
can be implemented.
Logi c Modu les
The 40MX logic module is an eight-input, one-output logic
circuit designed to implement a wide range of logic
functions with efficient use of interconnect routing
resources (Figure 1).
The logic module can implement the four basic logic
functions (NAND, AND, OR, and NOR) in gates of two, three,
or four inputs. Each function may have many versions with
different combinations of active LOW inputs. The logic
module can also implement a variety of D-latches,
exclusivity functions, AND-ORs, and OR-ANDs. No dedicated
hard-wired latches or flip-flops are required in the array,
since latches and flip-flops can be constructed from logic
modules wherever needed in the application.
Lo w P ow e r M o de
The 42MX devices have a power-saving feature enabled by a
special Low Power pin (LP). In this mode, the device
consumes very minimal power, with standby current as low
as 15µA (see “Electrical Specifications” on page 13 and 14).
All µ I/Os are tristated, all input buffers are turned off, and
the core of the device is turned off. Since the core is turned
off, the state of the registers and the contents of the SRAM
are lost. The device enters low power mode 800ns after the
LP pin is set High. It will resume normal operation 200µs
after the LP pin is driven to a logic Low.
Figure 1 • 40MX Logic Module
v5.0
5
40MX and 42MX FPGA Families
The 42MX devices contain three types of logic modules:
combinatorial (C-modules), sequential (S-modules), and
decode (D-modules).
A0
B0
S0
The C-module, shown in Figure 2, implements the following
function:
D00
Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11
D01
Y
where
S0=A0*B0
D10
S1=A1+B1
D11
The S-module, shown in Figure 3, is designed to implement
high-speed sequential functions within a single logic
module. The S-module implements the same combinatorial
logic function as the C-module while adding a sequential
element. The sequential element can be configured as
either a D flip-flop or a transparent latch. To increase
flexibility, the S-module register can be bypassed so that it
implements purely combinatorial logic.
S1
A1
B1
Figure 2 • C-Module Implementation
D00
D00
D01
Y
D10
D
Q
D01
OUT
S0
D11
D11
CLR
S1
Y
D10
S0
D
Q
GATE
S1
Up to 7-Input Function Plus Latch
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D00
D0
D01
Y
D1
S
D
Q
OUT
D11
S1
GATE
CLR
OUT
S0
Up to 8-Input Function Same as C-Module)
Up to 4-Input Function Plus Latch with Clear
Figure 3 • S-Module Implementation
6
Y
D10
v5.0
OUT
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Some of the 42MX devices contain D-modules, which are
arranged around the periphery of the devices. D-modules
contain wide-decode circuitry, which provides a fast,
wide-input AND function similar to that found in
product-term architectures (Figure 4). The D-module
allows 42MX devices to perform wide-decode functions at
speeds comparable to CPLDs and PALs. The output of the
D-module has a programmable inverter for active HIGH or
LOW assertion. The D-module output is hard-wired to an
output pin, but it can also be fed back into the array to be
incorporated into other logic.
offering active HIGH or LOW implementation. The SRAM
block contains eight data inputs (WD[7:0]), and eight
outputs (RD[7:0]) which are connected to segmented
vertical routing tracks.
The 42MX dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring fast
FIFO and LIFO queues. Actel’s ACTgen Macro Builder
provides the capability to quickly design memory functions,
such as FIFOs, LIFOs, and RAM arrays. In addition, unused
SRAM blocks can be used to implement registers for other
logic within the design.
Dua l- Po rt S R AM Mod ules
The A42MX36 device contains dual-port SRAM modules that
have been optimized for synchronous or asynchronous
applications. The SRAM modules are arranged in 256-bit
blocks that can be configured as 32x8 or 64x4. SRAM
modules can be cascaded together to form memory spaces
of user-definable width and depth. A block diagram of the
42MX dual-port SRAM block is shown in Figure 5.
The 42MX SRAM modules are true dual-port structures
containing independent read and write ports. Each SRAM
module contains six bits of read and write addressing
(RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit
blocks. When configured in byte mode, the highest order
address bits (RDAD5 and WRAD5) are not used. The read
and write ports of the SRAM block contain independent
clocks (RCLK and WCLK) with programmable polarities
WD[7:0]
7 Inputs
Hard-Wire to I/O
Programmable
Inverter
Feedback to Array
Figure 4 • D-Module Implementation
Latches
[7:0]
[5:0]
WRAD[5:0]
[5:0]
Write
Port
Logic
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
RDAD[5:0]
Latches
Read
Logic
Latches
REN
RCLK
MODE
BLKEN
WEN
Read
Port
Logic
Write
Logic
WCLK
RD[7:0]
Routing Tracks
Figure 5 • 42MX Dual-Port SRAM Block
v5.0
7
40MX and 42MX FPGA Families
Mul ti P lex I/ O M odul es
Horizontal Routing
MultiPlex I/O supports the most common voltage standards
today: pure 5.0V operation, pure 3.3V operation, and mixed
3.3V operation with 5.0V I/O tolerance for maximum
performance. Internal array performance is retained in 3.3V
systems by using complimentary pass gates that operate as
fast as they do at 5.0V at 3.3V.
Horizontal channels are located between the rows of
modules and are composed of several routing tracks. The
horizontal routing tracks within the channel are divided
into one or more segments. The minimum horizontal
segment length is the width of a module pair, and the
maximum horizontal segment length is the full length of the
channel. Any segment that spans more than one-third at the
row length is considered a long horizontal segment. A
typical channel is shown in Figure 8 on page 9.
Non-dedicated horizontal routing tracks are used to route
signal nets; dedicated routing tracks are used for global
clock networks and for power and ground tie-off tracks.
MultiPlex I/O includes selectable PCI output drives in
certain 42MX devices, enabling 100% PCI-compliance for
both 5.0V and 3.3V systems. For low-power systems,
MultiPlex I/O is used to turn off all inputs and outputs to cut
current consumption to below 100µA.
The MultiPlex I/O modules provide the interface between
the device pins and the logic array. The top of Figure 6 is a
block diagram of the 42MX I/O module. A variety of user
functions, determined by a library macro selection, can be
implemented in the module. (Refer to the Macro Library
Guide for more information.) All 42MX I/O modules contain
tristate buffers, with input and output latches that can be
configured for input, output, or bi-directional operation.
EN
Q
D
PAD
From Array
All 42MX devices contain flexible I/O structures (Figure 7 on
page 9), where each output pin has a dedicated
output-enable control. The I/O module can be used to latch
input or output data, or both, providing a fast set-up time. In
addition, the Actel Designer Series software tools can build
a D-type flip-flop using a C-module to register input and
output signals. To achieve 5.0V or 3.3V PCI-compliant output
drives on A42MX24 and A42MX36 devices, a chip-wide PCI
fuse is programmed. When the PCI fuse is not programmed,
the output drive is standard. (See the bottom portion of
Figure 6.)
G/CLK*
Q
D
To Array
G/CLK*
* Can be Configured as a Latch or D Flip-Flop
(Using C-Module)
Schematic
Actel’s Designer Series development tools provide a design
library of I/O macrofunctions that can implement all I/O
configurations supported by the MX FPGAs.
STD
Signal
Rou ti ng St r uct ur e
The MX architecture uses vertical and horizontal routing
tracks to interconnect the various logic and I/O modules.
These routing tracks are metal interconnects that may be
either of continuous length or broken into pieces called
segments. Varying segment lengths allows the interconnect
of over 90% of design tracks to occur with only two antifuse
connections. Segments can be joined together at the ends
using antifuses to increase their lengths up to the full length
of the track. All interconnects can be accomplished with a
maximum of four antifuses.
Output
PCI
Drive
PCI Enable
Fuse
Figure 6 • 42MX I/O Module
Vertical Routing
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks: input,
output, and long, which are also divided into one or more
segments. Each segment in an input track is dedicated to
the input of a particular module; each segment in an output
track is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
8
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
OE
From Internal Logic
To Internal Logic
Figure 7 • 40MX I/O Module
routing. Each output segment spans four channels (two
above and two below), except near the top and bottom of
the array, where edge effects occur. Long vertical tracks
contain either one or two segments. An example of vertical
routing tracks and segments is shown in Figure 8.
internally-generated clock signal to a clock network. Since
both clock networks are identical, it does not matter
whether CLK0 or CLK1 is being used. The clock input pads
can also be used as normal I/Os, bypassing the clock
networks (Figure 9).
The A42MX36 device has four additional register control
resources, called quadrant clock networks (Figure 10 on
page 10). Each quadrant clock provides a local, high-fanout
resource to the contiguous logic modules within its
quadrant of the device. Quadrant clock signals can originate
from specific I/O pins or from the internal array and can be
used as a secondary register clock, register clear, or output
enable.
Segmented
Horizontal
Routing
Tracks
Antifuse Structures
An antifuse is a “normally open” structure as opposed to the
normally connected fuse structure used in PROMs or PALs.
The use of antifuses to implement a programmable logic
device results in highly testable structures as well as
efficient programming algorithms. The structure is
highly-testable because there are no pre-existing
connections; therefore, temporary connections can be made
using pass transistors. These temporary connections can
isolate individual antifuses to be programmed and
individual circuit structures to be tested, which can be done
before and after programming. For example, all metal
tracks can be tested for continuity and shorts between
adjacent tracks, and the functionality of all logic modules
can be verified.
Logic
Modules
Antifuses
Vertical Routing Tracks
Figure 8 • Routing Structure
CLKB
CLKINB
CLKA
CLKINA
From
Pads
Cl ock Net wor ks
The 40MX devices have one global clock distribution
network (CLK). Two low-skew, high-fanout clock
distribution networks are provided in each 42MX device.
These networks are referred to as CLK0 and CLK1. Each
network has a clock module (CLKMOD) that selects the
source of the clock signal and may be driven as follows:
CLKMOD
S0
S1
Internal
Signal
CLKO(17)
Clock
Drivers
• Externally from the CLKA pad
CLKO(16)
CLKO(15)
• Externally from the CLKB pad
• Internally from the CLKINTA input
CLKO(2)
• Internally from the CLKINTB input
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
The user controls the clock module by selecting one of two
clock macros from the macro library. The macro CLKBUF is
used to connect one of the two external clock pins to a clock
network, and the macro CLKINT is used to connect an
CLKO(1)
Clock Tracks
Figure 9 • Clock Networks
v5.0
9
40MX and 42MX FPGA Families
T est C ir cu it ry
interconnections. The TMS and TCK signals are shared
among all devices in the test chain so that all components
operate in the same state.
All devices contain Actel’s ActionProbe test circuitry which
test and debug a design once it is programmed into a device.
Once a device has been programmed, the ActionProbe test
circuitry allows the designer to probe any internal node
during device operation to aid in debugging a design. In
addition, 42MX devices contain IEEE Standard 1149.1
boundary scan test circuitry.
The 42MX family implements a subset of the IEEE Standard
1149.1 BST instruction in addition to a private instruction,
which allows the use of Actel’s ActionProbe facility with
BST. Refer to the IEEE Standard 1149.1 specification for
detailed information regarding BST.
IEEE Standard 1149.1 Boundary Scan Testing (BST)
Boundary Scan Circuitry
IEEE Standard 1149.1 defines a four-pin Test Access Port
(TAP) interface for testing integrated circuits in a system.
The 42MX family provides five BST pins: Test Data In (TDI),
Test Data Out (TDO), Test Clock (TCK), and Test Mode
Select Test Reset (TRST) (42MX24A only). Devices are
configured in a test “chain” where BST data can be
transmitted serially between devices via TDO-to-TDI
The 42MX boundary scan circuitry consists of a Test Access
Port (TAP) controller, test instruction register, a JPROBE
register, a bypass register, and a boundary scan register.
Figure 11 on page 11 shows a block diagram of the 42MX
boundary scan circuitry.
QCLKA
QCLKB
QCLKC
Quad
Clock
Module
QCLK1
QCLK3
Quad
Clock
Module
*QCLK1IN
*QCLK3IN
S0 S1
S1 S0
Quad
Clock
Module
Quad
Clock
Module
QCLK2
QCLK4
*QCLK2IN
*QCLK4IN
S0 S1
S1 S0
*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 10 • Quadrant Clock Network
10
QCLKD
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
JPROBE Register
Boundary Scan Register
Output
MUX
TDO
Bypass
Register
Control Logic
JTAG
TMS
TAP Controller
TCK
Instruction
Decode
JTAG
TDI
Instruction
Register
Figure 11 • 42MX IEEE 1149.1 Boundary Scan Circuitry
When a device is operating in BST mode, four I/O pins are
used for the TDI, TDO, TMS, and TCK signals. An active
reset (nTRST) pin is not supported; however, the 42MX
device contain power-on circuitry that resets the boundary
scan circuitry upon power-up. Table 1 summarizes the
functions of the IEEE 1149.1 BST signals.
Table 1 • IEEE 1149.1 BST Signals
JTAG fuse programmed:
• TCK must be terminated—logical high or low doesn’t
matter (to avoid floating input)
• TDI, TMS may float or at logical high (internal pull-up is
present)
• TDO may float or connect to TDI of another device (it’s an
output)
Signal
Name
Function
JTAG fuse not programmed:
TDI
Test Data In
Serial data input for BST
instructions and data. Data is
shifted in on the rising edge of
TCK.
• TCK, TDI, TDO, TMS are user I/O. If not used, they will be
configured as tristated output.
TDO
Test Data
Out
Serial data output for BST
instructions and test data.
TMS
Test Mode
Select
Serial data input for BST mode.
Data is shifted in on the rising
edge of TCK.
TCK
Test Clock
Clock signal to shift the BST
data into the device.
JTAG
All SX-A devices are IEEE 1149.1 (JTAG) compliant. SX-A
devices offer superior diagnostic and testing capabilities by
providing JTAG and probing capabilites. These functions
are controlled through the special JTAG pins in conjunction
with the program fuse.
BST Instructions
Boundary scan testing within the 42MX devices is controlled
by a Test Access Port (TAP) state machine. The TAP
controller drives the three-bit instruction register, a bypass
register, and the boundary scan data registers within the
device. The TAP controller uses the TMS signal to control
the testing of the device. The BST mode is determined by
the bitstream entered on the TMS pin. Table 2 describes the
test instructions supported by the 42MX devices.
Reset
The TMS pin is equipped with an internal pull-up resistor.
This allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
v5.0
11
40MX and 42MX FPGA Families
Table 2 • BST Instructions
Test Mode
Code
Description
EXTEST
000
Allows the external circuitry and
board-level interconnections to
be tested by forcing a test
pattern at the output pins and
capturing test results at the
input pins.
SAMPLE/
PRELOAD
001
Allows a snapshot of the signals
at the device pins to be
captured and examined during
device operation.
JPROBE
011
A private instruction allowing the
user to connect Actel’s Micro
Probe registers to the test
chain.
USER
100
INSTRUCTION
Allows the user to build
application-specific instructions
such as RAM READ and RAM
WRITE.
HIGH Z
101
Refer to the IEEE Standard
1149.1 specification.
CLAMP
110
Refer to the IEEE Standard
1149.1 specification.
BYPASS
111
Enables the bypass register
between the TDI and TDO pins.
The test data passes through
the selected device to adjacent
devices in the test chain.
12
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
5 . 0V O p er a t i n g C o nd i t i o ns a nd M i xe d 5. 0 V / 3. 3 V Op e r at i ng C on di t i on s
A bs o l ut e M a xi m u m R at i ng s 1
R e co m m e nd e d O p era t i n g C o nd i t i o ns
Free Ai r Tem per at ure Rang e
Parameter
Symbol Parameter
Limits
VCCA/
VCCI
DC Supply Voltage
VI
Units
–0.5 to +7.0
V
Input Voltage
–0.5 to VCC +0.5
V
VO
Output Voltage
–0.5 to VCC +0.5
V
TSTG
Storage Temperature
–65 to +150
°C
Notes:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Devices should not be
operated outside the Recommended Operating Conditions.
2. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than VCCA + 0.5V or less than GND – 0.5V, the internal
protection diode will be forward-biased and can draw
excessive current.
Commercial Industrial
Military
Units
Temperature
Range1
0 to +70
Power Supply
Tolerance
±5
±10
±10
%VCC
VCCI
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCA
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCI2
3.14 to 3.47
3.0 to 3.6
3.0 to 3.6
V
–40 to +85 –55 to +125
°C
Notes:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
2. Operating condition for I/Os in mixed voltage mode.
E l ec t r i c a l Sp e ci f i c a t i on s
Commercial
Symbol
Industrial
Military
Units
Min.
VOH1
Commercial ‘–F’
Parameter
(IOH = –10 mA) 2 TTL
Max.
2.4
Min.
Max.
Min.
Max.
Min.
Max.
2.4
V
(IOH = –6 mA) TTL
V
(IOH = –4 mA) TTL
VOL
1
(IOL = 10
3.7
mA) 2 TTL
0.5
VIH
IIL
(VIN = 0.5)
IIH
(VIN = 2.7)
Input Transition Time tR, tF
CIO I/O
2
Capacitance2, 3
Standby Current, ICC
4
V
0.40
0.40
V
V
–0.3
0.8
–0.3
0.8
–0.3
0.8
–0.3
0.8
2.0
VCCI + 0.3
2.0
VCCI + 0.3
2.0
VCCI + 0.3
2.0
VCCI + 0.3
V
–10
–10
–10
–10
µA
–10
–10
–10
–10
µA
500
500
500
500
ns
10
10
10
10
pF
Notes 5 & 6
25.0
Notes 6 & 7
25
mA
ICC – 0.5
mA
ICC(D) Dynamic VCCI Supply Current
Low Power Mode Standby Current
V
0.5
(IOL = 6 mA) TTL
VIL
3.7
See the “Power Dissipation” section on page 18.
Note 8
ICC – 0.5
ICC – 0.5
Notes:
1. Only one output tested at a time. VCCI = min.
2. Not tested, for information only.
3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz.
4. All outputs unloaded. All inputs = VCCI or GND. ICC limit includes IPP and ISV during normal operation.
5. A40MX02 and A40MX04 ICC = 3 mA, A42MX09 ICC = 5 mA, A42MX16 ICC = 6 mA, A42MX24, A42MX24A, and A42MX36 ICC = 25 mA.
6. ICC Max = 2 mA is available by special request. Contact your local Actel Sales representative for additional information.
7. A40MX02 and A40MX04 ICC = 10 mA, A42MX09, A42MX16, A42MX24, A42MX24A, and A42MX36 ICC = 25 mA.
8. In Low Power Mode, A42MX09 ICC = 50 µA; A42MX16, A42MX24, and A42MX36 ICC = 100 µA. A40MX02 and A40MX04 = N/A.
v5.0
13
40MX and 42MX FPGA Families
3. 3 V O pe r a t i ng C on d i t i on s
A bs ol u t e M ax i m u m Ra t i n gs 1
R ec o m m en d ed O pe r a t i ng C on d i t i o ns
V C C = V C C A and V C C I
Fr ee Air Te m per at ure R ange
Parameter
Symbol
Parameter
Limits
Units
–0.5 to +7.0
V
Commercial Industrial
Military
Units
Temperature
Range1
0 to
+70
–40 to
+85
–55 to
+125
°C
Power Supply
Tolerance
±5
±10
±10
%V
VCC
DC Supply Voltage
VI
Input Voltage
–0.5 to VCC +0.5
V
VCCI
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
VO
Output Voltage
–0.5 to VCC +0.5
V
VCCA
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
±20
mA
–65 to +150
°C
IIO
TSTG
I/O Source Sink
Current2
Storage Temperature
Note:
1. Ambient temperature (TA) is used for commercial, and
industrial; case temperature (TC) is used for military.
Notes:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Devices should not be
operated outside the Recommended Operating Conditions.
2. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than VCC + 0.5V or less than GND – 0.5V, the internal protection
diodes will forward-bias and can draw excessive current.
El e c t r i c al S p ec i f i c at i o n s
Commercial
Commercial ‘–F’
Industrial
Military
Parameter
Units
Min.
VOH1
VOL1
Max.
Min.
(IOH = –4 mA)
2.15
2.15
(IOH = –3.2 mA)
2.4
2.4
(IOL = 6 mA)
0.4
Max.
Min.
Max.
2.4
Min.
Max.
2.4
V
V
0.4
0.48
0.48
V
VIL
–0.3
0.8
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
VIH
2.0
VCC + 0.3
2.0
VCC + 0.3
2.0
VCC + 0.3
2.0
VCC + 0.3
V
IIL
IIH
Input Transition Time tR, tF
CIO I/O
2
Capacitance2, 3
Standby Current, ICC
4
–10
–10
–10
–10
µA
–10
–10
–10
–10
µA
500
500
500
500
ns
10
10
10
10
pF
Notes 5 & 6
25
Notes 6 & 7
25
mA
ICC – 5.0
mA
ICC(D) Dynamic VCC Supply Current
Low Power Mode Standby Current
See the “Power Dissipation” section on page 18.
Note 8
ICC – 5.0
ICC – 5.0
Notes:
1. Only one output IV curve tested at a time. VCC = min.
2. Not tested, for information only.
3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz.
4. All outputs unloaded. All inputs = VCC or GND.
5. A40MX02 and A40MX04 ICC = 3 mA, A42MX09 ICC = 5 mA, A42MX16 ICC = 6 mA, A42MX24 and A42MX36 ICC = 25 mA.
6. ICC Max = 1.5mA is available by special request. Contact your Actel Sales representative for additional information.
7. A40MX02 and A40MX04 ICC = 10 mA, A42MX09, A42MX16, A42MX24, and A42MX36 ICC = 25 mA.
8. In Low Power Mode, A42MX09 ICC = 15 µA; A42MX16, A42MX24, A42MX36 ICC = 50 µA. A40MX02 and A40MX04 = N/A.
14
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
O ut p u t D r i ve C ha r a ct e r i s t i c s f o r
5. 0 V PC I S i g na l i n g
MX PCI device I/O drivers were designed specifically for
high-performance PCI systems. Figure 12 on page 17 shows
the typical output drive characteristics of the MX devices.
MX output drivers are compliant with the PCI Local Bus
Specification.
DC S pec if i cat ion (5. 0V P CI S igna li ng) 1
PCI
Symbol
Parameter
Condition
Minimum
MX
Maximum
Minimum
Maximum
2
Units
VCC
Supply Voltage
4.75
5.25
4.75
5.25
VIH
Input High Voltage
2.0
VCC + 0.5
2.0
VCC + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
VIN = 2.7
70
—
10
µA
IIL
Input Low Leakage Current
VIN=0.5
–70
—
–10
µA
VOH
Output High Voltage
VOL
Output Low Voltage
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
LPIN
IOUT = –2 mA
2.4
IOUT = –6 mA
V
3.84
IOUT = 3 mA,
6 mA
V
0.55
—
0.33
V
10
—
10
pF
12
—
10
pF
5
Pin Inductance
20
—
<8
nH3
nH
Notes:
1. PCI Local Bus Specification Section 4.2.1.1.
2. Maximum rating for VCC –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
AC S pec if i cat ion s (5.0 V P C I S i gnal ing ) 1
PCI
Symbol
Parameter
Condition
Minimum
ICL
Low Clamp Current
–5 < VIN ≤ –1
Slew (r)
Output Rise Slew Rate
0.4V to 2.4V load
1
Slew (f)
Output Fall Slew Rate
2.4V to 0.4V load
1
MX
Maximum
Minimum
Maximum
Units
–60
–10
mA
5
1.8
2.8
V/ns
5
2.8
4.3
V/ns
–25 + (VIN +1)
/0.015
Note:
1. PCI Local Bus Specification Section 4.2.1.2.
v5.0
15
40MX and 42MX FPGA Families
O ut p u t D r i ve C ha r a ct e r i s t i c s f o r 3 . 3V P C I Si gn al i n g
DC S pec if i cat ion (3. 3V P CI S igna li ng) 1
PCI
Symbol
Parameter
VCC
Minimum
Maximum
Minimum
Maximum
Units
Supply Voltage
3.0
3.6
3.0
3.6
V
VIH
Input High Voltage
0.5
VCC + 0.5
0.5
VCC + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
70
10
µA
IIL
Input Leakage Current
–70
–10
µA
VOH
Output High Voltage
IOUT = –2 mA
VOL
Output Low Voltage
IOUT = 3 mA,
6 mA
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
LPIN
Condition
MX
VIN = 2.7
0.9
3.3
5
Pin Inductance
V
0.1
0.1 VCC
V
10
10
pF
12
10
pF
20
<8
nH3
nH
Notes:
1. PCI Local Bus Specification Section 4.2.2.1.
2. Maximum rating for VCC –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
AC S pec if i cat ion s for (3. 3V P CI S igna li ng) 1
PCI
Symbol
Parameter
Condition
Minimum
ICL
Low Clamp Current
–5 < VIN ≤ –1
Slew (r)
Output Rise Slew Rate
0.2V to 0.6V load
1
Slew (f)
Output Fall Slew Rate
0.6V to 0.2V load
1
Maximum
Minimum
Maximum
Units
–60
–10
mA
4
1.8
2.8
V/ns
4
2.8
4.0
V/ns
–25 + (VIN +1)
/0.015
Note:
1. PCI Local Bus Specification Section 4.2.2.2.
16
MX
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
0.50
0.45
0.40
PCI IOL Maximum
0.35
0.30
0.25
Current (A)
0.20
MX PCI IOL
0.15
0.10
PCI IOL Minimum
0.05
0.00
0
–0.05
1
2
3
4
PCI IOH Maximum
5
6
MX PCI IOH
–0.10
–0.15
PCI IOH Minimum
–0.20
Voltage Out (V)
Figure 12 • Typical Output Drive Characteristics (Based upon measured data)
v5.0
17
40MX and 42MX FPGA Families
Pa c ka ge T he r m a l C ha r a ct e r i s t i c s
The device junction-to-case thermal characteristic is θjc,
and the junction-to-ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates. Ambient temperature (TA) is used for
commercial and industrial; case temperature (TC) is used
for military.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a PQFP 160-pin package at
commercial temperature is as follows:
Max. junction temp. (°C) – Max. commercial temp.
– 70°C
----------------------------------------------------------------------------------------------------------------------------- = 150°C
--------------------------------= 2.5W
θ ja (°C/W)
32°C/W
θja
Plastic Packages
Pin Count
θjc
Still Air
300 ft/min
Plastic Quad Flat Pack
100
12
34°C/W
31°C/W
Plastic Quad Flat Pack
160
10
32°C/W
24°C/W
Plastic Quad Flat Pack
208
8
30°C/W
23°C/W
Plastic Quad Flat Pack
240
3.5
19°C/W
16°C/W
Plastic Leaded Chip Carrier
44
16
43°C/W
31°C/W
Plastic Leaded Chip Carrier
68
13
36°C/W
25°C/W
Plastic Leaded Chip Carrier
84
12
32°C/W
22°C/W
Thin Plastic Quad Flat Pack
176
11
28°C/W
21°C/W
Very Thin Plastic Quad Flat Pack
80
12
39°C/W
33°C/W
Very Thin Plastic Quad Flat Pack
100
10
38°C/W
32°C/W
Plastic Ball Grid Array
272
3
20°C/W
14.5°C/W
θja
Pin Count
θjc
Ceramic Quad Flat Pack
208
6.3
22°C/W
Ceramic Quad Flat Pack
256
6.2
20°C/W
Ceramic Packages
Po w e r D i ss i pa t i o n
Gener al P ow er E quat i on
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N
+ IOH * (VCCI – VOH) * M
where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
ICCactive is the current flowing due to CMOS switching.
Still Air
S t at ic Po wer C om pon ent
Actel FPGAs have small static power components that
result in power dissipation lower than PALs or CPLDs. By
integrating multiple PALs/CPLDs into one FPGA, an even
greater reduction in board-level power dissipation can
be achieved.
The power due to standby current is typically a small
component of the overall power. Standby power is
calculated for commercial, worst-case conditions:
ICC
2 mA
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to VOH.
Accurate values for N and M are difficult to determine
because they depend on the family type, on design details,
and on the system I/O. The power can be divided into two
components: static and active.
18
VCCA
5.25 V
Power
10.5 mW
The static power dissipation by TTL loads depends on the
number of outputs driving HIGH or LOW, and on the DC load
current. Again, this number is typically small. For instance,
a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with
all outputs driving LOW, and 140 mW with all outputs driving
HIGH. The actual dissipation will average somewhere in
between, as I/Os switch states with time.
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Act i ve P ower C om po nent
where:
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency-dependent and a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
and load device inputs. An additional component of the
active power dissipation is the totem pole current in the
CMOS transistor pairs. The net effect can be associated
with an equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
m
n
p
q1
E quiv al ent C apac it ance
The power dissipated by a CMOS circuit can be expressed by
the equation:
Power (µW) = CEQ * VCCA2 * F
(1)
where:
CEQ
= Equivalent capacitance expressed in picofarads
(pF)
VCCA = Power supply in volts (V)
F
= Switching frequency in megahertz (MHz)
Equivalent capacitance is calculated by measuring
ICCactive at a specified frequency and voltage for each
circuit component of interest. Measurements have been
made over a range of frequencies at a fixed value of VCC.
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown below.
= Number of logic modules switching at frequency fm
= Number of input buffers switching at frequency fn
= Number of output buffers switching at frequency fp
= Number of clock loads on the first routed array
clock
q2
= Number of clock loads on the second routed array
clock
r1
= lFixed capacitance due to first routed array clock
r2
= Fixed capacitance due to second routed array
clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
CL
= Output load capacitance in p
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
fp
= Average output buffer switching rate in MHz
fq1
= Average first routed array clock rate in MHz
fq2
= Average second routed array clock rate in MHz
Fix ed Capa cit anc e V alu es
for M X F PG As (pF )
r1
routed_Clk1
r2
routed_Clk2
A40MX02
41.4
N/A
A40MX04
68.6
N/A
Device Type
C E Q Valu es f or A ct el MX FP G A s
Modules (CEQM)
3.5
A42MX09
118
118
Input Buffers (CEQI)
6.9
A42MX16
165
165
A42MX24
185
185
A42MX36
220
220
Output Buffers (CEQO)
18.2
Routed Array Clock Buffer Loads (CEQCR)
1.4
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
must be known. The equation below shows a piece-wise
linear summation over all components.
Power = VCCA2 * [(m x CEQM * fm)Modules +
(n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs +
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2
(2)
v5.0
19
40MX and 42MX FPGA Families
Det er m ini ng Av er age S wi tch ing Frequ ency
To determine the switching frequency for a design, the data
input values to the circuit must be clearly understood. The
following guidelines represent worst-case scenarios; these
can be used to generally predict the upper limits of power
dissipation.
Logic Modules (m)
= 80% of
Combinatorial
Modules
Inputs Switching (n)
= # of Inputs/4
Outputs Switching (p)
= # of Outputs/4
First Routed Array Clock Loads
(q1)
= 40% of Sequential
Modules
Second Routed Array Clock
Loads (q2)
= 40% of Sequential
Modules
Load Capacitance (CL)
= 35 pF
Logic Modules (m)
= 80% of
Combinatorial
Modules
Average Logic Module Switching
Rate (fm)
= F/10
Average Input Switching Rate
(fn)
= F/5
Average Output Switching Rate
(fp)
= F/10
Average First Routed Array
Clock Rate (fq1)
= F
Average Second Routed Array
Clock Rate (fq2)
= F/2
40 M X Ti m i ng M od e l *
Input Delay
Internal Delays
Predicted
Routing
Delays
I/O Module
Output Delay
I/O Module
tINYL = 0.62 ns t
IRD2 = 2.59 ns
Logic Module
tDLH = 3.32 ns
tIRD1 = 2.09 ns
tIRD4 = 3.64 ns
tIRD8 = 5.73 ns
Array
Clock
tCKH = 4.55 ns
tPD = 1.24 ns
tCO = 1.24 ns
tRD1 = 1.28 ns
tRD2 = 1.80 ns
tRD4 = 2.33 ns
tRD8 = 4.93 ns
FO = 128
FMAX = 180 MHz
* Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.
20
v5.0
tENHZ = 7.92 ns
4 0 M X a n d 4 2 M X F PG A F a m il ie s
42 M X Ti m i ng M od e l *
Input Delays
Internal Delays
I/O Module
tINYL = 1.16 ns
Predicted
Routing
Delays
Output Delays
I/O Module
tIRD1 =
2.24 ns†
Combinatorial
Logic Module
D
Q
tDLH = 2.70 ns
tRD1 = 0.80 ns
tRD2 = 1.00 ns
tRD4 = 1.50 ns
tRD8 = 2.50 ns
tPD = 1.55 ns
G
Sequential
Logic Module
tINH = 0.00 ns
tINSU = 0.54 ns
tINGL = 1.40 ns
Combinatorial
Logic
included
in tSUD
Array
Clocks
tCKH = 2.70 ns
FMAX = 245 MHz
FO = 32
D
I/O Module
tDLH = 2.70 ns
D
Q
tRD1 = 0.80 ns
Q
tENHZ = 5.40 ns
G
tSUD = 0.36 ns
tHD = 0.00 ns
tCO = 1.37 ns
tOUTH = 0.00 ns
tOUTSU = 0.30 ns
tGLH = 2.90 ns
tLCO = 5.60 ns (light loads, pad-to-pad)
*Values are shown for A42MX09 ‘–2’ at 5.0V worst-case commercial conditions
† Input module predicted routing delay
v5.0
21
40MX and 42MX FPGA Families
42 M X Ti m i ng M od e l ( Lo g i c F un c t i on s us i ng Q ua dr an t C l o ck s) *
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
tINPY = 1.14 ns t
IRD1 = 2.18 ns
I/O Module
Combinatorial
Module
D
Q
tDLH = 2.84 ns
tRD1 = 1.04 ns
tRD2 = 1.42 ns
tRD4 = 2.18 ns
tPD = 1.46 ns
G
tINH = 0.00 ns
tINSU = 0.53 ns
tINGO = 1.55 ns
Decode
Module
tRDD = 0.38 ns
tPDD = 1.78 ns
I/O Module
tDLH = 2.84 ns
Sequential
Logic Module
Combinatorial
Logic
included
in tSUD
D
tRD1 = 1.04 ns
Q
tENHZ = 5.80 ns
tCO = 1.43 ns
tCKH = 3.03 ns**
FMAX = 163 MHz
* Preliminary values are shown for A42MX36 ‘–2’ at 5.0V worst-case commercial conditions
** Load-dependent
22
D
G
tSUD = 0.30 ns
tHD = 0.00 ns
Quadrant
Clocks
Q
v5.0
tLH = 0.00 ns
tLSU = 0.53 ns
tGHL= 3.27 ns
4 0 M X a n d 4 2 M X F PG A F a m il ie s
42 M X Ti m i ng M od e l ( SR A M F un ct i on s) *
Input Delays
I/O Module
tINPY = 1.14 ns t
IRD1 = 2.18 ns
D
Q
G
tINSU = 0.53 ns
tINH = 0.00 ns
tINGO = 1.55 ns
Predicted
Routing
Delays
WD [7:0]
WRAD [5:0]
Array
Clocks
I/O Module
tDLH = 2.84 ns
RD [7:0]
RDAD [5:0]
tRD1 = 1.04 ns
BLKEN
REN
D
WEN
WCLK
RCLK
G
tADSU = 1.80 ns
tADH = 0.00 ns
tWENSU = 2.90 ns
tBENS = 2.90 ns
tADSU = 1.80 ns
tADH = 0.00 ns
tRENSU = 0.80 ns
tRCO = 3.80 ns
Q
tGHL= 5.50 ns
tLSU = 0.30 ns
tLH = 0.00 ns
FMAX = 151 MHz
*Values are shown for A42MX36 ‘–2’ at 5.0V worst-case commercial conditions.
v5.0
23
40MX and 42MX FPGA Families
P ar am e t e r M ea s ur e m e nt
O ut put Buf f er De lay s
E
D
In
50%
PAD
VOL
50%
VOH
E
1.5V
1.5V
PAD To AC test loads (shown below)
TRIBUFF
50%
VCCI
E
50%
1.5V
PAD
PAD
GND
10%
VOL
tDLH
tENZL
tDHL
50%
VOH
50%
tENHZ
tENZH
tENLZ
90%
1.5V
A C Tes t Loa ds
Load 1
(Used to measure propagation delay)
Load 2
(Used to measure rising/falling edges)
VCCI
GND
To the output under test
35 pF
R to VCCI for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 kΩ
To the output under test
35 pF
Inp ut Bu ff er D ela ys
PAD
Modu le Del ay s
S
A
B
Y
INBUF
S, A or B
3V
PAD
1.5V 1.5V
VCCI
Y
GND
24
50%
50%
tPLH
50%
50%
tINYH
50% 50%
Y
0V
Y
tPHL
Y
50%
tPHL
tINYL
v5.0
50%
tPLH
4 0 M X a n d 4 2 M X F PG A F a m il ie s
S eq u en t i a l M od ul e T i m i ng C ha r a ct er i st i c s
Fl ip- Fl ops and La tch es
D
E
CLK
Y
PRE
CLR
(Positive Edge-Triggered)
tHD
1
D
tSUD
tA
tWCLKA
G, CLK
tSUENA
tWCLKI
tHENA
E
tCO
Q
tRS
PRE, CLR
tWASYN
Note:
D represents all data functions involving A, B, and S for multiplexed flip-flops.
v5.0
25
40MX and 42MX FPGA Families
Se q ue nt i al T i m i n g C h ar ac t er i st i c s (continued)
Inpu t Buffer Lat ch es
PAD
DATA
IBDL
G
PAD
CLK
CLKBUF
DATA
tINH
G
tINSU
tHEXT
CLK
tSUEXT
Out put B uffer L at ches
D
PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
26
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
D ec od e M od ul e T i m i ng
A
B
C
D
E
F
G
A–G, H
Y
H
50%
Y
tPHL
tPLH
SR A M T i m i ng C ha r a ct er i s t i c s
Read Port
Write Port
WRAD [5:0]
BLKEN
WEN
RDAD [5:0]
RAM Array
LEW
32x8 or 64x4
(256 Bits)
WCLK
REN
RCLK
WD [7:0]
RD [7:0]
v5.0
27
40MX and 42MX FPGA Families
D ua l - Po r t S R A M Ti m i n g W av ef or m s
42MX S R AM Wr it e O per at ion
tRCKHL
tRCKHL
WCLK
tADSU
WD[7:0]
WRAD[5:0]
tADH
Valid
tWENSU
tWENH
tBENSU
tBENH
WEN
BLKEN
Note:
Valid
Identical timing for falling edge clock.
42MX S R AM S ync hronou s Rea d Ope ra ti on
tCKHL
tRCKHL
RCLK
tRENSU
tRENH
tADSU
tADH
REN
Valid
RDAD[5:0]
tRCO
tDOH
RD[7:0]
Note:
28
Old Data
Identical timing for falling edge clock.
v5.0
New Data
4 0 M X a n d 4 2 M X F PG A F a m il ie s
42MX S R AM As yn chrono us Re ad Op er ati on— Typ e 1
(Read Address Controlled)
tRDADV
RDAD[5:0]
ADDR1
ADDR2
tRPD
tDOH
Data 1
RD[7:0]
Data 2
42MX S R AM As yn chrono us Re ad Op er ati on— Typ e 2
(Write Address Controlled)
WEN
WD[7:0]
WRAD[5:0]
BLKEN
tWENSU
tWENH
Valid
tADH
tADSU
WCLK
tRPD
tDOH
RD[7:0]
Old Data
v5.0
New Data
29
40MX and 42MX FPGA Families
Pr ed i ct ab l e Pe rf o r m a nc e:
Ti g h t D el a y D i s t r i b ut i on s
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of
inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer routing tracks.
The MX FPGAs deliver a tight fanout delay distribution,
which is achieved in two ways: by decreasing the delay of the
interconnect elements and by decreasing the number of
interconnect elements per path.
Actel’s patented antifuse offers a very low
resistive/capacitive interconnect. The antifuses, fabricated
in 0.45 µ lithography, offer nominal levels of 100 ¾
resistance and 7.0 femtofarad (fF) capacitance per antifuse.
MX fanout distribution is also tight due to the low number of
antifuses required for each interconnect path. The
proprietary architecture limits the number of antifuses per
path to a maximum of four, with 90 percent of interconnects
using only two antifuses.
Ti m i ng C ha r a ct e r i s t i c s
Lo ng T r ack s
Some nets in the design use long tracks, which are special
routing resources that span multiple rows, columns, or
modules. Long tracks employ three and sometimes four
antifuse connections, which increase capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6 percent of
nets in a fully utilized device require long tracks. Long
tracks add approximately a 3 ns to a 6 ns delay, which is
represented statistically in higher fanout (FO=8) routing
delays in the data sheet specifications section, beginning on
page 34.
T im i ng Der at in g
A timing derating factor of 0.45 is used to reflect best-case
processing. Note that this factor is relative to the standard
speed timing parameters and must be multiplied by the
appropriate voltage and temperature derating factors for a
given application.
T i m i n g D e r at i ng Fa c t or s
C om m er cial t o Indus t ri al
Industrial
(Commercial Specification) x
Max.
0.69
1.11
C om m er cial W o rs t- Ca se t o T y pica l
Device timing characteristics fall into three categories:
family-dependent, device-dependent, and design-dependent.
The input and output buffer characteristics are common to
all MX devices. For mixed voltage of the A42MX devices, the
timing numbers are defined in the 3.3V section for I/Os while
for the internal logic resources, the timing numbers are
defined in the 5.0V section. Internal routing delays are
device-dependent. Design dependency means actual delays
are not determined until after place-and-route of the user’s
design is complete. Delay values may then be determined by
using the Designer Series utility or by performing simulation
with post-layout delays.
Commerical Typical
(TJ = 25°C, VCC = 5.0V)
(Commercial, Worst-Case
Condition) x
Note:
Cr it ic al Net s and Ty pi cal Net s
Propagation delays in this data sheet apply to typical nets.
The abundant routing resources in the MX architecture
allows for deterministic timing using Actel’s Designer Series
development tools, which include TDPR, a timing-driven
place-and-route tool. Using Timer, the designer can specify
timing-critical nets and system clock frequency. Using these
timing specifications, the place-and-route software
optimizes the layout of the design to meet the user’s
specifications.
30
Min.
v5.0
0.85
This derating factor applies to all routing and propagation
delays.
4 0 M X a n d 4 2 M X F PG A F a m il ie s
42 M X Te m p era t u r e an d Vo l t a ge D era ti n g Fa ct ors
(Normalized to T J = 25°C, V CCA /V C CI = 5.0V)
Temperature
42MX
Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
4.50
0.93
0.95
1.05
1.09
1.25
1.29
1.41
4.75
0.88
0.90
1.00
1.03
1.18
1.22
1.34
5.00
0.85
0.87
0.96
1.00
1.15
1.18
1.29
5.25
0.84
0.86
0.95
0.97
1.12
1.14
1.28
5.50
0.83
0.85
0.94
0.96
1.10
1.13
1.26
(Normalized to TJ = 25°C, VCCA/VCCI = 5.0V)
1.50
Derating Factor
1.40
1.30
–55 C
1.20
–40 C
1.10
0C
1.00
25 C
0.90
70 C
0.80
85 C
0.70
125 C
0.60
4.50
4.75
5.00
5.25
5.50
Voltage (V)
Note:
This derating factor applies to all routing and propagation delays.
v5.0
31
40MX and 42MX FPGA Families
40 M X Te m p era t u r e an d V o l t a ge D era ti n g Fa ct ors
(Normalized to T J = 25°C, V CCA /V C CI = 5.0V)
Temperature
40MX
Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
4.50
0.89
0.93
1.02
1.09
1.25
1.31
1.45
4.75
0.84
0.88
0.97
1.03
1.18
1.24
1.37
5.00
0.82
0.85
0.94
1.00
1.15
1.20
1.33
5.25
0.80
0.82
0.91
0.97
1.12
1.16
1.29
5.50
0.79
0.82
0.90
0.96
1.10
1.15
1.28
40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA/VCCI = 5.0V)
1.50
Derating Factor
1.40
1.30
–55 C
1.20
–40 C
1.10
0C
1.00
25 C
0.90
70 C
0.80
85 C
0.70
125 C
0.60
4.50
4.75
5.00
Voltage (V)
Note:
32
This derating factor applies to all routing and propagation delays.
v5.0
5.25
5.50
4 0 M X a n d 4 2 M X F PG A F a m il ie s
PC I S ys t e m T i m i ng S pe ci f i ca t i o n
PC I M o d el s
Table 3 and Table 4 list the critical PCI timing parameters
and the corresponding timing parameter for the MX
PCI-compliant devices.
Actel provides synthesizable VHDL and Verilog-HDL models
for a PCI Target interface, a PCI Target and Target+DMA
Master interface. Contact your Actel sales representative
for more details.
Table 3 • Clock Specification for 33 MHz PCI
PCI
Symbol
Parameter
TCYC
A42MX24
A42MX36
Min.
Max.
Min.
Max.
Min.
Max.
Units
CLK Cycle Time
30
—
4.0
—
4.0
—
ns
THIGH
CLK High Time
11
—
1.9
—
1.9
—
ns
TLOW
CLK Low Time
11
—
1.9
—
1.9
—
ns
Table 4 • Timing Parameters for 33 MHz PCI
PCI
Symbol
Parameter
TVAL
A42MX24
A42MX36
Min.
Max.
Min.
Max.
Min.
Max.
Units
CLK to Signal Valid—Bused Signals
2
11
2.0
9.0
2.0
9.0
ns
TVAL(PTP)
CLK to Signal Valid—Point-to-Point
2
12
2.0
9.0
2.0
9.0
ns
TON
Float to Active
2
—
2.0
4.0
2.0
4.0
ns
—
8.31
ns
TOFF
Active to Float
—
28
—
8.31
TSU
Input Set-Up Time to CLK—Bused Signals
7
—
1.5
—
1.5
—
ns
TSU(PTP)
Input Set-Up Time to CLK—Point-to-Point
10, 12
—
1.5
—
1.5
—
ns
TH
Input Hold to CLK
0
—
0
—
0
—
ns
Note:
1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
v5.0
33
40MX and 42MX FPGA Families
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
ns
Logic Module Propagation Delays
tPD1
Single Module
1.2
1.4
1.6
1.9
2.7
tPD2
Dual-Module Macros
2.7
3.1
3.5
4.1
5.7
ns
tCO
Sequential Clock-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.4
1.6
1.9
2.7
ns
Logic Module Predicted Routing Delays
1
tRD1
FO=1 Routing Delay
1.3
1.5
1.7
2.0
2.8
ns
tRD2
FO=2 Routing Delay
1.8
2.1
2.4
2.8
3.9
ns
tRD3
FO=3 Routing Delay
2.3
2.7
3.0
3.6
5.0
ns
tRD4
FO=4 Routing Delay
2.9
3.3
3.7
4.4
6.1
ns
tRD8
FO=8 Routing Delay
4.9
5.7
6.5
7.6
10.6
ns
Logic Module Sequential
tSUD
Timing2
Flip-Flop (Latch) Data Input Set-Up
3.1
3.5
4.0
4.7
6.6
ns
3
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
3.3
3.8
4.3
5.0
7.0
ns
Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tA
Flip-Flop Clock Input Period
4.8
5.6
6.3
7.5
10.4
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
tHD
tWASYN
181
168
154
134
80
MHz
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.
34
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
tINYL
Pad-to-Y LOW
Input Module Predicted Routing
0.7
0.8
0.9
1.1
1.5
ns
0.6
0.7
0.8
1.0
1.3
ns
Delays1
tIRD1
FO=1 Routing Delay
2.1
2.4
2.2
3.2
4.5
ns
tIRD2
FO=2 Routing Delay
2.6
3.0
3.4
4.0
5.6
ns
tIRD3
FO=3 Routing Delay
3.1
3.6
4.1
4.8
6.7
ns
tIRD4
FO=4 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD8
FO=8 Routing Delay
5.7
6.6
7.5
8.8
12.4
ns
Global Clock Network
tCKH
Input Low to HIGH
FO = 16
FO = 128
4.6
4.6
5.3
5.3
6.0
6.0
7.0
7.0
9.8
9.8
ns
tCKL
Input High to LOW
FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.4
7.4
10.4
10.4
ns
Minimum Pulse Width HIGH FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
tPWL
Minimum Pulse Width LOW FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.01
3.4
3.6
4.8
5.1
tCKSW
Maximum Skew
tPWH
tP
fMAX
Minimum Period
Maximum Frequency
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
0.4
0.5
4.7
4.8
0.5
0.6
5.4
5.6
188
181
0.5
0.7
6.1
6.3
175
168
0.6
0.8
7.2
7.5
160
154
ns
ns
0.8
1.2
10.0
10.4
139
134
ns
ns
83
80
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
35
40MX and 42MX FPGA Families
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
3.3
3.8
4.3
5.1
7.2
ns
tDHL
Data-to-Pad LOW
4.0
4.6
5.2
6.1
8.6
ns
tENZH
Enable Pad Z to HIGH
3.7
4.3
4.9
5.8
8.0
ns
tENZL
Enable Pad Z to LOW
4.7
5.4
6.1
7.2
10.1
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.1
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH2
Delta LOW to HIGH
0.02
0.02
0.03
0.03
0.04
ns/pF
dTHL2
Delta HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
CMOS Output Module
Timing1
tDLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5
ns
tDHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
tENZH
Enable Pad Z to HIGH
3.4
3.9
4.4
5.2
7.3
ns
tENZL
Enable Pad Z to LOW
4.9
5.6
6.4
7.5
10.5
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.0
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
2
Delta LOW to HIGH
0.03
0.04
0.04
0.05
0.07
ns/pF
dTHL
2
Delta HIGH to LOW
0.02
0.02
0.03
0.03
0.04
ns/pF
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
36
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
3.7
ns
Logic Module Propagation Delays
tPD1
Single Module
tPD2
Dual-Module Macros
3.7
4.3
4.9
5.7
8.0
ns
tCO
Sequential Clock-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tGO
Latch G-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.7
2.0
2.3
2.7
3.7
ns
1.7
Logic Module Predicted Routing Delays
2.0
2.3
2.7
1
tRD1
FO=1 Routing Delay
2.0
2.2
2.5
3.0
4.2
ns
tRD2
FO=2 Routing Delay
2.7
3.1
3.5
4.1
5.7
ns
tRD3
FO=3 Routing Delay
3.4
3.9
4.4
5.2
7.3
ns
tRD4
FO=4 Routing Delay
4.2
4.8
5.4
6.3
8.9
ns
tRD8
FO=8 Routing Delay
7.1
8.2
9.2
10.9
15.2
ns
Logic Module Sequential
tSUD
Timing2
Flip-Flop (Latch) Data Input Set-Up
4.3
4.9
5.6
6.6
9.2
ns
3
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
4.3
4.9
5.6
6.6
9.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
4.6
5.3
6.0
7.0
9.8
ns
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
5.3
6.0
7.0
9.8
ns
tA
Flip-Flop Clock Input Period
6.8
7.8
8.9
10.4
14.6
ns
fMAX
Flip-Flop (Latch) Clock
Frequency (FO = 128)
tHD
tWASYN
109
101
92
80
48
MHz
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.
v5.0
37
40MX and 42MX FPGA Families
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
tINYL
Pad-to-Y LOW
Input Module Predicted Routing
1.0
1.1
1.3
1.5
2.1
ns
0.9
1.0
1.1
1.3
1.9
ns
Delays1
tIRD1
FO=1 Routing Delay
2.9
3.4
3.8
4.5
6.3
ns
tIRD2
FO=2 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD3
FO=3 Routing Delay
4.4
5.0
5.7
6.7
9.4
ns
tIRD4
FO=4 Routing Delay
5.1
5.9
6.7
7.8
11.0
ns
tIRD8
FO=8 Routing Delay
8.0
9.26
10.5
12.6
17.3
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 16
FO = 128
6.4
6.4
7.4
7.4
8.3
8.3
9.8
9.8
13.7
13.7
ns
tCKL
Input HIGH to LOW
FO = 16
FO = 128
6.7
6.7
7.8
7.8
8.8
8.8
10.4
10.4
14.5
14.5
ns
Minimum Pulse Width
HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
tPWL
Minimum Pulse Width
LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
tCKSW
Maximum Skew
FO = 16
FO = 128
tPWH
tP
fMAX
Minimum Period
Maximum Frequency
FO = 16
FO = 128
FO = 16
FO = 128
0.6
0.8
6.5
6.8
0.6
0.9
7.5
7.8
113
109
0.7
1.0
8.5
8.9
105
101
0.8
1.2
10.1
10.4
96
92
ns
ns
1.2
1.6
14.1
14.6
83
80
ns
ns
50
48
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
38
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 2 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
4.7
5.4
6.1
7.2
10.0
ns
tDHL
Data-to-Pad LOW
5.6
6.4
7.3
8.6
12.0
ns
tENZH
Enable Pad Z to HIGH
5.2
6.0
6.8
8.1
11.3
ns
tENZL
Enable Pad Z to LOW
6.6
7.6
8.6
10.1
14.1
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH2
Delta LOW to HIGH
0.03
0.03
0.04
0.04
0.06
ns/pF
dTHL2
Delta HIGH to LOW
0.04
0.04
0.05
0.06
0.08
ns/pF
CMOS Output Module
Timing1
tDLH
Data-to-Pad HIGH
5.5
6.4
7.2
8.5
11.9
ns
tDHL
Data-to-Pad LOW
4.8
5.5
6.2
7.3
10.2
ns
tENZH
Enable Pad Z to HIGH
4.7
5.5
6.2
7.3
10.2
ns
tENZL
Enable Pad Z to LOW
6.8
7.9
8.9
10.5
14.7
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
2
Delta LOW to HIGH
0.05
0.05
0.06
0.07
0.10
ns/pF
dTHL
2
Delta HIGH to LOW
0.03
0.03
0.04
0.04
0.06
ns/pF
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
v5.0
39
40MX and 42MX FPGA Families
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max. Units
Logic Module Propagation Delays
tPD1
Single Module
tPD2
Dual-Module Macros
2.3
3.1
3.5
4.1
5.7
ns
tCO
Sequential Clock-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.4
1.6
1.9
2.7
ns
1.2
Logic Module Predicted Routing Delays
1.4
1.6
1.9
2.7
ns
1
tRD1
FO=1 Routing Delay
1.2
1.6
1.8
2.1
3.0
ns
tRD2
FO=2 Routing Delay
1.9
2.2
2.5
2.9
4.1
ns
tRD3
FO=3 Routing Delay
2.4
2.8
3.2
3.7
5.2
ns
tRD4
FO=4 Routing Delay
2.9
3.4
3.9
4.5
6.3
ns
tRD8
FO=8 Routing Delay
5.0
5.8
6.6
7.8
10.9
ns
Logic Module Sequential
tSUD
Timing2
Flip-Flop (Latch) Data Input Set-Up
3.1
3.5
4.0
4.7
6.6
ns
3
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
3.3
3.8
4.3
5.0
7.0
ns
Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tA
Flip-Flop Clock Input Period
4.8
5.6
6.3
7.5
10.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
(FO = 128)
tHD
tWASYN
181
167
154
134
80
MHz
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.
40
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
tINYL
Pad-to-Y LOW
Input Module Predicted Routing
0.7
0.8
0.9
1.1
1.5
ns
0.6
0.7
0.8
1.0
1.3
ns
Delays1
tIRD1
FO=1 Routing Delay
2.1
2.4
2.2
3.2
4.5
ns
tIRD2
FO=2 Routing Delay
2.6
3.0
3.4
4.0
5.6
ns
tIRD3
FO=3 Routing Delay
3.1
3.6
4.1
4.8
6.7
ns
tIRD4
FO=4 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD8
FO=8 Routing Delay
5.7
6.6
7.5
8.8
12.4
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 16
FO = 128
4.6
4.6
5.3
5.3
6.0
6.0
7.1
7.1
9.9
9.9
ns
tCKL
Input HIGH to LOW
FO = 16
FO = 128
4.8
4.8
5.6
5.6
6.3
6.3
7.5
7.5
10.4
10.4
ns
Minimum Pulse Width HIGH FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
tPWL
Minimum Pulse Width LOW FO = 16
FO = 128
2.2
2.4
2.6
2.7
2.9
3.1
3.4
3.6
4.8
5.1
tCKSW
Maximum Skew
tPWH
tP
fMAX
Minimum Period
Maximum Frequency
FO = 16
FO = 128
FO = 16
FO = 128
FO = 16
FO = 128
0.4
0.5
4.7
4.8
0.5
0.6
5.4
5.6
188
181
0.5
0.7
6.1
6.3
175
168
0.6
0.8
7.2
7.5
160
154
ns
ns
0.8
1.2
10.1
10.4
139
134
ns
ns
83
80
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
41
40MX and 42MX FPGA Families
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
3.3
3.8
4.3
5.1
7.2
ns
tDHL
Data-to-Pad LOW
4.0
4.6
5.2
6.1
8.6
ns
tENZH
Enable Pad Z to HIGH
3.7
4.3
4.9
5.8
8.1
ns
tENZL
Enable Pad Z to LOW
4.7
5.4
6.1
7.2
10.1
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.1
ns
tENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH2
Delta LOW to HIGH
0.02
0.02
0.03
0.03
0.04
ns/pF
dTHL2
Delta HIGH to LOW
0.02
0.03
0.03
0.04
0.06
ns/pF
CMOS Output Module
Timing1
tDLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.1
8.5
ns
tDHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
tENZH
Enable Pad Z to HIGH
3.4
3.9
4.4
5.2
7.3
ns
tENZL
Enable Pad Z to LOW
4.9
5.6
6.4
7.5
10.5
ns
tENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.1
ns
tENLZ
Enable Pad LOW to Z
5.0
6.8
7.7
9.0
12.6
ns
dTLH
2
Delta LOW to HIGH
0.03
0.04
0.04
0.05
0.07
ns/pF
dTHL
2
Delta HIGH to LOW
0.02
0.02
0.03
0.03
0.04
ns/pF
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
42
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
3.7
ns
Logic Module Propagation Delays
tPD1
Single Module
tPD2
Dual-Module Macros
3.7
4.3
4.9
5.7
8.0
ns
tCO
Sequential Clock-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tGO
Latch G-to-Q
1.7
2.0
2.3
2.7
3.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.7
2.0
2.3
2.7
3.7
ns
1.7
2.0
2.3
2.7
1
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
1.9
2.2
2.5
3.0
4.2
ns
tRD2
FO=2 Routing Delay
2.7
3.1
3.5
4.1
5.7
ns
tRD3
FO=3 Routing Delay
3.4
3.9
4.4
5.2
7.3
ns
tRD4
FO=4 Routing Delay
4.1
4.8
5.4
6.3
8.9
ns
tRD8
FO=8 Routing Delay
7.1
8.1
9.2
10.9
15.2
ns
Logic Module Sequential
tSUD
Timing2
Flip-Flop (Latch) Data Input Set-Up
4.3
5.0
5.6
6.6
9.2
ns
3
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
4.3
5.0
5.6
6.6
9.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
4.6
5.3
5.6
7.0
9.8
ns
Flip-Flop (Latch)
Asynchronous Pulse Width
4.6
5.3
5.6
7.0
9.8
ns
tA
Flip-Flop Clock Input Period
6.8
7.8
8.9
10.4
14.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
(FO = 128)
tHD
tWASYN
109
101
92
80
48
MHz
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Series or later Timer to check the hold time for this macro.
v5.0
43
40MX and 42MX FPGA Families
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
tINYL
Pad-to-Y LOW
Input Module Predicted Routing
1.0
1.1
1.3
1.5
2.1
ns
0.9
1.0
1.1
1.3
1.9
ns
Delays1
tIRD1
FO=1 Routing Delay
2.9
3.34
3.8
4.5
6.3
ns
tIRD2
FO=2 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD3
FO=3 Routing Delay
4.4
5.0
5.7
6.7
9.4
ns
tIRD4
FO=4 Routing Delay
5.1
5.9
6.7
7.8
11.0
ns
tIRD8
FO=8 Routing Delay
8.0
9.3
10.5
12.4
17.2
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 16
FO = 128
6.4
6.4
7.4
7.4
8.4
8.4
9.9
9.9
13.8
13.8
ns
tCKL
Input HIGH to LOW
FO = 16
FO = 128
6.8
6.8
7.8
7.8
8.9
8.9
10.4
10.4
14.6
14.6
ns
Minimum Pulse Width
HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
tPWL
Minimum Pulse Width
LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
tCKSW
Maximum Skew
FO = 16
FO = 128
tPWH
tP
fMAX
Minimum Period
Maximum Frequency
FO = 16
FO = 128
FO = 16
FO = 128
0.6
0.8
6.5
6.8
0.6
0.9
7.5
7.8
113
109
0.7
1.0
8.5
8.9
105
101
0.8
1.2
10.1
10.4
96
92
ns
ns
1.2
1.6
14.1
14.6
83
80
ns
ns
50
48
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
44
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 40 M X0 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Wor st - Cas e C om m erci al Co ndit i ons , V C C = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
4.7
5.4
6.1
7.2
10.0
ns
tDHL
Data-to-Pad LOW
5.6
6.4
7.3
8.6
12.0
ns
tENZH
Enable Pad Z to HIGH
5.2
6.0
6.9
8.1
11.3
ns
tENZL
Enable Pad Z to LOW
6.6
7.6
8.6
10.1
14.1
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH2
Delta LOW to HIGH
0.03
0.03
0.04
0.04
0.06
ns/pF
dTHL2
Delta HIGH to LOW
0.04
0.04
0.05
0.06
0.08
ns/pF
CMOS Output Module
Timing1
tDLH
Data-to-Pad HIGH
5.5
6.4
7.2
8.5
11.9
ns
tDHL
Data-to-Pad LOW
4.8
5.5
6.2
7.3
10.2
ns
tENZH
Enable Pad Z to HIGH
4.7
5.5
6.2
7.3
10.2
ns
tENZL
Enable Pad Z to LOW
6.8
7.9
8.9
10.5
14.7
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
2
Delta LOW to HIGH
0.05
0.05
0.06
0.07
0.10
ns/pF
dTHL
2
Delta HIGH to LOW
0.03
0.03
0.04
0.04
0.06
ns/pF
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
v5.0
45
40MX and 42MX FPGA Families
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
Single Module
1.2
1.3
1.5
1.8
2.5
ns
tCO
Sequential Clock-to-Q
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.8
2.6
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.6
1.8
2.1
2.9
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
0.7
0.8
0.9
1.0
1.4
ns
tRD2
FO=2 Routing Delay
0.9
1.0
1.2
1.4
1.9
ns
tRD3
FO=3 Routing Delay
1.2
1.3
1.5
1.7
2.4
ns
tRD4
FO=4 Routing Delay
1.4
1.5
1.7
2.0
2.9
ns
tRD8
FO=8 Routing Delay
2.3
2.6
2.9
3.4
4.8
ns
Logic Module Sequential Timing
3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.4
0.5
0.5
0.6
0.8
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
3.4
3.8
4.3
5.0
7.0
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
4.5
4.9
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
3.5
3.8
4.3
5.1
7.1
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.3
0.3
0.4
0.4
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.3
0.3
0.4
0.4
0.6
ns
fMAX
Flip-Flop (Latch) Clock
Frequency
tWASYN
268
244
224
195
117
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
46
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V C C = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.0
1.2
1.3
1.6
2.2
ns
tINYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7
ns
tINGH
G to Y HIGH
1.3
1.4
1.6
1.9
2.7
ns
tINGL
G to Y LOW
1.3
1.4
1.6
1.9
2.7
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.0
2.2
2.5
3.0
4.2
ns
tIRD2
FO=2 Routing Delay
2.3
2.5
2.9
3.4
4.7
ns
tIRD3
FO=3 Routing Delay
2.5
2.8
3.2
3.7
5.2
ns
tIRD4
FO=4 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tIRD8
FO=8 Routing Delay
3.7
4.1
4.7
5.5
7.7
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
2.4
2.7
2.7
3.0
3.0
3.4
3.6
4.0
5.0
5.5
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
3.5
3.9
3.9
4.3
4.4
4.9
5.2
5.7
7.3
8.0
ns
ns
tPWH
Minimum Pulse Width
HIGH
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
tPWL
Minimum Pulse Width
LOW
FO = 32
FO = 256
1.2
1.3
1.4
1.5
1.5
1.7
1.8
2.0
2.5
2.7
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 256
2.3
2.2
2.6
2.4
3.0
3.3
3.5
3.9
4.9
5.5
ns
ns
tP
Minimum Period
FO = 32
FO = 256
3.4
3.7
3.7
4.1
4.0
4.5
4.7
5.2
7.8
8.6
ns
ns
fMAX
Maximum Frequency
FO = 32
FO = 256
0.3
0.3
0.3
0.3
296
268
269
244
0.4
0.4
247
224
0.5
0.5
215
195
0.6
0.6
129
117
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
47
40MX and 42MX FPGA Families
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
2.5
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tENZH
Enable Pad Z to HIGH
2.6
2.9
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.2
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
4.9
5.4
6.2
7.3
10.2
ns
tENLZ
Enable Pad LOW to Z
5.3
5.9
6.7
7.9
11.1
ns
tGLH
G-to-Pad HIGH
2.6
2.9
3.3
3.8
5.3
ns
tGHL
G-to-Pad LOW
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
2.6
2.9
5.2
3.3
5.8
3.8
6.6
5.3
7.7
10.8
ns
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
7.4
8.2
9.3
10.9
15.3
ns
dTLH2
Capacity Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
dTHL2
Capacity Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07
ns/pF
CMOS Output Module Timing
1
tDLH
Data-to-Pad HIGH
2.4
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tENZH
Enable Pad Z to HIGH
2.7
2.9
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.2
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
4.9
5.4
6.2
7.3
10.2
ns
tENLZ
Enable Pad LOW to Z
5.3
5.9
6.7
7.9
11.1
ns
tGLH
G-to-Pad HIGH
4.2
4.6
5.2
6.1
8.6
ns
tGHL
G-to-Pad LOW
4.2
4.6
5.2
6.1
8.6
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
5.2
5.8
6.6
7.7
10.8
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
7.4
8.2
9.3
10.9
15.3
ns
2
Capacity Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
dTHL2
Capacity Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07
ns/pF
dTLH
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
48
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 3. 0V, T J = 7 0°C )
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
1.6
1.8
2.1
2.5
3.5
ns
tCO
Sequential Clock-to-Q
1.8
2.0
2.3
2.7
3.8
ns
tGO
Latch G-to-Q
1.7
1.9
2.1
2.5
3.5
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.0
2.2
2.5
2.9
4.1
ns
Logic Module Predicted Routing
Delays2
tRD1
FO=1 Routing Delay
1.0
1.1
1.2
1.4
2.0
ns
tRD2
FO=2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD3
FO=3 Routing Delay
1.6
1.8
2.0
2.4
3.3
ns
tRD4
FO=4 Routing Delay
1.9
2.1
2.4
2.9
4.0
ns
tRD8
FO=8 Routing Delay
3.2
3.6
4.1
4.8
6.7
ns
Logic Module Sequential Timing 3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.5
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.6
0.7
0.8
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
4.7
5.3
6.0
7.0
9.8
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
6.2
6.9
7.8
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
5.0
5.6
6.2
7.1
9.9
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
fMAX
Flip-Flop (Latch) Clock
Frequency
161
146
135
117
70
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
v5.0
49
40MX and 42MX FPGA Families
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V C C = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.8
2.17
3.0
ns
tINYL
Pad-to-Y LOW
1.2
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
1.8
2.0
2.3
2.7
3.7
ns
tINGL
G to Y LOW
1.8
2.0
2.3
2.7
3.7
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.8
3.2
3.6
4.2
5.9
ns
tIRD2
FO=2 Routing Delay
3.2
3.5
4.0
4.7
6.6
ns
tIRD3
FO=3 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD4
FO=4 Routing Delay
3.9
4.3
4.9
5.7
8.0
ns
tIRD8
FO=8 Routing Delay
5.2
5.8
6.6
7.7
10.8
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
4.1
4.5
4.5
5.0
5.1
5.6
6.0
6.7
8.4
9.3
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
5.0
5.4
5.5
6.0
6.2
6.8
7.3
8.0
10.2
11.2
ns
ns
tPWH
Minimum Pulse Width
HIGH
FO = 32
FO = 256
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
tPWL
Minimum Pulse Width
LOW
FO = 32
FO = 256
1.7
1.9
1.9
2.1
2.1
2.3
2.5
2.7
3.5
3.8
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 256
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 256
3.3
3.7
3.7
4.1
4.2
4.6
4.9
5.5
6.9
7.6
ns
ns
tP
Minimum Period
FO = 32
FO = 256
5.6
6.1
6.2
6.8
6.7
7.4
7.8
8.5
12.9
14.2
ns
ns
fMAX
Maximum Frequency
FO = 32
FO = 256
0.4
0.4
0.5
0.5
177
161
161
146
0.5
0.5
148
135
0.6
0.6
129
117
0.9
0.9
77
70
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
50
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X0 9 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
3.4
3.8
4.3
5.1
7.1
ns
tDHL
Data-to-Pad LOW
4.0
4.5
5.1
6.1
8.3
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.6
5.5
7.6
ns
tENZL
Enable Pad Z to LOW
4.1
4.5
5.1
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
6.9
7.6
8.6
10.2
14.2
ns
tENLZ
Enable Pad LOW to Z
7.5
8.3
9.4
11.1
15.5
ns
tGLH
G-to-Pad HIGH
5.8
6.5
7.3
8.6
12.0
ns
tGHL
G-to-Pad LOW
tLSU
I/O Latch Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.7
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
dTLH2
Capacity Loading, LOW to HIGH
dTHL2
Capacity Loading, HIGH to LOW
CMOS Output Module Timing
5.8
6.5
7.3
8.6
12.0
ns
9.7
10.9
12.9
18.0
ns
12.2
13.5
15.4
18.1
25.3
ns
0.00
0.00
0.00
0.10
0.01
ns/pF
0.09
0.10
0.10
0.10
0.10
ns/pF
1
tDLH
Data-to-Pad HIGH
3.4
3.8
5.5
6.4
9.0
ns
tDHL
Data-to-Pad LOW
4.1
4.5
4.2
5.0
7.0
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.6
5.5
7.6
ns
tENZL
Enable Pad Z to LOW
4.1
4.5
5.1
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
6.9
7.6
8.6
10.2
14.2
ns
tENLZ
Enable Pad LOW to Z
7.5
8.3
9.4
11.1
15.5
ns
tGLH
G-to-Pad HIGH
5.8
6.5
7.3
8.6
12.0
ns
tGHL
G-to-Pad LOW
5.8
6.5
7.3
8.6
12.0
ns
tLSU
I/O Latch Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.7
9.7
10.9
12.9
18.0
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
12.2
13.5
15.4
18.1
25.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10
ns/pF
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
v5.0
51
40MX and 42MX FPGA Families
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 4. 75V, T J = 70° C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
1.4
1.5
1.7
2.0
2.8
ns
tCO
Sequential Clock-to-Q
1.4
1.6
1.8
2.1
3.0
ns
tGO
Latch G-to-Q
1.4
1.5
1.7
2.0
2.8
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.6
1.7
2.0
2.3
3.3
ns
Logic Module Predicted Routing
Delays2
tRD1
FO=1 Routing Delay
0.8
0.9
1.0
1.2
1.6
ns
tRD2
FO=2 Routing Delay
1.0
1.2
1.3
1.5
2.1
ns
tRD3
FO=3 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD4
FO=4 Routing Delay
1.6
1.7
2.0
2.3
3.2
ns
tRD8
FO=8 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
Logic Module Sequential Timing3,4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
3.4
3.8
4.3
5.0
7.1
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
4.5
5.0
5.6
6.6
9.2
ns
tA
Flip-Flop Clock Input Period
6.8
7.6
8.6
10.1
14.1
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
fMAX
Flip-Flop (Latch) Clock
Frequency
215
1955
1795
1565
94
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
52
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.1
1.2
1.3
1.6
2.2
ns
tINYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7
ns
tINGH
G to Y HIGH
1.4
1.6
1.8
2.1
2.9
ns
tINGL
G to Y LOW
1.4
1.6
1.8
2.1
2.9
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
1.8
2.0
2.3
2.7
4.0
ns
tIRD2
FO=2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
tIRD3
FO=3 Routing Delay
2.3
2.6
3.0
3.5
4.9
ns
tIRD4
FO=4 Routing Delay
2.6
3.0
3.3
3.9
5.4
ns
tIRD8
FO=8 Routing Delay
3.6
4.0
4.6
5.4
7.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
6.0
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
3.8
4.5
4.2
5.0
4.8
5.6
5.6
6.6
7.8
9.2
ns
ns
tPWH
Minimum Pulse Width
HIGH
FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.59
4.7
5.4
6.6
7.6
ns
ns
tPWL
Minimum Pulse Width LOW FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
tCKSW
Maximum Skew
tSUEXT
Input Latch External Set-Up FO = 32
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
2.8
3.2
3.1
3.5
5.5
4.0
4.1
4.7
5.7
6.6
ns
ns
tP
Minimum Period
FO = 32
FO = 384
4.2
4.6
4.67
5.1
5.1
5.6
5.8
6.4
9.7
10.7
ns
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
FO = 32
FO = 384
0.3
0.3
0.4
0.4
237
215
215
195
0.4
0.4
198
179
0.5
0.5
172
156
0.7
0.7
103
94
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
53
40MX and 42MX FPGA Families
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
2.5
2.8
3.2
3.7
5.2
ns
tDHL
Data-to-Pad LOW
3.0
3.3
3.7
4.4
6.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.4
4.0
5.6
ns
tENZL
Enable Pad Z to LOW
3.0
3.3
3.8
4.4
6.2
ns
tENHZ
Enable Pad HIGH to Z
5.4
6.0
6.8
8.0
11.2
ns
tENLZ
Enable Pad LOW to Z
5.0
5.6
6.3
7.4
10.4
ns
tGLH
G-to-Pad HIGH
2.9
3.2
3.6
4.3
6.0
ns
tGHL
G-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
5.7
6.3
7.1
8.4
11.9
ns
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
dTLH
2
Capacitive Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
dTHL
2
Capacitive Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07
ns/pF
tACO
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
3.2
3.6
4.0
4.7
6.6
ns
tDHL
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.4
4.0
5.6
ns
tENZL
Enable Pad Z to LOW
3.0
3.3
3.8
4.4
6.2
ns
tENHZ
Enable Pad HIGH to Z
5.4
6.0
6.8
8.0
11.2
ns
tENLZ
Enable Pad LOW to Z
5.0
5.6
6.3
7.4
10.4
ns
tGLH
G-to-Pad HIGH
5.1
5.6
6.4
7.5
10.5
ns
tGHL
G-to-Pad LOW
5.1
5.6
6.4
7.5
10.5
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
5.7
6.3
7.1
8.4
11.9
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
2
Capacitive Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07
ns/pF
dTLH
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
54
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 3. 0V, T J = 7 0°C )
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
1.9
2.1
2.4
2.8
4.0
ns
tCO
Sequential Clock-to-Q
2.0
2.2
2.5
3.0
4.2
ns
tGO
Latch G-to-Q
1.9
2.1
2.4
2.8
4.0
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.2
2.4
2.8
3.3
4.6
ns
Logic Module Predicted Routing
Delays2
tRD1
FO=1 Routing Delay
1.1
1.2
1.4
1.6
2.3
ns
tRD2
FO=2 Routing Delay
1.5
1.6
1.8
2.1
3.0
ns
tRD3
FO=3 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
tRD4
FO=4 Routing Delay
2.2
2.4
2.7
3.2
4.5
ns
tRD8
FO=8 Routing Delay
3.6
4.0
4.5
5.3
7.5
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.5
0.5
0.6
0.7
0.9
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
4.8
5.3
6.0
7.1
9.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
6.2
6.9
7.9
9.2
12.9
ns
tA
Flip-Flop Clock Input Period
9.5
10.6
12.0
14.1
19.8
ns
tINH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.7
0.8
0.9
1.01
1.4
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.7
0.8
0.89
1.01
1.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
129
117
108
94
56
MHz
Notes:
1. For dual-module macros use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
v5.0
55
40MX and 42MX FPGA Families
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.9
2.2
3.1
ns
tINYL
Pad-to-Y LOW
1.1
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
2.0
2.2
2.5
2.9
4.1
ns
tINGL
G to Y LOW
2.0
2.2
2.5
2.9
4.1
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
tIRD2
FO=2 Routing Delay
2.9
3.2
3.7
4.3
6.1
ns
tIRD3
FO=3 Routing Delay
3.3
3.6
4.1
4.9
6.8
ns
tIRD4
FO=4 Routing Delay
3.6
4.0
4.6
5.4
7.6
ns
tIRD8
FO=8 Routing Delay
5.1
5.6
6.4
7.5
10.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.0
9.9
ns
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
tPWH
Minimum Pulse Width
HIGH
FO = 32
FO = 384
5.7
6.6
6.3
7.4
7.1
8.3
8.4
9.8
11.8
13.7
ns
ns
tPWL
Minimum Pulse Width
LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold FO = 32
FO = 384
3.9
4.5
4.3
4.9
4.9
5.6
5.7
6.6
8.0
9.2
ns
ns
tP
Minimum Period
FO = 32
FO = 384
7.0
7.7
7.8
8.6
8.4
9.3
9.7
10.7
16.2
17.8
ns
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
0.5
2.2
0.5
2.4
142
129
129
117
0.6
2.7
119
108
0.7
3.2
103
94
1.0
4.5
62
56
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
56
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X1 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
3.5
3.9
4.4
5.2
7.3
ns
tDHL
Data-to-Pad LOW
4.1
4.6
5.2
6.1
8.6
ns
tENZH
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
tENZL
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
tENHZ
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
tENLZ
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
tGLH
G-to-Pad HIGH
4.8
5.3
6.0
7.2
10.0
ns
tGHL
G-to-Pad LOW
4.8
5.3
6.0
7.2
10.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
dTLH
2
Capacitive Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08
ns/pF
dTHL
2
Capacitive Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10
ns/pF
tACO
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
4.5
5.0
5.6
6.6
9.3
ns
tDHL
Data-to-Pad LOW
3.4
3.8
4.3
5.1
7.1
ns
tENZH
Enable Pad Z to HIGH
3.8
4.2
4.8
5.6
7.8
ns
tENZL
Enable Pad Z to LOW
4.2
4.6
5.3
6.2
8.7
ns
tENHZ
Enable Pad HIGH to Z
7.6
8.4
9.5
11.2
15.7
ns
tENLZ
Enable Pad LOW to Z
7.0
7.8
8.8
10.4
14.5
ns
tGLH
G-to-Pad HIGH
7.1
7.9
8.9
10.5
14.7
ns
tGHL
G-to-Pad LOW
7.1
7.9
8.9
10.5
14.7
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
tACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
11.3
12.5
14.2
16.7
23.3
ns
2
Capacitive Loading, LOW to HIGH
0.04
0.04
0.05
0.06
0.08
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.05
0.05
0.06
0.07
0.10
ns/pF
dTLH
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
v5.0
57
40MX and 42MX FPGA Families
A 42 M X2 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 4. 75V, T J = 70° C)
‘–3’ Speed
Parameter Description
Min.
Logic Module Combinatorial Functions
Max.
‘–2’Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
1
tPD
Internal Array Module Delay
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays
1.2
1.3
1.5
1.8
2.5
ns
1.4
1.6
1.8
2.1
3.0
ns
2
tRD1
FO=1 Routing Delay
0.8
0.9
1.0
1.2
1.7
ns
tRD2
FO=2 Routing Delay
1.0
1.2
1.3
1.5
2.1
ns
tRD3
FO=3 Routing Delay
1.3
1.4
1.6
1.9
2.6
ns
tRD4
FO=4 Routing Delay
1.5
1.7
1.9
2.2
3.1
ns
tRD5
FO=8 Routing Delay
2.4
2.7
3.0
3.6
5.0
ns
Logic Module Sequential Timing
3, 4
tCO
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch Gate-to-Output
1.2
1.3
1.5
1.8
2.5
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.3
0.4
0.4
0.5
0.7
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.4
0.5
0.5
0.6
0.8
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
3.3
3.7
4.2
4.9
6.9
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
4.4
4.8
5.3
6.5
9.0
ns
tWASYN
1.4
1.6
1.8
2.1
2.9
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
58
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.0
1.1
1.3
1.5
2.1
ns
tINGO
Input Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.6
ns
tINH
Input Latch Hold
tINSU
Input Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tILA
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
0.0
0.0
0.0
0.0
0.0
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
1.8
2.0
2.3
2.7
3.8
ns
tIRD2
FO=2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
tIRD3
FO=3 Routing Delay
2.3
2.5
2.9
3.4
4.8
ns
tIRD4
FO=4 Routing Delay
2.5
2.8
3.2
3.7
5.2
ns
tIRD8
FO=8 Routing Delay
3.4
3.8
4.3
5.1
7.1
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=486
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
5.9
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=486
3.7
4.3
4.1
4.7
4.6
5.4
5.4
6.3
7.6
8.8
ns
ns
tPWH
Minimum Pulse Width HIGH FO=32
FO=486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
tPWL
Minimum Pulse Width LOW FO=32
FO=486
2.2
2.4
2.4
2.6
2.7
3.0
3.2
3.5
4.5
4.9
ns
ns
tCKSW
Maximum Skew
tSUEXT
Input Latch External Set-Up FO=32
FO=486
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=486
2.8
3.3
3.1
3.7
3.5
4.2
4.1
4.9
5.7
6.9
ns
ns
tP
Minimum Period (1/fMAX)
FO=32
FO=486
4.7
5.1
5.2
5.7
5.7
6.2
6.5
7.1
10.9
11.9
ns
ns
fMAX
Maximum Datapath
Frequency
FO=32
FO=486
FO=32
FO=486
0.5
0.5
0.6
0.6
210
193
191
175
0.7
0.7
176
161
0.8
0.8
153
140
1.1
1.1
92
84
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
v5.0
59
40MX and 42MX FPGA Families
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
2.4
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.8
3.2
3.6
4.2
5.9
ns
tENZH
Enable Pad Z to HIGH
2.5
2.8
3.2
3.8
5.3
ns
tENZL
Enable Pad Z to LOW
2.8
3.1
3.5
4.2
5.9
ns
tENHZ
Enable Pad HIGH to Z
5.2
5.7
6.5
7.6
10.7
ns
tENLZ
Enable Pad LOW to Z
4.8
5.3
6.0
7.1
9.9
ns
tGLH
G-to-Pad HIGH
2.9
3.2
3.6
4.3
6.0
ns
tGHL
G-to-Pad LOW
tLSU
I/O Latch Output Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
2.9
3.2
3.6
4.3
6.0
ns
5.6
6.1
6.9
8.1
11.4
ns
Array Latch Clock-to-Out
(Pad-to-Pad)
32 I/O
10.6
11.8
13.4
15.7
22.0
ns
dTLH
2
Capacitive Loading, LOW to HIGH
0.04
0.04
0.04
0.05
0.07
ns/pF
dTHL
2
Capacitive Loading, HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
tACO
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
3.1
3.5
3.9
4.6
6.4
ns
tDHL
Data-to-Pad LOW
2.4
2.6
3.0
3.5
4.9
ns
tENZH
Enable Pad Z to HIGH
2.5
2.8
3.2
3.8
5.3
ns
tENZL
Enable Pad Z to LOW
2.8
3.1
3.5
4.2
5.8
ns
tENHZ
Enable Pad HIGH to Z
5.2
5.7
6.5
7.6
10.7
ns
tENLZ
Enable Pad LOW to Z
4.8
5.3
6.0
7.1
9.9
ns
tGLH
G-to-Pad HIGH
4.9
5.4
6.2
7.2
10.1
ns
tGHL
G-to-Pad LOW
4.9
5.4
6.2
7.2
10.1
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
Array Latch Clock-to-Out
(Pad-to-Pad)
32 I/O
tACO
5.5
6.1
6.9
8.1
11.3
ns
10.6
11.8
13.4
15.7
22.0
ns
2
Capacitive Loading, LOW to HIGH
0.04
0.04
0.04
0.05
0.07
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.03
0.03
0.03
0.04
0.06
ns/pF
dTLH
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
60
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X2 4 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 3. 0V, T J = 7 0°C )
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
1
Logic Module Combinatorial Functions
tPD
Internal Array Module Delay
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays
2.0
1.8
2.1
2.5
3.4
ns
1.1
2.2
2.5
3.0
4.2
ns
2
tRD1
FO=1 Routing Delay
1.7
1.3
1.4
1.7
2.3
ns
tRD2
FO=2 Routing Delay
2.0
1.6
1.8
2.1
3.0
ns
tRD3
FO=3 Routing Delay
1.1
2.0
2.2
2.6
3.7
ns
tRD4
FO=4 Routing Delay
1.5
2.3
2.6
3.1
4.3
ns
tRD5
FO=8 Routing Delay
1.8
3.7
4.2
5.0
7.0
ns
Logic Module Sequential Timing
3, 4
tCO
Flip-Flop Clock-to-Output
2.1
2.0
2.3
2.7
3.7
ns
tGO
Latch Gate-to-Output
3.4
1.9
2.1
2.5
3.4
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.6
0.7
0.8
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
4.6
5.2
5.8
6.9
9.6
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
6.1
6.8
7.7
9.0
12.6
ns
tWASYN
2.0
2.2
2.5
2.9
4.1
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
v5.0
61
40MX and 42MX FPGA Families
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.4
1.6
1.8
2.2
3.0
ns
tINGO
Input Latch Gate-to-Output
1.8
1.9
2.2
2.6
3.6
ns
tINH
Input Latch Hold
tINSU
Input Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tILA
Latch Active Pulse Width
6.5
7.3
8.2
9.7
13.5
ns
0.0
0.0
0.0
0.0
0.0
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
tIRD2
FO=2 Routing Delay
2.9
3.2
3.6
4.3
6.0
ns
tIRD3
FO=3 Routing Delay
3.2
3.6
4.0
4.8
6.6
ns
tIRD4
FO=4 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD8
FO=8 Routing Delay
4.8
5.3
6.1
7.1
10.0
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=486
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.1
10.0
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=486
5.1
6.0
5.7
6.6
6.4
7.5
7.6
8.8
10.6
12.4
ns
ns
tPWH
Minimum Pulse Width HIGH FO=32
FO=486
3.0
3.3
3.3
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
tPWL
Minimum Pulse Width LOW FO=32
FO=486
3.0
3.3
3.4
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
ns
tCKSW
Maximum Skew
tSUEXT
Input Latch External Set-Up FO=32
FO=486
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=486
3.9
4.6
4.3
5.2
4.9
5.8
5.7
6.9
8.1
9.6
ns
ns
tP
Minimum Period (1/fMAX)
FO=32
FO=486
7.8
8.6
8.7
9.5
9.47
10.4
10.8
11.9
18.2
19.9
ns
ns
fMAX
Maximum Datapath
Frequency
FO=32
FO=486
FO=32
FO=486
0.8
0.8
0.8
0.8
126
116
115
105
1.0
1.0
106
97
1.1
1.1
92
84
1.6
1.6
55
50
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
62
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70°C)
‘–3 Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
3.4
3.8
4.3
5.0
7.1
ns
tDHL
Data-to-Pad LOW
4.0
4.4
5.0
5.9
8.3
ns
tENZH
Enable Pad Z to HIGH
3.6
4.0
4.5
5.3
7.4
ns
tENZL
Enable Pad Z to LOW
3.9
4.4
5.0
5.8
8.2
ns
tENHZ
Enable Pad HIGH to Z
7.2
8.0
9.07
10.7
14.9
ns
tENLZ
Enable Pad LOW to Z
6.7
7.5
8.5
9.9
13.9
ns
tGLH
G-to-Pad HIGH
4.8
5.3
6.0
7.2
10.0
ns
tGHL
G-to-Pad LOW
tLSU
I/O Latch Output Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
7.67
8.5
9.6
11.3
15.9
ns
Array Latch Clock-to-Out
(Pad-to-Pad)
32 I/O
14.8
16.5
18.7
22.0
30.8
ns
dTLH
2
Capacitive Loading, LOW to HIGH
0.05
0.05
0.06
0.07
0.10
ns/pF
dTHL
2
Capacitive Loading, HIGH to LOW
0.04
0.04
0.05
0.06
0.08
ns/pF
tACO
4.8
5.3
6.0
7.2
10.0
ns
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
4.8
5.3
5.5
6.4
9.0
ns
tDHL
Data-to-Pad LOW
3.5
3.9
4.1
4.9
6.8
ns
tENZH
Enable Pad Z to HIGH
3.6
4.0
4.5
5.3
7.4
ns
tENZL
Enable Pad Z to LOW
3.4
4.0
5.0
5.8
8.2
ns
tENHZ
Enable Pad HIGH to Z
7.2
8.0
9.01
10.7
14.9
ns
tENLZ
Enable Pad LOW to Z
6.7
7.5
8.5
9.9
13.9
ns
tGLH
G-to-Pad HIGH
6.8
7.6
8.6
10.1
14.2
ns
tGHL
G-to-Pad LOW
6.8
7.6
8.6
10.1
14.2
ns
tLSU
I/O Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
7.7
8.5
9.6
11.3
15.9
ns
Array Latch Clock-to-Out
(Pad-to-Pad)
32 I/O
14.8
16.5
18.7
22.0
30.8
ns
tACO
2
Capacitive Loading, LOW to HIGH
0.05
0.05
0.06
0.07
0.10
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.04
0.04
0.05
0.06
0.08
ns/pF
dTLH
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
v5.0
63
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 4. 75V, T J = 70° C)
‘–3’ Speed
Parameter Description
Min.
Logic Module Combinatorial Functions
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
1
tPD
Internal Array Module Delay
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays
1.3
1.5
1.7
2.0
2.7
ns
1.6
1.8
2.0
2.4
3.3
ns
2
tRD1
FO=1 Routing Delay
0.9
1.0
1.2
1.4
2.0
ns
tRD2
FO=2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
tRD3
FO=3 Routing Delay
1.6
1.8
2.0
2.4
3.4
ns
tRD4
FO=4 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
tRD5
FO=8 Routing Delay
3.3
3.7
4.2
4.9
6.9
ns
tRDD
Decode-to-Output Routing Delay
0.3
0.4
0.4
0.5
0.7
ns
Logic Module Sequential Timing
3, 4
tCO
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tGO
Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.7
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.3
0.34
0.4
0.5
0.7
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
3.3
3.7
4.2
4.9
6.9
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
4.4
4.8
5.5
6.4
9.0
ns
tWASYN
1.6
1.7
2.0
2.3
3.2
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
64
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
Logic Module Timing
Parameter Description
‘–3’ Speed
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
tWC
Write Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
tRCKHL
Clock HIGH/LOW Time
3.4
3.8
4.3
5.0
7.0
ns
tRCO
Data Valid After Clock HIGH/LOW
tADSU
Address/Data Set-Up Time
1.6
1.8
2.0
2.4
3.4
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSU
Read Enable Set-Up
0.6
0.7
0.8
0.9
1.3
ns
tRENH
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tBENS
Block Enable Set-Up
2.8
3.1
3.5
4.1
5.7
ns
tBENH
Block Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
3.4
3.78
4.3
5.0
7.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
8.8
9.8
11.1
13.0
18.2
ns
tADSU
Address/Data Set-Up Time
1.6
1.8
2.0
2.4
3.4
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSUA
Read Enable Set-Up to Address Valid
0.6
0.7
0.8
0.9
1.3
ns
tRENHA
Read Enable Hold
3.4
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
2.7
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tDOH
Data Out Hold Time
8.1
9.0
1.2
1.34
v5.0
10.2
1.5
12.0
1.8
16.8
2.5
ns
ns
65
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.0
1.1
1.3
1.5
2.1
ns
tINGO
Input Latch Gate-to-Output
1.4
1.6
1.8
2.1
2.9
ns
tINH
Input Latch Hold
tINSU
Input Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tILA
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
0.0
0.0
0.0
0.0
0.0
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
tIRD2
FO=2 Routing Delay
2.3
2.6
2.9
3.4
4.8
ns
tIRD3
FO=3 Routing Delay
2.6
2.9
3.3
3.9
5.5
ns
tIRD4
FO=4 Routing Delay
3.0
3.3
3.8
4.4
6.2
ns
tIRD8
FO=8 Routing Delay
4.3
4.8
5.5
6.4
9.0
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=635
2.7
3.0
3.0
3.3
3.4
3.8
4.0
4.4
5.6
6.2
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=635
3.8
4.9
4.2
5.4
4.8
6.1
5.6
7.2
7.8
10.1
ns
ns
tPWH
Minimum Pulse Width HIGH FO=32
FO=635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
tPWL
Minimum Pulse Width LOW FO=32
FO=635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
tCKSW
Maximum Skew
tSUEXT
Input Latch External Set-Up FO=32
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=635
2.8
3.3
3.2
3.7
3.6
4.2
4.2
4.9
5.9
6.9
ns
ns
tP
Minimum Period (1/fMAX)
FO=32
FO=635
5.5
6.0
6.1
6.6
6.6
7.2
7.6
8.3
12.7
13.8
ns
ns
fHMAX
Maximum Datapath
Frequency
FO=32
FO=635
FO=32
FO=635
0.8
0.8
0.8
0.8
180
166
164
151
0.9
0.9
151
139
1.0
1.0
131
121
1.4
1.4
79
73
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
66
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V C C = 4.75V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
2.6
2.8
3.2
3.8
5.3
ns
tDHL
Data-to-Pad LOW
3.0
3.3
3.7
4.4
6.2
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
3.0
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
tENLZ
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
2.9
3.3
3.7
4.4
6.1
ns
tGHL
G-to-Pad LOW
tLSU
I/O Latch Output Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
5.7
6.3
7.1
8.4
11.8
ns
Array Latch Clock-to-Out
(Pad-to-Pad)
32 I/O
7.8
8.6
9.8
11.5
16.1
ns
dTLH
2
Capacitive Loading, LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
dTHL
2
Capacitive Loading, HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
tACO
2.9
3.3
3.7
4.4
6.1
ns
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
3.5
3.9
4.5
5.2
7.3
ns
tDHL
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
tENLZ
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
5.0
5.6
6.3
7.5
10.4
ns
tGHL
G-to-Pad LOW
5.0
5.6
6.3
7.5
10.4
ns
tLSU
I/O Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
5.7
6.3
7.1
8.4
11.8
ns
Array Latch Clock-to-Out
(Pad-to-Pad)
32 I/O
7.78
8.6
9.8
11.5
16.1
ns
tACO
2
Capacitive Loading, LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
dTLH
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
v5.0
67
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e C om m erci al Co ndit i ons , V CC = 3. 0V, T J = 7 0°C )
‘–3’ Speed
Parameter Description
Min.
Logic Module Combinatorial Functions
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
1
tPD
Internal Array Module Delay
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays
1.9
2.1
2.3
2.7
3.8
ns
2.2
2.5
2.8
3.3
4.7
ns
2
tRD1
FO=1 Routing Delay
1.3
1.5
1.7
2.0
2.7
ns
tRD2
FO=2 Routing Delay
1.8
2.0
2.3
2.7
3.7
ns
tRD3
FO=3 Routing Delay
2.3
2.5
2.8
3.4
4.7
ns
tRD4
FO=4 Routing Delay
2.8
3.1
3.5
4.1
5.7
ns
tRD5
FO=8 Routing Delay
4.6
5.2
5.8
6.9
9.6
ns
tRDD
Decode-to-Output Routing Delay
0.5
0.5
0.6
0.7
1.0
ns
Logic Module Sequential Timing
3, 4
tCO
Flip-Flop Clock-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tGO
Latch Gate-to-Output
1.8
2.0
2.3
2.7
3.7
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.4
0.5
0.6
0.7
0.9
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.0
1.1
1.2
1.4
2.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
4.6
5.2
5.8
6.9
9.6
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
6.1
6.8
7.7
9.0
12.6
ns
tWASYN
2.2
2.4
2.7
3.2
4.5
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
68
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70°C)
Logic Module Timing
Parameter Description
‘–3’ Speed
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tWC
Write Cycle Time
9.5
10.5
11.9
14.0
19.6
ns
tRCKHL
Clock HIGH/LOW Time
4.8
5.3
6.0
7.0
9.8
ns
tRCO
Data Valid After Clock HIGH/LOW
tADSU
Address/Data Set-Up Time
2.3
2.5
2.8
3.4
4.8
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSU
Read Enable Set-Up
0.9
1.0
1.1
1.3
1.8
ns
tRENH
Read Enable Hold
4.8
5.3
6.0
7.0
9.8
ns
tWENSU
Write Enable Set-Up
3.8
4.2
4.8
5.6
7.8
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tBENS
Block Enable Set-Up
3.9
4.3
4.9
5.7
8.0
ns
tBENH
Block Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
4.8
5.3
6.0
7.0
9.8
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
tADSU
tADH
11.3
12.6
14.3
16.8
23.5
ns
12.3
13.7
15.5
18.2
25.5
ns
Address/Data Set-Up Time
2.3
2.5
2.8
3.4
4.8
ns
Address/Data Hold Time
0.0
0.0
0.0
0.0
0.0
ns
tRENSUA
Read Enable Set-Up to Address Valid
0.9
1.0
1.1
1.3
1.8
ns
tRENHA
Read Enable Hold
4.8
5.3
6.0
7.0
9.8
ns
tWENSU
Write Enable Set-Up
3.8
4.2
4.8
5.6
7.8
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
tDOH
Data Out Hold Time
1.8
2.0
v5.0
2.1
2.5
3.5
ns
69
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V CC = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.4
1.6
1.8
2.1
3.0
ns
tINGO
Input Latch Gate-to-Output
2.0
2.2
2.5
2.9
4.1
ns
tINH
Input Latch Hold
tINSU
Input Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tILA
Latch Active Pulse Width
6.5
7.3
8.2
9.7
13.5
ns
0.0
0.0
0.0
0.0
0.0
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.8
3.1
3.5
4.07
5.7
ns
tIRD2
FO=2 Routing Delay
3.2
3.5
4.1
4.8
6.7
ns
tIRD3
FO=3 Routing Delay
3.7
4.1
4.7
5.5
7.7
ns
tIRD4
FO=4 Routing Delay
4.2
4.6
5.3
6.2
8.7
ns
tIRD8
FO=8 Routing Delay
6.1
6.8
7.7
9.0
12.6
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=635
4.6
5.0
5.1
5.6
5.7
6.3
6.7
7.4
9.3
10.3
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=635
5.3
6.8
5.9
7.6
6.7
8.6
7.8
10.1
11.0
14.1
ns
ns
tPWH
Minimum Pulse Width HIGH FO=32
FO=635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
tPWL
Minimum Pulse Width LOW FO=32
FO=635
2.5
2.8
2.7
3.1
3.1
3.5
3.6
4.1
5.1
5.7
ns
ns
tCKSW
Maximum Skew
tSUEXT
Input Latch External Set-Up FO=32
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=635
4.0
4.6
4.4
5.2
5.0
5.9
5.9
6.9
8.2
9.6
ns
ns
tP
Minimum Period (1/fMAX)
FO=32
FO=635
9.2
9.9
10.2
11.0
11.1
12.0
12.7
13.8
21.2
23.0
ns
ns
fHMAX
Maximum Datapath
Frequency
FO=32
FO=635
FO=32
FO=635
1.0
1.0
1.2
1.2
108
100
98
91
1.3
1.3
90
83
1.5
1.5
79
73
2.2
2.2
47
44
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
70
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Commercial Conditions, V C C = 3.0V, T J = 70°C)
‘–3’ Speed
Parameter Description
Min.
Max.
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
3.6
4.0
4.5
5.3
7.4
ns
tDHL
Data-to-Pad LOW
4.2
4.6
5.2
6.2
8.6
ns
tENZH
Enable Pad Z to HIGH
3.7
4.2
4.7
5.5
7.7
ns
tENZL
Enable Pad Z to LOW
4.1
4.6
5.2
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
7.34
8.2
9.3
10.9
15.3
ns
tENLZ
Enable Pad LOW to Z
6.9
7.6
8.7
10.2
14.3
ns
tGLH
G-to-Pad HIGH
4.9
5.5
6.2
7.3
10.2
ns
tGHL
G-to-Pad LOW
tLSU
I/O Latch Output Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
7.9
8.8
10.0
11.8
16.5
ns
Array Latch Clock-to-Out
(Pad-to-Pad)
32 I/O
10.9
12.1
13.7
16.1
22.5
ns
dTLH
2
Capacitive Loading, LOW to HIGH
0.10
0.11
0.12
0.14
0.20
ns/pF
dTHL
2
Capacitive Loading, HIGH to LOW
0.10
0.11
0.12
0.14
0.20
ns/pF
tACO
4.9
5.5
6.2
7.3
10.2
ns
CMOS Output Module Timing1
tDLH
Data-to-Pad HIGH
4.9
5.5
6.2
7.3
10.3
ns
tDHL
Data-to-Pad LOW
3.4
3.8
4.3
5.1
7.1
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.7
5.5
7.7
ns
tENZL
Enable Pad Z to LOW
4.1
4.6
5.2
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
7.4
8.2
9.3
10.9
15.3
ns
tENLZ
Enable Pad LOW to Z
6.9
7.6
8.7
10.2
14.3
ns
tGLH
G-to-Pad HIGH
7.0
7.8
8.9
10.4
14.6
ns
tGHL
G-to-Pad LOW
7.0
7.8
8.9
10.4
14.6
ns
tLSU
I/O Latch Set-Up
0.7
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
7.9
8.8
10.0
11.8
16.5
ns
Array Latch Clock-to-Out
(Pad-to-Pad)
32 I/O
10.9
12.1
13.7
16.1
22.5
ns
tACO
2
Capacitive Loading, LOW to HIGH
0.10
0.11
0.12
0.14
0.20
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.10
0.11
0.12
0.14
0.20
ns/pF
dTLH
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
v5.0
71
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5V, T J = 125 °C )
‘–2’ Speed
Parameter
Description
Min.
Logic Module Combinatorial Functions
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
1
tPD
Internal Array Module Delay
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays
1.5
1.7
2.0
2.7
ns
1.8
2.0
2.4
3.3
ns
2
tRD1
FO=1 Routing Delay
1.0
1.2
1.4
2.0
ns
tRD2
FO=2 Routing Delay
1.4
1.6
1.9
2.7
ns
tRD3
FO=3 Routing Delay
1.8
2.0
2.4
3.4
ns
tRD4
FO=4 Routing Delay
2.2
2.5
2.9
4.1
ns
tRD5
FO=8 Routing Delay
3.7
4.2
4.9
6.9
ns
tRDD
Decode-to-Output Routing Delay
0.4
0.4
0.5
0.7
ns
Logic Module Sequential Timing
3, 4
tCO
Flip-Flop Clock-to-Output
1.4
1.6
1.9
2.7
ns
tGO
Latch Gate-to-Output
1.4
1.6
1.9
2.7
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.4
0.4
0.5
0.7
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.8
0.9
1.0
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
3.7
4.2
4.9
6.9
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
4.8
5.5
6.4
9.0
ns
1.7
2.0
2.3
3.2
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate..
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
72
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125°C)
Logic Module Timing
Parameter
Description
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
7.5
8.5
10.0
14.0
ns
tWC
Write Cycle Time
7.5
8.5
10.0
14.0
ns
tRCKHL
Clock HIGH/LOW Time
3.8
4.3
5.0
7.0
ns
tRCO
Data Valid After Clock HIGH/LOW
tADSU
Address/Data Set-Up Time
1.8
2.0
2.4
3.4
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
ns
tRENSU
Read Enable Set-Up
0.7
0.8
0.9
1.3
ns
tRENH
Read Enable Hold
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
ns
tBENS
Block Enable Set-Up
3.1
3.5
4.1
5.7
ns
tBENH
Block Enable Hold
0.0
0.0
0.0
0.0
ns
3.8
4.3
5.0
7.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
tADSU
Address/Data Set-Up Time
1.8
2.1
2.4
3.4
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
0.0
ns
tRENSUA
Read Enable Set-Up to Address Valid
0.7
0.8
0.9
1.3
ns
tRENHA
Read Enable Hold
3.8
4.3
5.0
7.0
ns
tWENSU
Write Enable Set-Up
3.0
3.4
4.0
5.6
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
0.0
ns
tDOH
Data Out Hold Time
9.0
9.8
10.2
11.1
1.4
v5.0
12.0
13.0
1.5
16.8
18.2
1.8
ns
ns
2.5
ns
73
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125°C)
‘–2’ Speed
Parameter
Description
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.1
1.3
1.5
2.1
ns
tINGO
Input Latch Gate-to-Output
1.6
1.8
2.1
2.9
ns
tINH
Input Latch Hold
0.0
0.0
0.0
tINSU
Input Latch Set-Up
0.5
0.6
0.7
1.0
ns
tILA
Latch Active Pulse Width
5.2
5.9
6.9
9.7
ns
0.0
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.2
2.5
2.9
4.1
ns
tIRD2
FO=2 Routing Delay
2.6
2.9
3.4
4.8
ns
tIRD3
FO=3 Routing Delay
2.9
3.3
3.9
5.5
ns
tIRD4
FO=4 Routing Delay
3.3
3.8
4.4
6.2
ns
tIRD8
FO=8 Routing Delay
4.8
5.5
6.4
9.0
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=635
3.0
3.3
3.4
3.8
4.0
4.4
5.6
6.2
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=635
4.2
5.4
4.8
6.1
5.6
7.2
7.8
10.1
ns
ns
tPWH
Minimum Pulse Width HIGH
FO=32
FO=635
2.0
2.2
2.2
2.5
2.6
2.9
3.7
4.1
ns
ns
tPWL
Minimum Pulse Width LOW
FO=32
FO=635
2.0
2.2
2.2
2.5
2.6
2.9
3.7
4.1
ns
ns
tCKSW
Maximum Skew
FO=32
FO=635
tSUEXT
Input Latch External Set-Up
FO=32
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=635
3.2
3.7
3.6
4.2
4.2
4.9
5.9
6.9
ns
ns
tP
Minimum Period (1/fMAX)
FO=32
FO=635
6.1
6.6
6.6
7.2
7.6
8.3
12.7
13.8
ns
ns
fHMAX
Maximum Datapath Frequency
FO=32
FO=635
0.8
0.8
164
151
0.9
0.9
151
139
1.0
1.0
131
121
1.4
1.4
79
73
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
74
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 5 . 0V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125°C)
‘–2’ Speed
Parameter
Description
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
‘–F’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
2.8
3.2
3.8
5.3
ns
tDHL
Data-to-Pad LOW
3.3
3.7
4.4
6.2
ns
tENZH
Enable Pad Z to HIGH
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.8
6.6
7.8
11.0
ns
tENLZ
Enable Pad LOW to Z
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
3.3
3.7
4.4
6.1
ns
tGHL
G-to-Pad LOW
6.1
ns
tLSU
I/O Latch Output Set-Up
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
3.3
3.7
6.3
4.4
7.1
8.4
11.8
ns
tACO
Array Latch Clock-to-Out (Pad-to-Pad)
32 I/O
8.6
9.8
11.5
16.1
ns
dTLH2
Capacitive Loading, LOW to HIGH
0.08
0.09
0.10
0.14
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.08
0.09
0.10
0.14
ns/pF
CMOS Output Module Timing
1
tDLH
Data-to-Pad HIGH
3.9
4.5
5.2
7.3
ns
tDHL
Data-to-Pad LOW
2.7
3.1
3.7
5.1
ns
tENZH
Enable Pad Z to HIGH
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.8
6.6
7.8
10.9
ns
tENLZ
Enable Pad LOW to Z
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
5.6
6.3
7.5
10.4
ns
tGHL
G-to-Pad LOW
5.6
6.3
7.5
10.4
ns
tLSU
I/O Latch Set-Up
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
6.3
7.1
8.4
11.8
ns
tACO
Array Latch Clock-to-Out (Pad-to-Pad)
32 I/O
8.6
9.78
11.5
16.1
ns
2
Capacitive Loading, LOW to HIGH
0.08
0.09
0.10
0.14
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.08
0.09
0.10
0.14
ns/pF
dTLH
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
v5.0
75
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 3.0V, T J = 125 °C )
‘–2’ Speed
Parameter
Description
Min.
Logic Module Combinatorial Functions
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
tPD
Internal Array Module Delay
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays
2.4
2.7
3.2
ns
2.9
3.3
3.9
ns
2
tRD1
FO=1 Routing Delay
1.7
2.0
2.3
ns
tRD2
FO=2 Routing Delay
2.3
2.6
3.1
ns
tRD3
FO=3 Routing Delay
2.9
3.3
3.9
ns
tRD4
FO=4 Routing Delay
3.6
4.0
4.7
ns
tRD5
FO=8 Routing Delay
6.0
6.8
8.0
ns
tRDD
Decode-to-Output Routing Delay
6.7
0.8
0.9
ns
Logic Module Sequential Timing
3, 4
tCO
Flip-Flop Clock-to-Output
2.4
2.7
3.1
ns
tGO
Latch Gate-to-Output
2.4
2.7
3.1
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.6
0.7
0.8
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.3
1.4
1.7
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
6.0
6.8
8.0
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
7.9
8.9
10.5
ns
2.9
3.2
3.8
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
3. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
76
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 3.0V, T J = 125°C)
Logic Module Timing
Parameter
Description
‘–2’ Speed
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
12.1
13.8
16.2
ns
tWC
Write Cycle Time
12.1
13.8
16.2
ns
tRCKHL
Clock HIGH/LOW Time
6.1
6.9
8.1
ns
tRCO
Data Valid After Clock HIGH/LOW
tADSU
Address/Data Set-Up Time
2.9
3.2
3.9
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
ns
tRENSU
Read Enable Set-Up
1.2
1.5
ns
tRENH
Read Enable Hold
6.1
6.9
8.1
ns
tWENSU
Write Enable Set-Up
4.8
5.5
6.4
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
ns
tBENS
Block Enable Set-Up
4.9
5.6
6.6
ns
tBENH
Block Enable Hold
0.0
0.0
0.0
ns
6.2
7.0
8.2
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
tADSU
Address/Data Set-Up Time
2.9
3.2
3.9
ns
tADH
Address/Data Hold Time
0.0
0.0
0.0
ns
tRENSUA
Read Enable Set-Up to Address Valid
1.1
1.2
1.5
ns
tRENHA
Read Enable Hold
6.1
6.9
8.1
ns
tWENSU
Write Enable Set-Up
4.8
5.5
6.4
ns
tWENH
Write Enable Hold
0.0
0.0
0.0
ns
tDOH
Data Out Hold Time
14.7
15.9
18.0
2.4
v5.0
16.6
19.5
21.1
2.5
ns
ns
2.9
ns
77
40MX and 42MX FPGA Families
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 3.0V, T J = 125°C)
‘–2’ Speed
Parameter
Description
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.9
2.1
2.5
ns
tINGO
Input Latch Gate-to-Output
2.6
2.9
3.4
ns
tINH
Input Latch Hold
tINSU
Input Latch Set-Up
0.8
0.9
1.1
ns
tILA
Latch Active Pulse Width
8.4
9.5
11.2
ns
0.0
0.0
0.0
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
3.6
4.0
4.8
ns
tIRD2
FO=2 Routing Delay
4.2
4.7
5.6
ns
tIRD3
FO=3 Routing Delay
4.8
5.4
6.4
ns
tIRD4
FO=4 Routing Delay
5.4
6.1
7.2
ns
tIRD8
FO=8 Routing Delay
7.9
8.9
10.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=635
5.9
6.5
6.7
7.3
7.8
8.6
ns
ns
tCKL
Input HIGH to LOW
FO=32
FO=635
6.9
8.8
7.8
10.0
9.1
11.7
ns
ns
tPWH
Minimum Pulse Width HIGH
FO=32
FO=635
3.1
3.5
3.5
4.0
4.2
4.7
ns
ns
tPWL
Minimum Pulse Width LOW
FO=32
FO=635
3.1
3.5
3.5
4.0
4.2
4.7
ns
ns
tCKSW
Maximum Skew
FO=32
FO=635
tSUEXT
Input Latch External Set-Up
FO=32
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=635
5.1
5.9
5.8
6.7
6.8
7.9
ns
ns
tP
Minimum Period (1/fMAX)
FO=32
FO=635
11.8
12.7
12.8
13.8
14.7
15.9
ns
ns
fHMAX
Maximum Datapath Frequency
FO=32
FO=635
1.4
1.4
85
78
1.6
1.6
78
71
1.8
1.8
67
62
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
78
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
A 42 M X3 6 Ti m i n g Ch a r ac t e r i s t i cs ( N o m i na l 3 . 3V O pe r a t i o n) (continued)
(Worst-Case Military Conditions, V C C = 3.0V, T J = 125°C)
‘–2’ Speed
Parameter
Description
Min.
Max.
‘–1’ Speed
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
4.6
5.2
6.2
ns
tDHL
Data-to-Pad LOW
5.3
6.1
7.2
ns
tENZH
Enable Pad Z to HIGH
4.8
5.4
6.4
ns
tENZL
Enable Pad Z to LOW
5.3
6.0
7.1
ns
tENHZ
Enable Pad HIGH to Z
9.5
10.8
12.7
ns
tENLZ
Enable Pad LOW to Z
8.9
10.0
11.8
ns
tGLH
G-to-Pad HIGH
6.3
7.2
8.4
ns
tGHL
G-to-Pad LOW
8.4
ns
tLSU
I/O Latch Output Set-Up
0.8
0.9
1.1
ns
tLH
I/O Latch Output Hold
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
10.2
11.6
13.7
tACO
Array Latch Clock-to-Out (Pad-to-Pad)
32 I/O
14.0
15.9
18.7
ns
dTLH2
Capacitive Loading, LOW to HIGH
0.13
0.14
0.16
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.13
0.14
0.16
ns/pF
CMOS Output Module Timing
6.3
7.2
ns
1
tDLH
Data-to-Pad HIGH
6.4
7.3
8.5
ns
tDHL
Data-to-Pad LOW
4.5
5.1
5.9
ns
tENZH
Enable Pad Z to HIGH
4.8
5.5
6.4
ns
tENZL
Enable Pad Z to LOW
5.3
6.0
7.1
ns
tENHZ
Enable Pad HIGH to Z
9.5
10.8
12.7
ns
tENLZ
Enable Pad LOW to Z
8.9
10.0
11.8
ns
tGLH
G-to-Pad HIGH
9.1
10.3
12.1
ns
tGHL
G-to-Pad LOW
9.1
10.3
12.1
ns
tLSU
I/O Latch Set-Up
0.8
0.9
1.1
ns
tLH
I/O Latch Hold
0.0
0.0
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad)
32 I/O
10.2
13.7
13.7
ns
tACO
Array Latch Clock-to-Out (Pad-to-Pad)
32 I/O
14.0
18.7
18.7
ns
2
Capacitive Loading, LOW to HIGH
0.13
0.16
0.16
ns/pF
dTHL2
Capacitive Loading, HIGH to LOW
0.13
0.16
0.16
ns/pF
dTLH
Notes:
1. Delays based on 35 pF loading.
2. Slew rates measured from 10% to 90% VCCI.
v5.0
79
40MX and 42MX FPGA Families
Pi n D es c r i pt i on s
CLK, CLKA,
CLKB
Global Clock (Input)
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
QCLKA,B,C,D Quadrant Clock (Input/Output)
TTL clock inputs for clock distribution networks. The clock
input is buffered prior to clocking the logic modules. This
pin can also be used as an I/O.
Quadrant clock inputs. When not used as a register control
signal, these pins can function as general-purpose I/Os.
DCLK
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground (Input)
Input LOW supply voltage.
I/O
Input/Output (Input, Output)
Input, output, tri-state, or bi-directional buffer. Input and
output levels are compatible with standard TTL and CMOS
specifications. Unused I/O pins are automatically driven
LOW by the Designer Series software.
LP
Low Power Mode
Controls the low power mode of all 42MX devices. This pin
must be set HIGH to switch the device to low power mode.
To exit the LOW power mode, the LP pin must be set LOW.
MODE
Mode (Input)
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). To provide verification capability, the MODE pin
should be held HIGH. To facilitate this, the MODE pin
should be terminated to GND through a 10K¾ resistor so
that the MODE pin can be pulled HIGH when required.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O
Probe A (Output)
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when verification has been completed.
The pin's probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRA is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
PRB, I/O
Probe B (Output)
The Probe B pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe A pin to allow real-time diagnostic output of any
signal path within the device. The Probe B pin can be used
as a user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality. PRB is
80
SDI
SDO, TDO,
I/O
Serial Data Input (Input)
Serial Data (Output)
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO is not available for 40MX devices.
TCK
Test Clock
Clock signal to shift the Boundary Scan Test (BST) data into
the device. This pin functions as an I/O when the test fuse is
not programmed. BST pins are only available in the
A42MX24, A42MX24A, and A42MX36 devices.
TDI
Test Data In
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as an
I/O when the test fuse is not programmed. BST pins are only
available in the A42MX24 and A42MX36 devices.
TDO
Test Data Out
Serial data output for BST instructions and test data. This
pin functions as an I/O when the test fuse is not
programmed. BST pins are only available in the A42MX24
and A42MX36 devices.
TMS
Test Mode Select
Serial data input for boundary scan test mode. Data is shifted
in on the rising edge of TCK. This pin functions as an I/O
when the test fuse is not programmed. BST pins are only
available in the A42MX24 and A42MX36 devices.
VCC
Supply Voltage (Input)
Input HIGH supply voltage.
V C CA
Supply Voltage (Input)
Input HIGH supply voltage, supplies array core only.
V C CI
Supply Voltage (Input)
Input HIGH supply voltage, supplies I/O cells only.
WD
Wide Decode Output
When a wide decode module is used in a 42MX device, this
pin can be used as a dedicated output from the wide decode
module. This direct connection eliminates additional
interconnect delays associated with regular logic modules.
To implement the direct I/O connection, connect an output
buffer of any type to the output of the wide decode macro
and place this output on one of the reserved WD pins.
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s
44-Pin PLCC
1 44
44-Pin
PLCC
44- pin P LCC
Pin Number
A40MX02
Function
A40MX04
Function
Pin Number
A40MX02
Function
A40MX04
Function
1
I/O
I/O
23
I/O
I/O
2
I/O
I/O
24
I/O
I/O
3
VCC
VCC
25
VCC
VCC
4
I/O
I/O
26
I/O
I/O
5
I/O
I/O
27
I/O
I/O
6
I/O
I/O
28
I/O
I/O
7
I/O
I/O
29
I/O
I/O
8
I/O
I/O
30
I/O
I/O
9
I/O
I/O
31
I/O
I/O
10
GND
GND
32
GND
GND
11
I/O
I/O
33
CLK, I/O
CLK, I/O
12
I/O
I/O
34
MODE
MODE
13
I/O
I/O
35
VCC
VCC
14
VCC
VCC
36
SDI, I/O
SDI, I/O
15
I/O
I/O
37
DCLK, I/O
DCLK, I/O
16
VCC
VCC
38
PRA, I/O
PRA, I/O
17
I/O
I/O
39
PRB, I/O
PRB, I/O
18
I/O
I/O
40
I/O
I/O
19
I/O
I/O
41
I/O
I/O
20
I/O
I/O
42
I/O
I/O
21
GND
GND
43
GND
GND
22
I/O
I/O
44
I/O
I/O
v5.0
81
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s
68-Pin PLCC
1 68
68-Pin
PLCC
68- Pi n PL CC
Pin
Number
A40MX02
Function
A40MX04
Function
Pin
Number
A40MX02
Function
A40MX04
Function
Pin
Number
A40MX02
Function
A40MX04
Function
1
I/O
I/O
24
I/O
I/O
47
I/O
I/O
2
I/O
I/O
25
VCC
VCC
48
I/O
I/O
3
I/O
I/O
26
I/O
I/O
49
GND
GND
4
VCC
VCC
27
I/O
I/O
50
I/O
I/O
5
I/O
I/O
28
I/O
I/O
51
I/O
I/O
6
I/O
I/O
29
I/O
I/O
52
CLK, I/O
CLK, I/O
7
I/O
I/O
30
I/O
I/O
53
I/O
I/O
8
I/O
I/O
31
I/O
I/O
54
MODE
MODE
9
I/O
I/O
32
GND
GND
55
VCC
VCC
10
I/O
I/O
33
I/O
I/O
56
SDI, I/O
SDI, I/O
11
I/O
I/O
34
I/O
I/O
57
DCLK, I/O
DCLK, I/O
12
I/O
I/O
35
I/O
I/O
58
PRA, I/O
PRA, I/O
13
I/O
I/O
36
I/O
I/O
59
PRB, I/O
PRB, I/O
14
GND
GND
37
I/O
I/O
60
I/O
I/O
15
GND
GND
38
VCC
VCC
61
I/O
I/O
16
I/O
I/O
39
I/O
I/O
62
I/O
I/O
17
I/O
I/O
40
I/O
I/O
63
I/O
I/O
18
I/O
I/O
41
I/O
I/O
64
I/O
I/O
19
I/O
I/O
42
I/O
I/O
65
I/O
I/O
20
I/O
I/O
43
I/O
I/O
66
GND
GND
21
VCC
VCC
44
I/O
I/O
67
I/O
I/O
22
I/O
I/O
45
I/O
I/O
68
I/O
I/O
23
I/O
I/O
46
I/O
I/O
82
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s (continued)
84-Pin PLCC
1
84
84-Pin
PLCC
v5.0
83
40MX and 42MX FPGA Families
84- Pi n PL CC
Pin
A40MX04 A42MX09 A42MX16 A42MX24
Number Function Function Function Function
84
Pin
A40MX04 A42MX09 A42MX16
Number Function Function Function
A42MX24
Function
43
I/O
VCCA
VCCA
VCCA
44
I/O
I/O
I/O
I/O (WD)
I/O
45
I/O
I/O
I/O
I/O (WD)
PRB, I/O
PRB, I/O
46
VCC
I/O
I/O
I/O (WD)
I/O
I/O
I/O (WD)
47
I/O
I/O
I/O
I/O (WD)
GND
GND
GND
48
I/O
I/O
I/O
I/O
I/O
I/O
I/O
49
I/O
GND
GND
GND
I/O
I/O
I/O (WD)
50
I/O
I/O
I/O
I/O (WD)
I/O
I/O
I/O (WD)
51
I/O
I/O
I/O
I/O (WD)
52
I/O
SDO, I/O
1
I/O
2
I/O
I/O
I/O
3
I/O
I/O
I/O
4
VCC
PRB, I/O
5
I/O
6
I/O
7
I/O
8
I/O
I/O
CLKB, I/O CLKB, I/O CLKB, I/O
9
I/O
10
I/O
11
I/O
I/O
I/O
I/O
53
I/O
I/O
I/O
I/O
12
NC
MODE
MODE
MODE
54
I/O
I/O
I/O
I/O
13
I/O
I/O
I/O
I/O
55
I/O
I/O
I/O
I/O
14
I/O
I/O
I/O
I/O
56
I/O
I/O
I/O
I/O
15
I/O
I/O
I/O
I/O
57
I/O
I/O
I/O
I/O
16
I/O
I/O
I/O
I/O
58
I/O
I/O
I/O
I/O
17
I/O
I/O
I/O
I/O
59
I/O
I/O
I/O
I/O
18
GND
I/O
I/O
I/O
60
GND
I/O
I/O
I/O
19
GND
I/O
I/O
I/O
61
GND
I/O
I/O
I/O
20
I/O
I/O
I/O
I/O
62
I/O
I/O
I/O
TCK, I/O
21
I/O
I/O
I/O
I/O
63
I/O
GND (LP)
GND (LP)
GND (LP)
22
I/O
VCCA
VCCI
VCCI
64
CLK, I/O
VCCA
VCCA
VCCA
23
I/O
VCCI
VCCA
VCCA
65
I/O
VCCI
VCCI
VCCI
24
I/O
I/O
I/O
I/O
66
MODE
I/O
I/O
I/O
25
VCC
I/O
I/O
I/O
67
VCC
I/O
I/O
I/O
26
VCC
I/O
I/O
I/O
68
VCC
I/O
I/O
I/O
27
I/O
I/O
I/O
I/O
69
I/O
I/O
I/O
I/O
28
I/O
GND
GND
GND
70
I/O
GND
GND
GND
DCLK, I/O DCLK, I/O DCLK, I/O
SDO, I/O SDO, TDO (WD)
29
I/O
I/O
I/O
I/O
71
I/O
I/O
I/O
I/O
30
I/O
I/O
I/O
I/O
72
SDI, I/O
I/O
I/O
I/O
31
I/O
I/O
I/O
I/O
73
DCLK, I/O
I/O
I/O
I/O
32
I/O
I/O
I/O
I/O
74
PRA, I/O
I/O
I/O
I/O
33
VCC
I/O
I/O
I/O
75
PRB, I/O
I/O
I/O
I/O
34
I/O
I/O
I/O
TMS, I/O
76
I/O
SDI, I/O
SDI, I/O
SDI, I/O
35
I/O
I/O
I/O
TDI, I/O
77
I/O
I/O
I/O
I/O
36
I/O
I/O
I/O
I/O (WD)
78
I/O
I/O
I/O
I/O (WD)
37
I/O
I/O
I/O
I/O
79
I/O
I/O
I/O
I/O (WD)
38
I/O
I/O
I/O
I/O (WD)
80
I/O
I/O
I/O
I/O (WD)
39
I/O
I/O
I/O
I/O (WD)
81
I/O
PRA, I/O
PRA, I/O
PRA, I/O
40
GND
I/O
I/O
I/O
82
GND
I/O
I/O
I/O
41
I/O
I/O
I/O
I/O
83
I/O
42
I/O
I/O
I/O
I/O
84
I/O
v5.0
CLKA, I/O CLKA, I/O
VCCA
VCCA
CLKA, I/O
VCCA
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s (continued)
100-Pin PQFP Package (Top View)
100-Pin
PQFP
100
1
v5.0
85
40MX and 42MX FPGA Families
100- P in P Q FP
Pin
Number
86
A40MX02 A40MX04 A42MX09 A42MX16
Function Function Function Function
1
NC
NC
I/O
2
NC
NC
3
NC
NC
I/O
4
NC
NC
5
NC
6
Pin
Number
I/O
A40MX02 A40MX04 A42MX09 A42MX16
Function Function Function Function
40
I/O
I/O
VCCA
VCCA
41
I/O
I/O
I/O
I/O
I/O
42
I/O
I/O
I/O
I/O
MODE
MODE
43
VCC
VCC
I/O
I/O
NC
I/O
I/O
44
VCC
VCC
I/O
I/O
PRB, I/O
PRB, I/O
I/O
I/O
45
I/O
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
46
I/O
I/O
GND
GND
8
I/O
I/O
I/O
I/O
47
I/O
I/O
I/O
I/O
9
I/O
I/O
GND
GND
48
NC
I/O
I/O
I/O
10
I/O
I/O
I/O
I/O
49
NC
I/O
I/O
I/O
11
I/O
I/O
I/O
I/O
50
NC
I/O
I/O
I/O
12
I/O
I/O
I/O
I/O
51
NC
NC
I/O
I/O
13
GND
GND
I/O
I/O
52
NC
NC
SDO, I/O
SDO, I/O
14
I/O
I/O
I/O
I/O
53
NC
NC
I/O
I/O
15
I/O
I/O
I/O
I/O
54
NC
NC
I/O
I/O
16
I/O
I/O
VCCA
VCCA
55
NC
NC
I/O
I/O
17
I/O
I/O
VCCI
VCCA
56
VCC
VCC
I/O
I/O
18
I/O
I/O
I/O
I/O
57
I/O
I/O
GND
GND
19
VCC
VCC
I/O
I/O
58
I/O
I/O
I/O
I/O
20
I/O
I/O
I/O
I/O
59
I/O
I/O
I/O
I/O
21
I/O
I/O
I/O
I/O
60
I/O
I/O
I/O
I/O
22
I/O
I/O
GND
GND
61
I/O
I/O
I/O
I/O
23
I/O
I/O
I/O
I/O
62
I/O
I/O
I/O
I/O
24
I/O
I/O
I/O
I/O
63
GND
GND
I/O
I/O
25
I/O
I/O
I/O
I/O
64
I/O
I/O
26
I/O
I/O
I/O
I/O
65
I/O
I/O
VCCA
VCCA
27
NC
NC
I/O
I/O
66
I/O
I/O
VCCI
VCCI
28
NC
NC
I/O
I/O
67
I/O
I/O
VCCA
VCCA
29
NC
NC
I/O
I/O
68
I/O
I/O
I/O
I/O
30
NC
NC
I/O
I/O
69
VCC
VCC
I/O
I/O
31
NC
I/O
I/O
I/O
70
I/O
I/O
I/O
I/O
32
NC
I/O
I/O
I/O
71
I/O
I/O
I/O
I/O
33
NC
I/O
I/O
I/O
72
I/O
I/O
GND
GND
34
I/O
I/O
GND
GND
73
I/O
I/O
I/O
I/O
35
I/O
I/O
I/O
I/O
74
I/O
I/O
I/O
I/O
36
GND
GND
I/O
I/O
75
I/O
I/O
I/O
I/O
37
GND
GND
I/O
I/O
76
I/O
I/O
I/O
I/O
38
I/O
I/O
I/O
I/O
77
NC
NC
I/O
I/O
39
I/O
I/O
I/O
I/O
78
NC
NC
I/O
I/O
DCLK, I/O DCLK, I/O
v5.0
GND (LP) GND (LP)
4 0 M X a n d 4 2 M X F PG A F a m il ie s
100- P in P Q FP (C ont inu ed)
Pin
Number
A40MX02 A40MX04 A42MX09 A42MX16
Function Function Function Function
Pin
Number
A40MX02 A40MX04 A42MX09 A42MX16
Function Function Function Function
79
NC
NC
SDI, I/O
SDI, I/O
90
CLK, I/O
CLK, I/O
VCCA
VCCA
80
NC
I/O
I/O
I/O
91
I/O
I/O
I/O
I/O
81
NC
I/O
I/O
I/O
92
MODE
MODE
82
NC
I/O
I/O
I/O
93
VCC
VCC
I/O
I/O
83
I/O
I/O
I/O
I/O
94
VCC
VCC
PRB, I/O
PRB, I/O
84
I/O
I/O
GND
GND
95
NC
I/O
I/O
I/O
85
I/O
I/O
I/O
I/O
96
NC
I/O
GND
GND
86
GND
GND
I/O
I/O
97
NC
I/O
I/O
I/O
87
GND
GND
PRA, I/O
PRA, I/O
98
SDI, I/O
SDI, I/O
I/O
I/O
88
I/O
I/O
I/O
I/O
99
I/O
I/O
89
I/O
I/O
I/O
I/O
CLKA, I/O CLKA, I/O
v5.0
100
DCLK, I/O DCLK, I/O
PRA, I/O
PRA, I/O
CLKB, I/O CLKB, I/O
87
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s (continued)
160-Pin PQFP Package (Top View)
160
1
160-Pin
PQFP
88
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
160- P in P Q FP
Pin
Number
A42MX09
Function
A42MX16
Function
A42MX24
Fucntion
Pin
Number
A42MX09
Function
A42MX16
Function
A42MX24
Fucntion
1
I/O
I/O
I/O
41
I/O
I/O
I/O
2
DCLK, I/O
DCLK, I/O
DCLK, I/O
42
I/O
I/O
I/O
3
NC
I/O
I/O
43
I/O
I/O
I/O
4
I/O
I/O
I/O (WD)
44
GND
GND
GND
5
I/O
I/O
I/O (WD)
45
I/O
I/O
I/O
6
NC
VCCI
VCCI
46
I/O
I/O
I/O
7
I/O
I/O
I/O
47
I/O
I/O
I/O
8
I/O
I/O
I/O
48
I/O
I/O
I/O
9
I/O
I/O
I/O
49
GND
GND
GND
10
NC
I/O
I/O
50
I/O
I/O
I/O
11
GND
GND
GND
51
I/O
I/O
I/O
12
NC
I/O
I/O
52
NC
I/O
I/O
13
I/O
I/O
I/O (WD)
53
I/O
I/O
I/O
14
I/O
I/O
I/O (WD)
54
NC
VCCA
VCCA
15
I/O
I/O
I/O
55
I/O
I/O
I/O
16
PRB, I/O
PRB, I/O
PRB, I/O
56
I/O
I/O
I/O
17
I/O
I/O
I/O
57
VCCA
VCCA
VCCA
18
CLKB, I/O
CLKB, I/O
CLKB, I/O
58
VCCI
VCCI
VCCI
19
I/O
I/O
I/O
59
GND
GND
GND
20
VCCA
VCCA
VCCA
60
VCCA
VCCA
VCCA
21
CLKA, I/O
CLKA, I/O
CLKA, I/O
61
GND (LP)
GND (LP)
GND (LP)
22
I/O
I/O
I/O
62
I/O
I/O
TCK, I/O
23
PRA, I/O
PRA, I/O
PRA, I/O
63
I/O
I/O
I/O
24
NC
I/O
I/O (WD)
64
GND
GND
GND
25
I/O
I/O
I/O (WD)
65
I/O
I/O
I/O
26
I/O
I/O
I/O
66
I/O
I/O
I/O
27
I/O
I/O
I/O
67
I/O
I/O
I/O
28
NC
I/O
I/O
68
I/O
I/O
I/O
29
I/O
I/O
I/O (WD)
69
GND
GND
GND
30
GND
GND
GND
70
NC
I/O
I/O
31
NC
I/O
I/O (WD)
71
I/O
I/O
I/O
32
I/O
I/O
I/O
72
I/O
I/O
I/O
33
I/O
I/O
I/O
73
I/O
I/O
I/O
34
I/O
I/O
I/O
74
I/O
I/O
I/O
35
NC
VCCI
VCCI
75
NC
I/O
I/O
36
I/O
I/O
I/O (WD)
76
I/O
I/O
I/O
37
I/O
I/O
I/O (WD)
77
NC
I/O
I/O
38
SDI, I/O
SDI, I/O
SDI, I/O
78
I/O
I/O
I/O
39
I/O
I/O
I/O
79
NC
I/O
I/O
40
GND
GND
GND
80
GND
GND
GND
v5.0
89
40MX and 42MX FPGA Families
160- P in P Q FP (C ont inu ed)
Pin
Number
A42MX09
Function
A42MX16
Function
A42MX24
Fucntion
Pin
Number
A42MX09
Function
A42MX16
Function
A42MX24
Fucntion
81
I/O
I/O
I/O
121
I/O
I/O
I/O
82
SDO, I/O
SDO, I/O
SDO, TDO, I/O
122
I/O
I/O
I/O
83
I/O
I/O
I/O (WD)
123
I/O
I/O
I/O
84
I/O
I/O
I/O (WD)
124
NC
I/O
I/O
85
I/O
I/O
I/O
125
GND
GND
GND
86
NC
VCCI
VCCI
126
I/O
I/O
I/O
87
I/O
I/O
I/O
127
I/O
I/O
I/O
88
I/O
I/O
I/O (WD)
128
I/O
I/O
I/O
89
GND
GND
GND
129
NC
I/O
I/O
90
NC
I/O
I/O
130
GND
GND
GND
91
I/O
I/O
I/O
131
I/O
I/O
I/O
92
I/O
I/O
I/O
132
I/O
I/O
I/O
93
I/O
I/O
I/O
133
I/O
I/O
I/O
94
I/O
I/O
I/O
134
I/O
I/O
I/O
95
I/O
I/O
I/O
135
NC
VCCA
VCCA
96
I/O
I/O
I/O (WD)
136
I/O
I/O
I/O
97
I/O
I/O
I/O
137
I/O
I/O
I/O
98
VCCA
VCCA
VCCA
138
NC
VCCA
VCCA
99
GND
GND
GND
139
VCCI
VCCI
VCCI
100
NC
I/O
I/O
140
GND
GND
GND
101
I/O
I/O
I/O
141
NC
I/O
I/O
102
I/O
I/O
I/O
142
I/O
I/O
I/O
103
NC
I/O
I/O
143
I/O
I/O
I/O
104
I/O
I/O
I/O
144
I/O
I/O
I/O
105
I/O
I/O
I/O
145
GND
GND
GND
106
I/O
I/O
I/O (WD)
146
NC
I/O
I/O
107
I/O
I/O
I/O (WD)
147
I/O
I/O
I/O
108
I/O
I/O
I/O
148
I/O
I/O
I/O
109
GND
GND
GND
149
I/O
I/O
I/O
110
NC
I/O
I/O
150
NC
VCCA
VCCA
111
I/O
I/O
I/O (WD)
151
NC
I/O
I/O
112
I/O
I/O
I/O (WD)
152
NC
I/O
I/O
90
113
I/O
I/O
I/O
153
NC
I/O
I/O
114
NC
VCCI
VCCI
154
NC
I/O
I/O
115
I/O
I/O
I/O (WD)
155
GND
GND
GND
116
NC
I/O
I/O (WD)
156
I/O
I/O
I/O
117
I/O
I/O
I/O
157
I/O
I/O
I/O
118
I/O
I/O
TDI, I/O
158
I/O
I/O
I/O
119
I/O
I/O
TMS, I/O
159
MODE
MODE
MODE
120
GND
GND
GND
160
GND
GND
GND
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s (continued)
208-Pin PQFP Package (Top View)
208
1
208-Pin PQFP
v5.0
91
40MX and 42MX FPGA Families
208- P in P Q FP
Pin
Number
A42MX16
Function
1
GND
GND
2
NC
VCCA
3
MODE
MODE
4
I/O
5
6
92
A42MX24
Function
A42MX36
Function
Pin
Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
GND
43
NC
I/O
I/O
VCCA
44
I/O
I/O
I/O
MODE
45
I/O
I/O
I/O
I/O
I/O
46
I/O
I/O
I/O
I/O
I/O
I/O
47
I/O
I/O
I/O
I/O
I/O
I/O
48
I/O
I/O
I/O
7
I/O
I/O
I/O
49
I/O
I/O
I/O
8
I/O
I/O
I/O
50
NC
I/O
I/O
9
NC
I/O
I/O
51
NC
I/O
I/O
10
NC
I/O
I/O
52
GND
GND
GND
11
NC
I/O
I/O
53
GND
GND
GND
12
I/O
I/O
I/O
54
I/O
TMS, I/O
TMS, I/O
13
I/O
I/O
I/O
55
I/O
TDI, I/O
TDI, I/O
14
I/O
I/O
I/O
56
I/O
I/O
I/O
15
I/O
I/O
I/O
57
I/O
I/O (WD)
I/O (WD)
16
NC
I/O
I/O
58
I/O
I/O (WD)
I/O (WD)
17
VCCA
VCCA
VCCA
59
I/O
I/O
I/O
18
I/O
I/O
I/O
60
VCCI
VCCI
VCCI
19
I/O
I/O
I/O
61
NC
I/O
I/O
20
I/O
I/O
I/O
62
NC
I/O
I/O
21
I/O
I/O
I/O
63
I/O
I/O
I/O
22
GND
GND
GND
64
I/O
I/O
I/O
23
I/O
I/O
I/O
65
I/O
I/O
QCLKA, I/O
24
I/O
I/O
I/O
66
I/O
I/O (WD)
I/O (WD)
25
I/O
I/O
I/O
67
NC
I/O (WD)
I/O (WD)
26
I/O
I/O
I/O
68
NC
I/O
I/O
27
GND
GND
GND
69
I/O
I/O
I/O
28
VCCI
VCCI
VCCI
70
I/O
I/O (WD)
I/O (WD)
29
VCCA
VCCA
VCCA
71
I/O
I/O (WD)
I/O (WD)
30
I/O
I/O
I/O
72
I/O
I/O
I/O
31
I/O
I/O
I/O
73
I/O
I/O
I/O
32
VCCA
VCCA
VCCA
74
I/O
I/O
I/O
33
I/O
I/O
I/O
75
I/O
I/O
I/O
34
I/O
I/O
I/O
76
I/O
I/O
I/O
35
I/O
I/O
I/O
77
I/O
I/O
I/O
36
I/O
I/O
I/O
78
GND
GND
GND
37
I/O
I/O
I/O
79
VCCA
VCCA
VCCA
38
I/O
I/O
I/O
80
NC
VCCI
VCCI
39
I/O
I/O
I/O
81
I/O
I/O
I/O
40
I/O
I/O
I/O
82
I/O
I/O
I/O
41
NC
I/O
I/O
83
I/O
I/O
I/O
42
NC
I/O
I/O
84
I/O
I/O
I/O
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
208- P in P Q FP (C ont inu ed)
Pin
Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
Pin
Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
85
I/O
I/O (WD)
I/O (WD)
127
I/O
I/O
I/O
86
I/O
I/O (WD)
I/O (WD)
128
I/O
TCK, I/O
TCK, I/O
87
I/O
I/O
I/O
129
GND (LP)
GND (LP)
GND (LP)
88
I/O
I/O
I/O
130
VCCA
VCCA
VCCA
89
NC
I/O
I/O
131
GND
GND
GND
90
NC
I/O
I/O
132
VCCI
VCCI
VCCI
91
I/O
I/O
QCLKB, I/O
133
VCCA
VCCA
VCCA
92
I/O
I/O
I/O
134
I/O
I/O
I/O
93
I/O
I/O (WD)
I/O (WD)
135
I/O
I/O
I/O
94
I/O
I/O (WD)
I/O (WD)
136
VCCA
VCCA
VCCA
95
NC
I/O
I/O
137
I/O
I/O
I/O
96
NC
I/O
I/O
138
I/O
I/O
I/O
97
NC
I/O
I/O
139
I/O
I/O
I/O
98
VCCI
VCCI
VCCI
140
I/O
I/O
I/O
99
I/O
I/O
I/O
141
NC
I/O
I/O
100
I/O
I/O (WD)
I/O (WD)
142
I/O
I/O
I/O
101
I/O
I/O (WD)
I/O (WD)
143
I/O
I/O
I/O
102
I/O
I/O
I/O
144
I/O
I/O
I/O
103
SDO, I/O
145
I/O
I/O
I/O
104
I/O
146
NC
I/O
I/O
105
GND
GND
GND
147
NC
I/O
I/O
106
NC
VCCA
VCCA
148
NC
I/O
I/O
107
I/O
I/O
I/O
149
NC
I/O
I/O
108
I/O
I/O
I/O
150
GND
GND
GND
109
I/O
I/O
I/O
151
I/O
I/O
I/O
110
I/O
I/O
I/O
152
I/O
I/O
I/O
111
I/O
I/O
I/O
153
I/O
I/O
I/O
112
NC
I/O
I/O
154
I/O
I/O
I/O
113
NC
I/O
I/O
155
I/O
I/O
I/O
114
NC
I/O
I/O
156
I/O
I/O
I/O
115
NC
I/O
I/O
157
GND
GND
GND
116
I/O
I/O
I/O
158
I/O
I/O
I/O
117
I/O
I/O
I/O
159
SDI, I/O
SDI, I/O
SDI, I/O
118
I/O
I/O
I/O
160
I/O
I/O
I/O
119
I/O
I/O
I/O
161
I/O
I/O (WD)
I/O (WD)
120
I/O
I/O
I/O
162
I/O
I/O (WD)
I/O (WD)
121
I/O
I/O
I/O
163
I/O
I/O
I/O
122
I/O
I/O
I/O
164
VCCI
VCCI
VCCI
123
I/O
I/O
I/O
165
NC
I/O
I/O
124
I/O
I/O
I/O
166
NC
I/O
I/O
SDO, TDO, I/O SDO, TDO, I/O
I/O
I/O
125
I/O
I/O
I/O
167
I/O
I/O
I/O
126
GND
GND
GND
168
I/O
I/O (WD)
I/O (WD)
v5.0
93
40MX and 42MX FPGA Families
208- P in P Q FP (C ont inu ed)
Pin
Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
169
I/O
I/O (WD)
I/O (WD)
189
I/O
I/O
I/O
170
I/O
I/O
I/O
190
I/O
I/O (WD)
I/O (WD)
171
NC
I/O
QCLKD, I/O
191
I/O
I/O (WD)
I/O (WD)
172
I/O
I/O
I/O
192
I/O
I/O
I/O
94
Pin
Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
173
I/O
I/O
I/O
193
NC
I/O
I/O
174
I/O
I/O
I/O
194
NC
I/O (WD)
I/O (WD)
175
I/O
I/O
I/O
195
NC
I/O (WD)
I/O (WD)
176
I/O
I/O (WD)
I/O (WD)
196
I/O
I/O
QCLKC, I/O
177
I/O
I/O (WD)
I/O (WD)
197
NC
I/O
I/O
178
PRA, I/O
PRA, I/O
PRA, I/O
198
NC
I/O
I/O
179
I/O
I/O
I/O
199
I/O
I/O
I/O
180
CLKA, I/O
CLKA, I/O
CLKA, I/O
200
I/O
I/O
I/O
181
NC
I/O
I/O
201
NC
I/O
I/O
182
NC
VCCI
VCCI
202
VCCI
VCCI
VCCI
183
VCCA
VCCA
VCCA
203
I/O
I/O (WD)
I/O (WD)
184
GND
GND
GND
204
I/O
I/O (WD)
I/O (WD)
185
I/O
I/O
I/O
205
I/O
I/O
I/O
186
CLKB, I/O
CLKB, I/O
CLKB, I/O
206
I/O
I/O
I/O
187
I/O
I/O
I/O
207
DCLK, I/O
DCLK, I/O
DCLK, I/O
188
PRB, I/O
PRB, I/O
PRB, I/O
208
I/O
I/O
I/O
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s (continued)
•
•
•
240-Pin PQFP Package (Top View)
240
1
240-Pin
PQFP
•
•
•
•
•
•
•
•
•
v5.0
95
40MX and 42MX FPGA Families
240- P in P Q FP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
1
I/O
41
I/O
81
I/O
121
GND
2
DCLK, I/O
42
I/O
82
I/O
122
I/O
3
I/O
43
I/O
83
I/O
123
SDO, TDO, I/O
4
I/O
44
I/O
84
I/O
124
I/O
5
I/O
45
QCLKD, I/O
85
VCCA
125
I/O (WD)
6
I/O (WD)
46
I/O
86
I/O
126
I/O (WD)
7
I/O (WD)
47
I/O (WD)
87
I/O
127
I/O
8
VCCI
48
I/O (WD)
88
VCCA
128
VCCI
9
I/O
49
I/O
89
VCCI
129
I/O
10
I/O
50
I/O
90
VCCA
130
I/O
11
I/O
51
I/O
91
GND (LP)
131
I/O
12
I/O
52
VCCI
92
TCK, I/O
132
I/O (WD)
96
13
I/O
53
I/O
93
I/O
133
I/O (WD)
14
I/O
54
I/O (WD)
94
GND
134
I/O
15
QCLKC, I/O
55
I/O (WD)
95
I/O
135
QCLKB, I/O
16
I/O
56
I/O
96
I/O
136
I/O
17
I/O (WD)
57
SDI, I/O
97
I/O
137
I/O
18
I/O (WD)
58
I/O
98
I/O
138
I/O
19
I/O
59
VCCA
99
I/O
139
I/O
20
I/O
60
GND
100
I/O
140
I/O
21
I/O (WD)
61
GND
101
I/O
141
I/O
22
I/O (WD)
62
I/O
102
I/O
142
I/O (WD)
23
I/O
63
I/O
103
I/O
143
I/O (WD)
24
PRB, I/O
64
I/O
104
I/O
144
I/O
25
I/O
65
I/O
105
I/O
145
I/O
26
CLKB, I/O
66
I/O
106
I/O
146
I/O
27
I/O
67
I/O
107
I/O
147
I/O
28
GND
68
I/O
108
VCCI
148
I/O
29
VCCA
69
I/O
109
I/O
149
I/O
30
VCCI
70
I/O
110
I/O
150
VCCI
31
I/O
71
VCCI
111
I/O
151
VCCA
32
CLKA, I/O
72
I/O
112
I/O
152
GND
33
I/O
73
I/O
113
I/O
153
I/O
34
PRA, I/O
74
I/O
114
I/O
154
I/O
35
I/O
75
I/O
115
I/O
155
I/O
36
I/O
76
I/O
116
I/O
156
I/O
37
I/O (WD)
77
I/O
117
I/O
157
I/O
38
I/O (WD)
78
I/O
118
VCCA
158
I/O
39
I/O
79
I/O
119
GND
159
I/O (WD)
40
I/O
80
I/O
120
GND
160
I/O (WD)
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
240- P in P Q FP (C ont inu ed)
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
161
I/O
181
VCCA
201
I/O
221
I/O
162
I/O
182
GND
202
I/O
222
I/O
163
I/O (WD)
183
I/O
203
I/O
223
I/O
164
I/O (WD)
184
I/O
204
I/O
224
I/O
165
I/O
185
I/O
205
I/O
225
I/O
166
QCLKA, I/O
186
I/O
206
VCCA
226
I/O
167
I/O
187
I/O
207
I/O
227
VCCI
168
I/O
188
I/O
208
I/O
228
I/O
169
I/O
189
I/O
209
VCCA
229
I/O
170
I/O
190
I/O
210
VCCI
230
I/O
171
I/O
191
I/O
211
I/O
231
I/O
172
VCCI
192
VCCI
212
I/O
232
I/O
173
I/O
193
I/O
213
I/O
233
I/O
174
I/O (WD)
194
I/O
214
I/O
234
I/O
175
I/O (WD)
195
I/O
215
I/O
235
I/O
176
I/O
196
I/O
216
I/O
236
I/O
177
I/O
197
I/O
217
I/O
237
GND
178
TDI, I/O
198
I/O
218
I/O
238
MODE
179
TMS, I/O
199
I/O
219
VCCA
239
VCCA
180
GND
200
I/O
220
I/O
240
GND
v5.0
97
40MX and 42MX FPGA Families
Package Pin Assignments (continued)
80-Pin VQFP
1
80
80-Pin
VQFP
98
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
80- Pi n VQFP
Pin Number
A40MX02
Function
A40MX04
Function
Pin Number
A40MX02
Function
A40MX04
Function
1
I/O
I/O
41
NC
I/O
2
NC
I/O
42
NC
I/O
3
NC
I/O
43
NC
I/O
4
NC
I/O
44
I/O
I/O
5
I/O
I/O
45
I/O
I/O
6
I/O
I/O
46
I/O
I/O
7
GND
GND
47
GND
GND
8
I/O
I/O
48
I/O
I/O
9
I/O
I/O
49
I/O
I/O
10
I/O
I/O
50
CLK, I/O
CLK, I/O
11
I/O
I/O
51
I/O
I/O
12
I/O
I/O
52
MODE
MODE
13
VCC
VCC
53
VCC
VCC
14
I/O
I/O
54
NC
I/O
15
I/O
I/O
55
NC
I/O
16
I/O
I/O
56
NC
I/O
17
NC
I/O
57
SDI, I/O
SDI, I/O
18
NC
I/O
58
DCLK, I/O
DCLK, I/O
19
NC
I/O
59
PRA, I/O
PRA, I/O
20
VCC
VCC
60
NC
NC
21
I/O
I/O
61
PRB, I/O
PRB, I/O
22
I/O
I/O
62
I/O
I/O
23
I/O
I/O
63
I/O
I/O
24
I/O
I/O
64
I/O
I/O
25
I/O
I/O
65
I/O
I/O
26
I/O
I/O
66
I/O
I/O
27
GND
GND
67
I/O
I/O
28
I/O
I/O
68
GND
GND
29
I/O
I/O
69
I/O
I/O
30
I/O
I/O
70
I/O
I/O
31
I/O
I/O
71
I/O
I/O
32
I/O
I/O
72
I/O
I/O
33
VCC
VCC
73
I/O
I/O
34
I/O
I/O
74
VCC
VCC
35
I/O
I/O
75
I/O
I/O
36
I/O
I/O
76
I/O
I/O
37
I/O
I/O
77
I/O
I/O
38
I/O
I/O
78
I/O
I/O
39
I/O
I/O
79
I/O
I/O
40
I/O
I/O
80
I/O
I/O
v5.0
99
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s (continued)
100- P in VQF P P ackag e (T op V iew )
100
1
100-Pin
VQFP
100
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
100-Pin VQFP Package
Pin Number
A42MX09
Function
A42MX16
Function
Pin Number
A42MX09
Function
A42MX16
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
MODE
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
VCCI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
SDO, I/O
I/O
MODE
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
NC
VCCI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
SDO, I/O
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND (LP)
VCCA
VCCI
VCCA
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
SDI, I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
PRA, I/O
I/O
CLKA, I/O
VCCA
I/O
CLKB, I/O
I/O
PRB, I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND (LP)
VCCA
VCCI
VCCA
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
SDI, I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
PRA, I/O
I/O
CLKA, I/O
VCCA
I/O
CLKB, I/O
I/O
PRB, I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
v5.0
101
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s (continued)
176-Pin TQFP Package (Top View)
176
1
176-Pin
TQFP
102
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
176- P in T Q FP
Pin
Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin
Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
1
GND
GND
GND
45
GND
GND
GND
2
MODE
MODE
MODE
46
I/O
I/O
TMS, I/O
3
I/O
I/O
I/O
47
I/O
I/O
TDI, I/O
4
I/O
I/O
I/O
48
I/O
I/O
I/O
5
I/O
I/O
I/O
49
I/O
I/O
I/O (WD)
6
I/O
I/O
I/O
50
I/O
I/O
I/O (WD)
7
I/O
I/O
I/O
51
I/O
I/O
I/O
8
NC
NC
I/O
52
NC
VCCI
VCCI
9
I/O
I/O
I/O
53
I/O
I/O
I/O
10
NC
I/O
I/O
54
NC
I/O
I/O
11
NC
I/O
I/O
55
NC
I/O
I/O (WD)
12
I/O
I/O
I/O
56
I/O
I/O
I/O (WD)
13
NC
VCCA
VCCA
57
NC
NC
I/O
14
I/O
I/O
I/O
58
I/O
I/O
I/O
15
I/O
I/O
I/O
59
I/O
I/O
I/O (WD)
16
I/O
I/O
I/O
60
I/O
I/O
I/O (WD)
17
I/O
I/O
I/O
61
NC
I/O
I/O
18
GND
GND
GND
62
I/O
I/O
I/O
19
NC
I/O
I/O
63
I/O
I/O
I/O
20
NC
I/O
I/O
64
NC
I/O
I/O
21
I/O
I/O
I/O
65
I/O
I/O
I/O
22
NC
I/O
I/O
66
NC
I/O
I/O
23
GND
GND
GND
67
GND
GND
GND
24
NC
VCCI
VCCI
68
VCCA
VCCA
VCCA
25
VCCA
VCCA
VCCA
69
I/O
I/O
I/O (WD)
26
NC
I/O
I/O
70
I/O
I/O
I/O (WD)
27
NC
I/O
I/O
71
I/O
I/O
I/O
28
VCCI
VCCA
VCCA
72
I/O
I/O
I/O
29
NC
I/O
I/O
73
I/O
I/O
I/O
30
I/O
I/O
I/O
74
NC
I/O
I/O
31
I/O
I/O
I/O
75
I/O
I/O
I/O
32
I/O
I/O
I/O
76
I/O
I/O
I/O
33
NC
NC
I/O
77
NC
NC
I/O (WD)
34
I/O
I/O
I/O
78
NC
I/O
I/O (WD)
35
I/O
I/O
I/O
79
I/O
I/O
I/O
36
I/O
I/O
I/O
80
NC
I/O
I/O
37
NC
I/O
I/O
81
I/O
I/O
I/O
38
NC
NC
I/O
82
NC
VCCI
VCCI
39
I/O
I/O
I/O
83
I/O
I/O
I/O
40
I/O
I/O
I/O
84
I/O
I/O
I/O (WD)
41
I/O
I/O
I/O
85
I/O
I/O
I/O (WD)
42
I/O
I/O
I/O
86
NC
I/O
I/O
43
I/O
I/O
I/O
87
SDO, I/O
SDO, I/O
SDO, TDO, I/O
44
I/O
I/O
I/O
88
I/O
I/O
I/O
v5.0
103
40MX and 42MX FPGA Families
176- P in T Q FP (C ont inu ed)
Pin
Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin
Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
89
GND
GND
GND
133
GND
GND
GND
90
I/O
I/O
I/O
134
I/O
I/O
I/O
91
I/O
I/O
I/O
135
SDI, I/O
SDI, I/O
SDI, I/O
92
I/O
I/O
I/O
136
NC
I/O
I/O
93
I/O
I/O
I/O
137
I/O
I/O
I/O (WD)
94
I/O
I/O
I/O
138
I/O
I/O
I/O (WD)
95
I/O
I/O
I/O
139
I/O
I/O
I/O
96
NC
I/O
I/O
140
NC
VCCI
VCCI
97
NC
I/O
I/O
141
I/O
I/O
I/O
98
I/O
I/O
I/O
142
I/O
I/O
I/O
104
99
I/O
I/O
I/O
143
NC
I/O
I/O
100
I/O
I/O
I/O
144
NC
I/O
I/O (WD)
101
NC
NC
I/O
145
NC
NC
I/O (WD)
102
I/O
I/O
I/O
146
I/O
I/O
I/O
103
NC
I/O
I/O
147
NC
I/O
I/O
104
I/O
I/O
I/O
148
I/O
I/O
I/O
105
I/O
I/O
I/O
149
I/O
I/O
I/O
106
GND
GND
GND
150
I/O
I/O
I/O (WD)
107
NC
I/O
I/O
151
NC
I/O
I/O (WD)
108
NC
I/O
TCK, I/O
152
PRA, I/O
PRA, I/O
PRA, I/O
109
GND (LP)
GND (LP)
GND (LP)
153
I/O
I/O
I/O
110
VCCA
VCCA
VCCA
154
CLKA, I/O
CLKA, I/O
CLKA, I/O
111
GND
GND
GND
155
VCCA
VCCA
VCCA
112
VCCI
VCCI
VCCI
156
GND
GND
GND
113
VCCA
VCCA
VCCA
157
I/O
I/O
I/O
114
NC
I/O
I/O
158
CLKB, I/O
CLKB, I/O
CLKB, I/O
115
NC
I/O
I/O
159
I/O
I/O
I/O
116
NC
VCCA
VCCA
160
PRB, I/O
PRB, I/O
PRB, I/O
117
I/O
I/O
I/O
161
NC
I/O
I/O (WD)
118
I/O
I/O
I/O
162
I/O
I/O
I/O (WD)
119
I/O
I/O
I/O
163
I/O
I/O
I/O
120
I/O
I/O
I/O
164
I/O
I/O
I/O
121
NC
NC
I/O
165
NC
NC
I/O (WD)
122
I/O
I/O
I/O
166
NC
I/O
I/O (WD)
123
I/O
I/O
I/O
167
I/O
I/O
I/O
124
NC
I/O
I/O
168
NC
I/O
I/O
125
NC
I/O
I/O
169
I/O
I/O
I/O
126
NC
NC
I/O
170
NC
VCCI
VCCI
127
I/O
I/O
I/O
171
I/O
I/O
I/O (WD)
128
I/O
I/O
I/O
172
I/O
I/O
I/O (WD)
129
I/O
I/O
I/O
173
NC
I/O
I/O
130
I/O
I/O
I/O
174
I/O
I/O
I/O
131
I/O
I/O
I/O
175
DCLK, I/O
DCLK, I/O
DCLK, I/O
132
I/O
I/O
I/O
176
I/O
I/O
I/O
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s
208-Pin CQFP (Top View)
208 207 206 205 204 203 202 201 200
164 163 162 161 160 159 158 157
Pin #1
Index
1
156
2
155
3
154
4
153
5
152
6
151
7
150
8
149
A42MX36
208-Pin
CQFP
44
113
45
112
46
111
47
110
48
109
49
108
50
107
51
106
52
105
53 54 55 56 57 58 59 60 61
v5.0
97 98 99 100 101 102 103 104
105
40MX and 42MX FPGA Families
208-Pin CQFP
Pin Number
A42MX36
Function
Pin Number
A42MX36
Function
Pin Number
A42MX36
Function
Pin Number
A42MX36
Function
1
GND
40
I/O
79
VCCA
118
I/O
2
VCCA
41
I/O
80
VCCI
119
I/O
3
MODE
42
I/O
81
I/O
120
I/O
4
I/O
43
I/O
82
I/O
121
I/O
5
I/O
44
I/O
83
I/O
122
I/O
6
I/O
45
I/O
84
I/O
123
I/O
7
I/O
46
I/O
85
I/O (WD)
124
I/O
8
I/O
47
I/O
86
I/O (WD)
125
I/O
9
I/O
48
I/O
87
I/O
126
GND
10
I/O
49
I/O
88
I/O
127
I/O
11
I/O
50
I/O
89
I/O
128
TCK, I/O
12
I/O
51
I/O
90
I/O
129
GND (LP)
13
I/O
52
GND
91
QCLKB, I/O
130
VCCA
14
I/O
53
GND
92
I/O
131
GND
15
I/O
54
TMS, I/O
93
I/O (WD)
132
VCCI
16
I/O
55
TDI, I/O
94
I/O (WD)
133
VCCA
17
VCCA
56
I/O
95
I/O
134
I/O
18
I/O
57
I/O (WD)
96
I/O
135
I/O
19
I/O
58
I/O (WD)
97
I/O
136
VCCA
20
I/O
59
I/O
98
VCCI
137
I/O
21
I/O
60
VCCI
99
I/O
138
I/O
22
GND
61
I/O
100
I/O (WD)
139
I/O
23
I/O
62
I/O
101
I/O (WD)
140
I/O
24
I/O
63
I/O
102
I/O
141
I/O
25
I/O
64
I/O
103
TDO, I/O
142
I/O
26
I/O
65
QCLKA, I/O
104
I/O
143
I/O
27
GND
66
I/O (WD)
105
GND
144
I/O
28
VCCI
67
I/O (WD)
106
VCCA
145
I/O
29
VCCA
68
I/O
107
I/O
146
I/O
30
I/O
69
I/O
108
I/O
147
I/O
31
I/O
70
I/O (WD)
109
I/O
148
I/O
32
VCCA
71
I/O (WD)
110
I/O
149
I/O
33
I/O
72
I/O
111
I/O
150
GND
34
I/O
73
I/O
112
I/O
151
I/O
35
I/O
74
I/O
113
I/O
152
I/O
36
I/O
75
I/O
114
I/O
153
I/O
37
I/O
76
I/O
115
I/O
154
I/O
38
I/O
77
I/O
116
I/O
155
I/O
39
I/O
78
GND
117
I/O
156
I/O
106
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
208-Pin CQFP (Continued)
Pin Number
A42MX36
Function
Pin Number
A42MX36
Function
Pin Number
A42MX36
Function
Pin Number
A42MX36
Function
157
GND
170
I/O
183
VCCA
196
QCLKC, I/O
158
I/O
171
QCLKD, I/O
184
GND
197
I/O
159
SDI, I/O
172
I/O
185
I/O
198
I/O
160
I/O
173
I/O
186
CLKB, I/O
199
I/O
161
I/O (WD)
174
I/O
187
I/O
200
I/O
162
I/O (WD)
175
I/O
188
PRB, I/O
201
I/O
163
I/O
176
I/O (WD)
189
I/O
202
VCCI
164
VCCI
177
I/O (WD)
190
I/O (WD)
203
I/O (WD)
165
I/O
178
PRA, I/O
191
I/O (WD)
204
I/O (WD)
166
I/O
179
I/O
192
I/O
205
I/O
167
I/O
180
CLKA, I/O
193
I/O
206
I/O
168
I/O (WD)
181
I/O
194
I/O (WD)
207
DCLK, I/O
169
I/O (WD)
182
VCCI
195
I/O (WD)
208
I/O
v5.0
107
40MX and 42MX FPGA Families
Pa c ka ge P i n A s si g nm e n t s (continued)
256-Pin CQFP (Top View)
256 255 254 253 252 251 250 249 248
200 199 198 197 196 195 194 193
Pin #1
Index
1
192
2
191
3
190
4
189
5
188
6
187
7
186
8
185
A42MX36
256-Pin
CQFP
56
137
57
136
58
135
59
134
60
133
61
132
62
131
63
130
64
129
65 66 67 68 69 70 71 72 73
108
121 122 123 124 125 126 127 128
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
256-Pin CQFP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
1
NC
44
I/O
87
I/O, (WD)
130
NC
2
GND
45
I/O
88
I/O, (WD)
131
GND
3
I/O
46
I/O
89
I/O
132
I/O
4
I/O
47
I/O
90
I/O
133
I/O
5
I/O
48
GND
91
I/O
134
I/O
6
I/O
49
I/O
92
I/O
135
I/O
7
I/O
50
I/O
93
I/O
136
I/O
8
I/O
51
I/O
94
I/O
137
I/O
9
I/O
52
I/O
95
VCCI
138
I/O
10
GND
53
I/O
96
VCCA
139
GND
11
I/O
54
I/O
97
GND
140
I/O
12
I/O
55
I/O
98
GND
141
I/O
13
I/O
56
I/O
99
I/O
142
I/O
14
I/O
57
I/O
100
I/O
143
I/O
15
I/O
58
I/O
101
I/O
144
I/O
16
I/O
59
I/O
102
I/O
145
I/O
17
I/O
60
VCCA
103
I/O
146
I/O
18
I/O
61
GND
104
I/O
147
I/O
19
I/O
62
GND
105
I/O, (WD)
148
I/O
20
I/O
63
NC
106
I/O, (WD)
149
I/O
21
I/O
64
NC
107
I/O
150
I/O
22
I/O
65
NC
108
I/O
151
I/O
23
I/O
66
I/O
109
I/O, (WD)
152
I/O
24
I/O
67
SDO, TDO, I/O
110
I/O, (WD)
153
I/O
25
I/O
68
I/O
111
I/O
154
I/O
26
VCCA
69
I/O (WD)
112
QCLKA, I/O
155
VCCA
27
I/O
70
I/O (WD)
113
I/O
156
I/O
28
I/O
71
I/O
114
GND
157
I/O
29
VCCA
72
VCCI
115
I/O
158
VCCA
30
VCCI
73
I/O
116
I/O
159
VCCI
31
GND
74
I/O
117
I/O
160
GND
32
VCCA
75
I/O
118
I/O
161
I/O
33
GND
76
I/O (WD)
119
VCCI
162
I/O
34
TCK, I/O
77
GND
120
I/O
163
I/O
35
I/O
78
I/O, (WD)
121
I/O, (WD)
164
I/O
36
GND
79
I/O
122
I/O, (WD)
165
GND
37
I/O
80
QCLKB, I/O
123
I/O
166
I/O
38
I/O
81
I/O
124
I/O
167
I/O
39
I/O
82
I/O
125
I/O
168
I/O
40
I/O
83
I/O
126
I/O
169
I/O
41
I/O
84
I/O
127
GND
170
VCCA
42
I/O
85
I/O
128
NC
171
I/O
43
I/O
86
I/O
129
NC
172
I/O
v5.0
109
40MX and 42MX FPGA Families
256-Pin CQFP (Continued)
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
173
I/O
194
I/O
215
I/O (WD)
236
I/O
174
I/O
195
DCLK, I/O
216
I/O (WD)
237
I/O
110
175
I/O
196
I/O
217
I/O
238
I/O
176
I/O
197
I/O
218
PRB, I/O
239
I/O
177
I/O
198
I/O
219
I/O
240
QCLKD, I/O
178
I/O
199
I/O (WD)
220
CLKB, I/O
241
I/O
179
I/O
200
I/O (WD)
221
I/O
242
I/O (WD)
180
GND
201
VCCI
222
GND
243
GND
181
I/O
202
I/O
223
GND
244
I/O (WD)
182
I/O
203
I/O
224
VCCA
245
I/O
183
I/O
204
I/O
225
VCCI
246
I/O
184
I/O
205
I/O
226
I/O
247
I/O
185
I/O
206
GND
227
CLKA, I/O
248
VCCI
186
I/O
207
I/O
228
I/O
249
I/O
187
I/O
208
I/O
229
PRA, I/O
250
I/O (WD)
188
MODE
209
QCLKC, I/O
230
I/O
251
I/O (WD)
189
VCCA
210
I/O
231
I/O
252
I/O
190
GND
211
I/O (WD)
232
I/O (WD)
253
SDI, I/O
191
NC
212
I/O (WD)
233
I/O (WD)
254
I/O
192
NC
213
I/O
234
I/O
255
GND
193
NC
214
I/O
235
I/O
256
NC
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
Pa c ka ge P i n A s si g nm e n t s (continued)
272- P in BGA P ack age (T op Vie w)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
A
B
C
D
E
F
G
272-Pin PBGA
H
J
K
L
M
N
P
R
T
U
V
W
Y
v5.0
111
40MX and 42MX FPGA Families
272-Pin PBGA
Ball
A42MX36
Function
Ball
A42MX36
Function
Ball
A42MX36
Function
Ball
A42MX36
Function
A1
GND
C4
I/O
E19
I/O
K10
GND
A2
GND
C5
I/O (WD)
E20
I/O
K11
GND
A3
I/O
C6
I/O
F1
I/O
K12
GND
A4
I/O (WD)
C7
QCLKC, I/O
F2
I/O
K17
I/O
A5
I/O
C8
I/O
F3
I/O
K18
VCCA
112
A6
I/O
C9
I/O
F4
VCCI
K19
VCCA
A7
I/O (WD)
C10
CLKB
F17
I/O
K20
GND (LP)
A8
I/O (WD)
C11
PRA, I/O
F18
I/O
L1
I/O
A9
I/O
C12
I/O (WD)
F19
I/O
L2
I/O
A10
I/O
C13
I/O
F20
I/O
L3
VCCA
A11
CLKA
C14
QCLKD, I/O
G1
I/O
L4
VCCA
A12
I/O
C15
I/O
G2
I/O
L9
GND
A13
I/O
C16
I/O (WD)
G3
I/O
L10
GND
A14
I/O
C17
SDI, I/O
G4
VCCI
L11
GND
A15
I/O
C18
I/O
G17
VCCI
L12
GND
A16
I/O (WD)
C19
I/O
G18
I/O
L17
VCCI
A17
I/O
C20
I/O
G19
I/O
L18
I/O
A18
I/O
D1
I/O
G20
I/O
L19
I/O
A19
GND
D2
I/O
H1
I/O
L20
TCK, I/O
A20
GND
D3
I/O
H2
I/O
M1
I/O
B1
GND
D4
I/O
H3
I/O
M2
I/O
B2
GND
D5
VCCI
H4
VCCA
M3
I/O
B3
DCLK, I/O
D6
I/O
H17
I/O
M4
VCCI
B4
I/O
D7
I/O
H18
I/O
M9
GND
B5
I/O
D8
VCCA
H19
I/O
M10
GND
B6
I/O
D9
I/O (WD)
H20
I/O
M11
GND
B7
I/O (WD)
D10
VCCI
J1
I/O
M12
GND
B8
I/O
D11
I/O
J2
I/O
M17
I/O
B9
PRB, I/O
D12
VCCI
J3
I/O
M18
I/O
B10
I/O
D13
I/O
J4
VCCI
M19
I/O
B11
I/O
D14
VCCI
J9
GND
M20
I/O
B12
I/O (WD)
D15
I/O
J10
GND
N1
I/O
B13
I/O
D16
VCCA
J11
GND
N2
I/O
B14
I/O
D17
GND
J12
GND
N3
I/O
B15
I/O (WD)
D18
I/O
J17
VCCA
N4
VCCI
B16
I/O
D19
I/O
J18
I/O
N17
VCCI
B17
I/O (WD)
D20
I/O
J19
I/O
N18
I/O
B18
I/O
E1
I/O
J20
I/O
N19
I/O
B19
GND
E2
I/O
K1
I/O
N20
I/O
B20
GND
E3
I/O
K2
I/O
P1
I/O
C1
I/O
E4
VCCA
K3
I/O
P2
I/O
C2
MODE
E17
VCCI
K4
VCCI
P3
I/O
C3
GND
E18
I/O
K9
GND
P4
VCCA
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
272-Pin PBGA (Continued)
Ball
A42MX36
Function
Ball
A42MX36
Function
Ball
A42MX36
Function
Ball
A42MX36
Function
P17
I/O
U6
I/O (WD)
V11
I/O
W16
I/O (WD)
P18
I/O
U7
I/O
V12
I/O
W17
I/O
P19
I/O
U8
I/O
V13
I/O (WD)
W18
I/O (WD)
P20
I/O
U9
I/O (WD)
V14
I/O
W19
GND
R1
I/O
U10
VCCA
V15
I/O (WD)
W20
GND
R2
I/O
U11
VCCI
V16
I/O
Y1
GND
R3
I/O
U12
I/O
V17
I/O
Y2
GND
R4
VCCI
U13
I/O
V18
SDO, TDO, I/O
Y3
I/O
R17
VCCI
U14
QCLKB, I/O
V19
I/O
Y4
TDI, I/O
R18
I/O
U15
I/O
V20
I/O
Y5
I/O (WD)
R19
I/O
U16
VCCI
W1
GND
Y6
I/O
R20
I/O
U17
I/O
W2
GND
Y7
QCLKA, I/O
T1
I/O
U18
GND
W3
I/O
Y8
I/O
T2
I/O
U19
I/O
W4
TMS, I/O
Y9
I/O
T3
I/O
U20
I/O
W5
I/O
Y10
I/O
T4
I/O
V1
I/O
W6
I/O
Y11
I/O
T17
VCCA
V2
I/O
W7
I/O
Y12
I/O
T18
I/O
V3
GND
W8
I/O (WD)
Y13
I/O
T19
I/O
V4
GND
W9
I/O (WD)
Y14
I/O
T20
I/O
V5
I/O
W10
I/O
Y15
I/O
U1
I/O
V6
I/O
W11
I/O
Y16
I/O
U2
I/O
V7
I/O
W12
I/O
Y17
I/O
U3
I/O
V8
I/O (WD)
W13
I/O (WD)
Y18
I/O (WD)
U4
I/O
V9
I/O
W14
I/O
Y19
GND
U5
VCCI
V10
I/O
W15
I/O
Y20
GND
v5.0
113
40MX and 42MX FPGA Families
Li s t o f C ha ng e s
The following table lists critical changes that were made in the current version of the document.
Previous version
Changes in current version (v6.0)
Page
v4.0
Because the changes in this data sheet are extensive and technical in nature, this should ALL
be viewed as a new document. Please read it as you would a data sheet that is published
for the first time.
Note that the “Package Characteristics and Mechanical Drawings” section has been
eliminated from the data sheet. The mechanical drawings are now contained in a separate
document, “Package Characteristics and Mechanical Drawings,” available on the Actel
web site.
D at a S he et Ca t e g o r i e s
In order to provide the latest information to designers, some data sheets are published before data has been fully
characterized. These data sheets are marked as “Advanced” or Preliminary” data sheets. The definition of these categories
are as follows:
Adv anc ed
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This
information can be used as estimates, but not for production.
P rel im i nar y
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be
correct, but changes are possible.
Unm ar ked (pr odu ct ion)
The data sheet contains information that is considered to be final.
114
v5.0
4 0 M X a n d 4 2 M X F PG A F a m il ie s
v5.0
115
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd.
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Basingstoke, Hampshire RG24 8AG
United Kingdom
Tel: +44 (0)1256 305600
Fax: +44 (0)1256 355420
Actel Corporation
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USA
Tel: (408) 739-1010
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Fax: +81 03-3445-7668
5172136-6/2.01