A65H73361/A65H83181 Series 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Preliminary Document Title 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Revision History Rev. No. 2.0 PRELIMINARY History Issue Date Remark Add JTAG standard February 12, 1999 Preliminary (February, 1999, Version 2.0) AMIC Technology, Inc. A65H73361/A65H83181 Series 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Preliminary Features n n n n n n n n n n n Fast access times: 2.5/3.0/3.5ns 128k x 36 or 256k x 18 organizations CMOS technology Register to register synchronous operation with selftimed late write n Single +3.3V ±5% power supply n Individual byte write and global write HSTL input & output levels Boundary scan(JTAG) IEEE 1149.1 compatible Asynchronous output enable Sleep mode (ZZ) Programmable impedance output drivers JEDEC Standard pinout and boundary scan order 7 x 17 bump plastic ball grid array (PBGA) package General Description The A65H73361 and A65H83181 are 128k words by 36 bits and 256k words by 18 bits late write synchronous 4Mb SRAMS built using high performance CMOS process. The differential clock are used to control the timing of read/write operation and all internal operations are selftimed. The positive edge triggered CK clock input controls all addresses write-enables and Synchronous select and data ins are registered. PRELIMINARY (February, 1999, Version 2.0) The data outs are controlled by the output registers off the next positive clock edge to be updated. The internal write buffer enables write data to be accepted on the rising edge of the clock one cycle after address and control signals. The SRAM uses HSTL I/O interfaces with programmable impedance output drivers allowing the outputs to match the impedance of the circuit traces which reduces signal reflections. 1 AMIC Technology, Inc. A65H73361/A65H83181 Series Pin Configuration A65H73361 A65H83181 1 2 3 4 5 6 7 VDDQ SA5 SA7 NC SA16 SA14 VDDQ A 1 2 3 4 5 6 7 VDDQ SA5 SA7 NC SA16 SA14 VDDQ NC NC SA8 NC SA11 NC NC NC SA6 SA9 VDD SA10 SA15 NC DQ 9 NC VSS ZQ VSS DQ 1 NC NC DQ 12 VSS SS VSS NC DQ 2 VDDQ NC VSS G VSS DQ 4 VDDQ NC DQ 15 NC VSS NC DQ 5 DQ 16 NC VSS NC VSS DQ 8 NC VDDQ VDD Vref VDD Vref VDD VDDQ NC DQ 17 VSS CK VSS NC DQ 7 DQ 14 NC VSS CK SBWa DQ 6 NC VDDQ DQ 13 VSS SW VSS NC VDDQ DQ 11 NC VSS SA0 VSS DQ 3 NC NC DQ 10 VSS SA1 VSS NC DQ 0 NC SA4 M1 VDD M2 SA13 NC NC SA2 SA3 NC SA17 SA12 ZZ VDDQ TMS TDI TCK TDO NC VDDQ A B B NC NC SA8 NC SA11 NC NC C C NC SA6 SA9 VDD SA10 SA15 NC D D DQ 18 DQ 19 VSS ZQ VSS DQ 10 DQ 9 E E DQ 20 DQ 21 VSS SS VSS DQ 12 DQ 11 F F VDDQ DQ 22 VSS G VSS DQ 13 VDDQ G G DQ 23 DQ 24 H DQ 25 DQ 26 SBWC VSS NC NC SBWb VSS DQ 15 DQ 14 H DQ 17 DQ 16 J SBWb J VDDQ VDD Vref VDD Vref VDD VDDQ K K DQ 34 DQ 35 VSS CK VSS DQ 8 DQ 7 L L DQ 32 DQ 33 M VDDQ DQ 31 SBWd CK VSS SW SBWa VSS DQ 6 DQ 5 M DQ 4 VDDQ N N DQ 29 DQ 30 VSS SA0 VSS DQ 3 DQ 2 P P DQ 27 DQ 25 VSS SA1 VSS DQ 1 DQ 0 R R NC SA4 M1 VDD M2 SA12 NC T T NC NC SA3 SA2 SA13 NC ZZ VDDQ TMS TDI TCK TDO NC VDDQ U U PRELIMINARY (February, 1999, Version 2.0) 2 AMIC Technology, Inc. A65H73361/A65H83181 Series Block Diagram SA0-SA17 Latch ZZ SW Register SW Row Decoder SS WR Add Register 2:1 MUX RD Add Register CK 128Kx36 or 256Kx18 Array SW Register Column Decoder Read/Write Amp SBW Latch SBW Register SBW Register Match Write Buffer 2:1 MUX Data Out Registor SS Register SS Register G DQ0 - DQ35 Pin Description SA0-SA17 Address input G Asynchronous output enable (X18 : SA0 - SA17, X36 : SA0 - SA16) DQ0-DQ35 Data I/O SS Synchronous select (X18 : DQ0 - DQ17, X36 : DQ0 - DQ35) CK , CK SW Differential input register clocks M1, M2 For boundary scan purpose Write enable. Global VREP(2) HSTL input reference voltage SBWa Write enable. Byte a (DQ0-DQ8) VDD Power supply (+3.3V) SBWb Write enable. Byte b (DQ9-DQ17) VSS Ground SBWc Write enable. Byte c (DQ18-DQ26) VDDQ Output power supply SBWd Write enable. Byte d (DQ27-DQ35) ZZ Asynchronous sleep mode TMS, TDI, TCK IEEE 1149.1 test inputs(LVTTL levels) ZQ Output driver impedance control TDO IEEE 1149.1 test output(LVTTL level) NC No connect PRELIMINARY (February, 1999, Version 2.0) 3 AMIC Technology, Inc. A65H73361/A65H83181 Series Clock Truth Table SBWa SBWb SBWc SBWd DQ(n) DQ(n+1) MODE K ZZ SS SW LÕ H L L H X X X X X LÕ H L L L L H H H X DIN 0-8 Write Cycle 1st Byte LÕ H L L L H L H H X DIN 9-17 Write Cycle 2nd Byte LÕ H L L L H H L H X DIN 18-26 Write Cycle 3rd Byte LÕ H L L L H H H L X DIN 27-35 Write Cycle 4th Byte LÕ H L L L L L L L X DIN 0-35 Write Cycle ALL Byte LÕ H L L L H H H H X High-Z Abort Write Cycle LÕ H L H X X X X X X High-Z Deselect Cycle X H X X X X X X High-Z High-Z Sleep Mode DOUT 0-35 Read Cycle ALL Bytes Clock Truth Table Operation G DQ Read L DOUT 0-35 Read H High-Z Sleep(ZZ=H) X High-Z Write( SW =L) X DIN Deselect( SS =H) X High-Z PRELIMINARY (February, 1999, Version 2.0) 4 AMIC Technology, Inc. A65H73361/A65H83181 Series Absolute Maximum Ratings* *Comments Power Supply Voltage(VDD) . . . . . . . . . . -0.5V to +4.6V Voltage Relative to GND for any Pin Except VDD(VIN, VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Power Dissipation (PD) . . . . . . . . .. . . . . . . . . . .. . .1.0W Operating Temperature (Topr). . . . . . . . .. . 0°C to 70°C Storage Temperature (Tbias) . . . . . . .. .. . -10°C to 85°C Storage Temperature(Tstg). . . . . . . . . . .-55°C to 125°C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure the absolute maximum rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TJ = 0 to 110°C) Parameter Symbol Min. Typ. Max. Units Notes Supply Voltage VDD 3.15 3.3 3.47 V 1 Output Driver Supply Voltage VDDQ 1.4 1.5 1.6 V 1 Input High Voltage VIH VREF+0.1 - VDDQ+0.3 V 1, 2 Input Low Voltage VIL -0.3 - VREF-0.1 V 1, 3 Input reference Voltage VREF 0.68 0.75 0.90 V 1, 6 Clocks Signal Voltage VIN-CLK -0.3 - VDDQ+0.3 V 1, 4 Differential Clocks Signal Voltage VDIF-CLK 0.1 - VDDQ+0.6 V 1, 5 Clocks Common Mode Voltage VCM-CLK 0.55 - 0.90 V 1 IOUT - 5 8 mA Output Current 1.All voltage reference to VSS. All VDD VDDQ and VSS pins must be connected. 2.VIH(Max)DC = VDD + 0.3V, VIH(Max)AC = VDD + 1.5V (pulse width ≤ 4.0ns). 3.VIL(Min)DC = -0.3V, VIL(Min)AC = -1.5 V (pulse width ≤ 4.0ns). 4.VIN-CLK specifies the maximum allowable DC excursions of each differential clock ( CK , CK ). 5.VDIF-CLK specifies the minimum clock differential voltage required for switching. 6.Peak to Peak AC component superimposed on VREF may not exceed 5% of VREF. PRELIMINARY (February, 1999, Version 2.0) 5 AMIC Technology, Inc. A65H73361/A65H83181 Series DC Electrical Characteristics (TJ = 0 to +110°C, VDD = 3.3V ± 5%) Parameter Symbol Min. Max. Units Notes lDD5 lDD6 lDD7 - TBD mA 1 lDD5 lDD6 lDD7 - TBD mA 1 Power Supply Standby Current (ZZ = VIH, All other inputs = VIH or VIL, Iout =0) Lsbzz - TBD mA 1 ( SS = VIH, ZZ = VIL. All their inputs = VIH or VIL, lOUT = 0 ) lSBss mA 1 Average Power Supply Operating Current-X36 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) Average Power Supply Operating Current-X18 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) Input Leakage Current (VIN = VSS or VDD) lLI - ±1.0 µA Output Leakage Current (VOUT = VSS or VDD, DQ in High = Z) lLO - ±1.0 µA Output High Level Voltage(lOH = -6mA @ VDDQ/2+0.3) VOH VDDQ-.4 VDDQ V 2 Output Low Level Voltage(lOL = +6mA @ VDDQ/2-0.3) VOL VSS VSS+.4 V 2 1. lOUT = Chip Output Current. 2.Minimum Impedance Output Driver. PRELIMINARY (February, 1999, Version 2.0) 6 AMIC Technology, Inc. A65H73361/A65H83181 Series Capacitance (TJ = 0 to +110°C, VDD = 3.3V ± 5%, f = 1MHz) Parameter Symbol Test Condition Max. Units CIN VIN = 0V 3 pF COUT VOUT= 0V 4 pF Symbol Min. Max. Notes AC Input Logic High VIN (ac) TBD AC Input Logic Low VIL (ac) Clock Input Differential Voltage VDIF (ac) VREF Peak to Peak ac Voltage VREF (ac) Input Capacitance Data I/O Capacitance (DQ0-DQ35) AC Input Characteristics Item 3 TBD TBD 3 2 5% VREF (dc) 1 1.The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2.Performance is a function on VIH and VIL levels to clock inputs. 3.See AC input Definition figure on page 7. AC Input Definition VIH(ac) VREF VIL(ac) PRELIMINARY (February, 1999, Version 2.0) 7 AMIC Technology, Inc. A65H73361/A65H83181 Series Programmable Impedance Output Driver DC Electrical Characteristics (TJ = 0 to +110°C, VDD = 3.3V ± 5%) Parameter Symbol Min. Max. Units Notes Output High Level Voltage VOH VDDQ/2 VDDQ V 1 Output Low Level Voltage VOL VSS VDDQ/2 V 2 1.lOH = (VDDQ/2)/(RQ/5) 7.5% @ VOH = VDDQ/2 For :150Ω ≤ RQ ≤ 350Ω 2.lOL = (VDDQ/2)/(RQ/5) 7.5% @ VOL = VDDQ/2 For :150Ω ≤ RQ ≤ 350Ω AC Test Conditions (TJ = 0 to +110°C, VDD = 3.3V ± 5%, VDDQ = 1.5V) Parameter Symbol Conditions units Output High Level Voltage VIH 1.25 V Output Low Level Voltage VIL 0.25 V VREF 0.75 V VDIF-CLK 0.75 V Input Rise Time TR 0.5 ns Input Fall Time TF 0.5 ns 0.75 V Differential Cross Point V Input Reference Voltage Differential Clocks Voltage I/O Signals Reference Level Clocks Reference level Output Load Conditions Notes 1 1.See AC Test Loading figure on page 8. AC Test Loading 0.75V VDDO/2 50Ω VREF DEVICE UNDER TEST 50Ω 250Ω ZQ PRELIMINARY (February, 1999, Version 2.0) 8 AMIC Technology, Inc. A65H73361/A65H83181 Series AC Characteristics (TJ = 0 to +110°C, VDD = 3.3V ± 5%) Parameter Symbol -5 -6 -7 Units Min. Max. Min. Max. Min. Max. Notes Cycle Time tKHKH 5 - 6.0 - 7.0 - ns Clock High Pulse Width tKHKL 1.5 - 1.5 - 1.5 - ns Clock Low Pulse Width tKLKH 1.5 - 1.5 - 1.5 - ns Clock to Output Valid tKHQV - 2.5 3.0 - 3.5 ns 1 Address Setup Time tAVKH 0.5 - 0.5 - 0.5 - ns 4 Address Hold Time tKHAX 1.0 - 1.0 - 1.0 - ns 4 Sync Select Setup Time tSVKH 0.5 - 0.5 - 0.5 - ns 4 Sync Select Hold Time tKHSX 1.0 - 1.0 - 1.0 - ns 4 Write Enables Setup Time tWVKH 0.5 - 0.5 - 0.5 - ns 4 Write Enables Hold Time tKHWX 1.0 - 1.0 - 1.0 - ns 4 Data In Setup Time tDVKH 0.5 - 0.5 - 0.5 - ns 4 Data In Hold Time tKHDX 1.0 - 1.0 - 1.0 - ns 4 Data Out Hold Time tKHQX 0.5 - 0.5 - 0.5 - ns 1 Clock High to Output High-z tKHQZ - 2.5 - 3.0 - 3.5 ns 1, 2 Clock high to Output Active tXHQX4 1.0 - 1.0 - 1.0 - ns 1, 2 Output Enable to High-z tGHQZ - 2.5 3.0 - 3.5 ns 1, 2 Output Enable to Low-z tGLQX 0.5 - 0.5 - 0.5 - ns 1, 2 Output Enable to Output Valid tGLQV - 2.5 - 3.0 - 3.5 ns 1 Output Enable Setup Time tGHKH 0.5 - 0.5 - 0.5 - ns 1, 3 Output Enable Hold Time tKHGX 1.5 - 1.5 - 1.5 - ns 1, 3 Sleep Mode Recovery Time tZZR 5 - 6 - 7 - ns Sleep Mode Enable Time tZZE - 5 - 6 - 7 ns 1.See AC Test Loading figure on page 8. 2.Transitions are measured ± 200mV from steady state voltage. 3.Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver Updates during High-z. 4.Inuse conditions VIH, VIL, Trise, Tfall of inputs must be withim 20% of VIH, VIL, Trise, Tfall of Clock. PRELIMINARY (February, 1999, Version 2.0) 9 AMIC Technology, Inc. A65H73361/A65H83181 Series Timing Diagram (Read and Deselect Cycles) tKLKH tKHKL tKHKH CK tAVKH SA A1 A2 A3 A3 A4 tKHAX tKHSX SS tSVKH tWVKH SW tKHWX tGLQV G tGHQZ tKHQX tKHQZ DQ Q1 tGLQX PRELIMINARY (February, 1999, Version 2.0) Q2 Q3 Q4 tKHQV tKHQX4 10 tKHQV AMIC Technology, Inc. A65H73361/A65H83181 Series Timing Diagram (Read Write Cycles) tKLKH tKHKL tKHKH CK tAVKH SA A1 A2 A3 A2 A4 tKHAX tSVKH SS tKHSX tKHWX tXHWX SW tWVKH tWVKH tXHWX tKHWX SBW tWVKH tWVKH G tGHQZ tKHQZ DQ tKHDX Q1 tKHQV D2 Q3 tKHQV tKHQX4 tDVKH Q2 tDVKH D4 tKHDX NOTES: 1.D2 is the input data write in memory location A2. 2.Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address. PRELIMINARY (February, 1999, Version 2.0) 11 AMIC Technology, Inc. A65H73361/A65H83181 Series Timing Diagram (Sleep Mode) tKHKH CK zz tZZE tZZR DQ PRELIMINARY (February, 1999, Version 2.0) 12 AMIC Technology, Inc. A65H73361/A65H83181 Series IEEE 1149.1 TAP AND BOUNDARY SCAN The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary Scan register, Bypass register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. Signal List l TCK : Test Clock l TMS : Test Mode Select l TDI : Test Data In l TDO : Test Data Out Caution: TCK, TMS, TDI must be tied down, even if JTAG is not used. JTAG Recommended DC Operating Conditions (TJ = 0 to 110 °C) Parameter Symbol Min. Typ. Max. Units Notes JTAG Input High Voltage VIH1 2.2 - VDD + 0.3 V 1 JTAG Input Low Voltage VIL1 -03 - 0.8 V 1 JTAG Output High Level VOH1 2.4 - - V 1,2 JTAG Output Low Level VOL1 - - 0.4 V 1,3 1. All JTAG Inputs/Outputs are LVTTL Compatible only. 2. IOH1 = -8mA at 2.4V. 3. IOL1 = +8mA at 0.4V. JTAG Recommended DC Operating Conditions (TJ = 0 to 110 °C) Parameter Symbol Conditions Units Input Pulse High Level VIH1 3.0 V Input Pulse Low Level VIL1 0.0 V Input Rise Time TR1 2.0 ns Input Fall Time TF1 2.0 ns 1.5 V Input and Output Timing Reference Level Notes 1 1. See AC Test Loading on page 8. PRELIMINARY (February, 1999, Version 2.0) 13 AMIC Technology, Inc. A65H73361/A65H83181 Series JTAG AC Characteristics (TJ = 0 to 110 °C, VDD = 3.3V ± 5%) Parameter Symbol Min. Max. Units TCK Cycle Time tTHTH 20 - ns TCK High Pulse Width tTHTL 7 - ns TCK Low Pulse Width tTLTH 7 - ns TMS Setup tMVTH 4 - ns TMS Hold tTHMX 4 - ns TDI Setup tDVTH 4 - ns TDI Hold tTHDX 4 - ns TCK Low to Valid Data tTLOV - 7 ns Notes 1 1. See AC Test Loading on page 8. JTAG Timing Diagram tTHTL tTLTH tTHTH TCK tTHMX TMS tMVTH tTHDX TDI tDVTH TDO tTLOV PRELIMINARY (February, 1999, Version 2.0) 14 AMIC Technology, Inc. A65H73361/A65H83181 Series Scan Register Definition Register Name Bit Size X18 Bit Size X 36 Instruction Bypass 3 1 3 1 ID 32 32 Boundary Scan* 51 70 * The Boundary Scan chain consists of the following bits : •36 or 18 bits for Data Inputs Depending on X 18 or X 36 Configuration •15 bits for SA0 - SA14 for X 36, 16 bits for SA0 - SA15 for X 18 •4 bits for SBWa - SBWd in X 36, 2 bits for SBWa and SBWb X 18 •9 bits for CK, CK , ZQ, SS , G , SW , ZZ, M1 and M2 •6 bits for Place Holders * CK and CK clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used for Boundary Scan sampling. ID Register Definition Field Bit Number and Description Device Density Revision Number Vender Definition Manufacture JEDEC Start and Configuration (31 : 28) (17 : 12) Code (11 : 1) Bit (0) (27 : 18) Part 256K X 18 128K X 36 0001 0001 100 000 0110 011 100 1101 000001 100001 000 101 111 11 000 101 111 11 1 1 Instruction Set Code Instruction Notes 000 001 SAMPLE-Z IDCODE 1 1 010 SAMPLE-Z 1 011 PRIVATE 3 100 SAMPLE 4 101 PRIVATE 3 110 PRIVATE 3 111 BYPASS 3 1. Places DQs in High-Z in order to sample all input data regardless of the other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to Vss when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the Shift DR state. 4. SAMPLE instruction does not place DQs in High-Z List of IEEE 1149.1 standard violations : • 7.2.1.b,e • 7.7.1.a-f • 10.1.1.b,e • 10.7.1.a-d • 6.1.1.d PRELIMINARY (February, 1999, Version 2.0) 15 AMIC Technology, Inc. A65H73361/A65H83181 Series Boundary Scan Order (X 36) Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 25 DQ13 6F 49 DQ26 2H 2 SA1 4P 26 DQ11 7E 50 DQ25 1H 3 SA2 4T 27 DQ12 6E 51 SBWc 3G 4 SA12 6R 28 DQ9 7D 52 ZQ 4D 5 SA13 5T 29 DQ10 6D 53 SS 4E 6 ZZ 7T 30 SA14 6A 54 NC 4G 7 DQ1 6P 31 SA15 6C 55 NC 4H 8 DQ0 7P 32 SA10 5C 56 SW 4M 9 DQ3 6N 33 SA16 5A 57 SBWd 3L 10 DQ2 7N 34 NC 6B 58 DQ34 1K 11 DQ4 6M 35 SA11 5B 59 DQ35 2K 12 DQ6 6L 36 SA8 3B 60 DQ32 1L 13 DQ5 7L 37 NC 2B 61 DQ33 2L 14 DQ8 6K 38 SA7 3A 62 DQ31 2M 15 DQ7 7K 39 SA9 3C 63 DQ29 1N 16 SBWa 5L 40 SA6 2C 64 DQ30 2N 17 CK 4L 41 SA5 2A 65 DQ27 1P 18 CK 4K 42 DQ19 2D 66 DQ28 2P 19 G 4F 43 DQ18 1D 67 SA3 3T 20 SBWb 5G 44 DQ21 2E 68 SA4 2R 21 DQ16 7H 45 DQ20 1E 69 SA0 4N 22 DQ17 6H 46 DQ22 2F 70 M1 3R 23 DQ14 7G 47 DQ24 2G 24 DQ15 6G 48 DQ23 1G PRELIMINARY (February, 1999, Version 2.0) 16 AMIC Technology, Inc. A65H73361/A65H83181 Series Boundary Scan Order (X 18) Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 27 NC 2B 2 SA12 6T 28 SA7 3A 3 SA1 4P 29 SA9 3C 4 SA13 6R 30 SA6 2C 5 SA17 5T 31 SA5 2A 6 ZZ 7T 32 DQ9 1D 7 DQ0 7P 33 DQ12 2E 8 DQ3 6N 43 DQ15 2G 9 DQ6 6L 35 DQ16 1H 10 DQ7 7K 36 SBWb 3G 11 SBWa 5L 37 ZQ 4D 12 CK 4L 38 SS 4E 13 CK 4K 39 NC 4G 14 G 4F 40 NC 4H 15 DQ8 6H 41 SW 4M 16 DQ5 7G 42 DQ17 2K 17 DQ4 6F 43 DQ14 1L 18 DQ2 7E 44 DQ13 2M 19 DQ1 6D 45 DQ11 1N 20 SA14 6A 46 DQ10 2P 21 SA15 6C 47 SA3 3T 22 SA10 5C 48 SA4 2R 23 SA16 5A 49 SA0 4N 24 NC 6B 50 SA2 2T 25 SA11 5B 51 M1 3R 26 SA8 3B PRELIMINARY (February, 1999, Version 2.0) 17 AMIC Technology, Inc. A65H73361/A65H83181 Series TAP Controller State Machine 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR Select IR 0 1 0 1 Capture DR Capture IR 0 0 0 Shift DR Shift IR 1 1 1 Exit1 DR Exit1 IR 0 0 Pause DR Pause IR 1 Exit2 IR 0 0 1 1 Update DR Update IR 1 0 (February, 1999, Version 2.0) 0 1 Exit2 DR PRELIMINARY 0 1 0 1 1 18 0 AMIC Technology, Inc. A65H73361/A65H83181 Series Ordering Information Part Number Organization Speed Package A65H83181P-5 256K x 18 2.5ns Access / 5 ns Cycle 7 x 17 PBGA A65H83181P-6 256K x 18 3.0ns Access / 6 ns Cycle 7 x 17 PBGA A65H83181P-7 256K x 18 3.5ns Access / 7 ns Cycle 7 x 17 PBGA A65H73361P-5 128K x 36 2.5ns Access / 5 ns Cycle 7 x 17 PBGA A65H73361P-6 128K x 36 3.0ns Access / 6 ns Cycle 7 x 17 PBGA A65H73361P-7 128K x 36 3.5ns Access / 7 ns Cycle 7 x 17 PBGA PRELIMINARY (February, 1999, Version 2.0) 19 AMIC Technology, Inc. A65H73361/A65H83181 Series Package Information PIN #1 14.00±0.10 1.96 (Min) 2.36 (Max) 7 6 5 4 3 2 1 -A- A B C D E F G H J K L M N P R T U 20.32±0.10 1.27 TYP. 20.00±0.05 22.00±0.10 30°±2 1.00±0.05 0.60±0.10 0.30 S C A S B S 0.10 S C 1.56 SEATING PLANE -C- NOTE: 1. ALL DIMENSIONS ARE MILLIMETERS. 2. DETAILS OF MOLDED PLASTIC BODY MAY VARY FROM THAT SHOWN. 0.56 D 7.62±0.10 119X φ0.80±0.1 12.00±0.05 0.15 C -B- 1.270 TYP. PRELIMINARY (February, 1999, Version 2.0) 20 AMIC Technology, Inc.